V1 | smoke | keymgr_smoke | Smoke test accessing a major datapath within the keymgr.
Test operations (advance, gen-id and gen-sw-out) in every state
Stimulus:
- Go through state from
StReset to StDisabled .
- Issue gen-id, gen-sw-output operation in each state, including invalid operations in
states other than normal operating states (
StCreatorRootKey , StOwnerIntKey and
StOwnerRootKey ).
- Randomize
CDI_SEL and DEST_SEL .
- Use default/fixed values for HW/SW inputs.
Checks:
- Check STATUS reg for each operation.
- Check interrupts
op_done is triggered when operation is done.
- Check
err and alert recov_operation_err are triggered after invalid operation.
- Check KMAC key, KMAC data and output SW data for correctness.
- For invalid operations, check KMAC key, KMAC data and output SW data don't match to
any of saved meaningful data, which are collected from valid operations. This
checking method is also applied to other error cases.
|
V1 | random | keymgr_random | Extend from smoke to randomize all SW input data
- Fully randomize SW inputs: rom_ext_desc_, software_binding_, salt_, max__key_ver,
*_key_ver_regwen.
- Randomize key_version any value less than max_*_key_ver, to avoid triggerring
invalid_kmac_input error.
- Fully randomize HW inputs from flash, otp and life cycle.
- Randomize *sw_binding_regwen. Ensure this gates the *_sw_binding and it will
be cleared after a successful advance operation.
Most of other sequences are derived from this to have similar init and sequence.
Stimulus and checks are the same as smoke. |
V1 | csr_hw_reset | keymgr_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
- Write all CSRs with a random value.
- Apply reset to the DUT as well as the RAL model.
- Read each CSR and compare it against the reset value.
it is mandatory to replicate this test for each reset that affects
all or a subset of the CSRs.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
|
V1 | csr_rw | keymgr_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
- Loop through each CSR to write it with a random value.
- Read the CSR back and check for correctness while adhering to its
access policies.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
|
V1 | csr_bit_bash | keymgr_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
- Walk a 1 through each CSR by flipping 1 bit at a time.
- Read the CSR back and check for correctness while adhering to its
access policies.
- This verify that writing a specific bit within the CSR did not affect
any of the other bits.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
|
V1 | csr_aliasing | keymgr_csr_aliasing | Verify no aliasing within the CSR address space.
- Loop through each CSR to write it with a random value
- Shuffle and read ALL CSRs back.
- All CSRs except for the one that was written in this iteration should
read back the previous value.
- The CSR that was written in this iteration is checked for correctness
while adhering to its access policies.
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
- Shuffle the list of CSRs first to remove the effect of ordering.
|
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
- Run csr_rw sequence to randomly access CSRs
- If memory exists, run mem_partial_access in parallel with csr_rw
- Randomly issue reset and then use hw_reset sequence to check all CSRs
are reset to default value
- It is mandatory to run this test for all available interfaces the
CSRs are accessible from.
|
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw
keymgr_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
- Randomly access all CSRs
- Test when regwen CSR is set, its corresponding lockable CSRs become
read-only registers
Note:
- If regwen CSR is HW read-only, this feature can be fully tested by common
CSR tests - csr_rw and csr_aliasing.
- If regwen CSR is HW updated, a separate test should be created to test it.
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | cfgen_during_op | keymgr_cfg_regwen | cfg_regwen is RO reg and it gates bunch of write access of other registers, which is
not tested in common CSR tests.
Stimulus and checks:
Test command and reg access gated by cfg_regwen is ignored during operation. |
V2 | sideload | keymgr_sideload
keymgr_sideload_kmac
keymgr_sideload_aes
keymgr_sideload_otbn | Keymgr contains HW sideload interfaces to output keys for KMAC, AES, OTBN.
Stimulus:
- Generate a keymgr output to HW sideload interface, exercising all the sideload
interfaces.
- Randomly program any value to Sideload_clear after any operation.
Checks:
Verify the sideload data and status for correctness. |
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | Stimulus and checks:
Directly go to StDisabled from any state and check StDisabled is entered correctly. |
V2 | lc_disable | keymgr_lc_disable | Life cycle can disable keymgr and let keymgr wipe secret immediately.
Stimulus:
Test life cycle disables keymgr in any state.
Checks:
- If keymgr is not initialized, check it can't be initialized until life cycle enables
keymgr.
- If keymgr is in a valid state after
StReset , key output to KMAC is wiped immediately
and SW output will be invalid after OP is done.
- If keymgr in disabled state, check the behavior is consistent with normal behavior.
|
V2 | kmac_error_response | keymgr_kmac_rsp_err | Verify keymgr behavior on error response received from KMAC after sending data to
it.
Stimulus:
- Drive error from KMAC interface when VALID is high.
- Or drive all 0s or 1s as KMAC input digest data
Checks:
Same as above entry - "invalid_cmd". |
V2 | invalid_sw_input | keymgr_sw_invalid_input | Verify keymgr behavior with invalid key version.
Stimulus:
Randomize KEY_VERSION and MAX_*_VER registers.
Checks:
when KEY_VERSION > MAX_*_VER
- Check interrupts
err is triggered.
- Check alert
recov_operation_err is triggered and err_code is INVALID_KMAC_INPUT .
- Check KMAC output key is corrupted and working state remains the same.
|
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | Verify keymgr behavior with invalid data patterns.
Stimulus:
- Drive all 0s or 1s on any of these inputs - flash seeds, otp_key, diversification ID,
Rom digest etc.
- Make sure all cases are covered in
csr_debug_cg .
Checks:
- Check interrupts
err is triggered.
- Check alert
recov_operation_err is triggered and err_code is INVALID_KMAC_DATA .
- Check SW output isn't updated and working state remains the same.
|
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | Verify keymgr behavior with invalid data patterns.
Stimulus:
Create these 2 direct tests:
- Sync (transactional) fault occurs followed by async (non-transactional) fault.
- Async (non-transactional) fault occurs followed by sync (transactional) fault.
Checks:
- Check interrupts
err is triggered.
- Check alert
fatal_fault_err is triggered.
- Check
fault_status is updated correctly.
|
V2 | stress_all | keymgr_stress_all |
- Combine above sequences in one test to run sequentially, except csr sequence and
keymgr_cfg_regwen (requires zero_delays).
- Randomly add reset between each sequence.
|
V2 | intr_test | keymgr_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
- Enable a random set of interrupts by writing random value(s) to
intr_enable CSR(s).
- Randomly "turn on" interrupts by writing random value(s) to intr_test
CSR(s).
- Read all intr_state CSR(s) back to verify that it reflects the same value
as what was written to the corresponding intr_test CSR.
- Check the cfg.intr_vif pins to verify that only the interrupts that were
enabled and turned on are set.
- Clear a random set of interrupts by writing a randomly value to intr_state
CSR(s).
- Repeat the above steps a bunch of times.
|
V2 | alert_test | keymgr_alert_test | Verify common alert_test CSR that allows SW to mock-inject alert requests.
- Enable a random set of alert requests by writing random value to
alert_test CSR.
- Check each
alert_tx.alert_p pin to verify that only the requested alerts
are triggered.
- During alert_handshakes, write
alert_test CSR again to verify that:
If alert_test writes to current ongoing alert handshake, the alert_test
request will be ignored.
If alert_test writes to current idle alert handshake, a new alert_handshake
should be triggered.
- Wait for the alert handshakes to finish and verify
alert_tx.alert_p pins
all sets back to 0.
- Repeat the above steps a bunch of times.
|
V2 | tl_d_oob_addr_access | keymgr_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | keymgr_tl_errors | Drive unsupported requests via TL interface and verify correctness of response
/ behavior. Below error cases are tested bases on the
TLUL spec
- TL-UL protocol error cases
- invalid opcode
- some mask bits not set when opcode is
PutFullData
- mask does not match the transfer size, e.g.
a_address = 0x00 , a_size = 0 ,
a_mask = 'b0010
- mask and address misaligned, e.g.
a_address = 0x01 , a_mask = 'b0001
- address and size aren't aligned, e.g.
a_address = 0x01 , a_size != 0
- size is greater than 2
- OpenTitan defined error cases
- access unmapped address, expect
d_error = 1 when devmode_i == 1
- write a CSR with unaligned address, e.g.
a_address[1:0] != 0
- write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
- write a memory with
a_mask != '1 when it doesn't support partial accesses
- read a WO (write-only) memory
- write a RO (read-only) memory
- write with
instr_type = True
|
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset
keymgr_csr_rw
keymgr_csr_aliasing
keymgr_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one
transaction outstanding within the TL device. Also, verify one outstanding when back-
to-back accesses are made to the same address. |
V2 | tl_d_partial_access | keymgr_csr_hw_reset
keymgr_csr_rw
keymgr_csr_aliasing
keymgr_same_csr_outstanding | Access CSR with one or more bytes of data.
For read, expect to return all word value of the CSR.
For write, enabling bytes should cover all CSR valid fields. |
V2S | sec_cm_additional_check | keymgr_sec_cm | Verify the outcome of injecting faults to security countermeasures.
Stimulus:
As mentioned in prim_count_check , prim_one_hot_check and prim_fsm_check .
Checks:
- Besides checking alert and
fault_status , issue an operation after injecting faults,
then ensure that op_status is failed and design enters StInvalid .
|
V2S | tl_intg_err | keymgr_tl_intg_err
keymgr_sec_cm | Verify that the data integrity check violation generates an alert.
- Randomly inject errors on the control, data, or the ECC bits during CSR accesses.
Verify that triggers the correct fatal alert.
- Inject a fault at the onehot check in
u_reg.u_prim_reg_we_check and verify the
corresponding fatal alert occurs
|
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | Verify shadowed registers' update error.
- Randomly pick a shadowed register in the DUT.
- Write it twice with different values.
- Verify that the update error alert is triggered and the register value remains
unchanged.
- Verify the update_error status register field is set to 1.
- Repeat the above steps a bunch of times.
|
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | Verify reading a shadowed register will clear its staged value.
- Randomly pick a shadowed register in the DUT.
- Write it once and read it back to clear the staged value.
- Then write it twice with the same new value (but different from the previous step).
- Read it back to verify the new value and ensure that the update error alert did not
trigger.
- Verify the update_error status register field remains the same value.
- Repeat the above steps a bunch of times.
|
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | Verify shadowed registers' storage error.
- Randomly pick a shadowed register in the DUT.
- Backdoor write to shadowed or committed flops to create a storage fatal alert.
- Check if fatal alert continuously fires until reset.
- Verify that all other frontdoor write attempts are blocked during the storage error.
- Verify that storage_error status register field is set to 1.
- Reset the DUT.
- Read all CSRs to ensure the DUT is properly reset.
- Repeat the above steps a bunch of times.
|
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | Verify toggle shadowed_rst_n pin can trigger storage error.
- Randomly drive
shadowed_rst_n pin to low or rst_n pin to low.
- check if any registers have been written before the reset. If so check if storage
error fatal alert is triggered.
- Check status register.
- Drive
shadowed_rst_n pin or rst_n pin back to high.
- If fatal alert is triggered, reset the DUT.
- Read all CSRs to ensure the DUT is properly reset.
- Repeat the above steps a bunch of times.
|
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | Run shadow_reg_update_error sequence in parallel with csr_rw sequence.
- Randomly select one of the above sequences.
- Apply csr_rw sequence in parallel but disable the
csr_access_abort to ensure all
shadowed registers' write/read to be executed without aborting.
- Repeat the above steps a bunch of times.
|
V2S | prim_count_check | keymgr_sec_cm | Verify that violating prim_count counter properties generate a fatal alert.
Stimulus:
- At the falling edge (non-active edge), force the counter to a different value than
expected.
- Randomly force the counter back to a normal value to ensure the error is latched and
won't go away until reset.
- Within the next few cycles, the violation of hardened counter property should
generate a fatal alert.
- Repeat for ALL prim_count instances in the DUT.
Checks:
- Check that fatal alert is triggered.
- Check that err_code/fault_status is updated correctly and preserved until reset.
- Verify any operations that follow fail (as applicable).
|
V2S | prim_fsm_check | keymgr_sec_cm | Verify that entering to an undefined state generates a fatal alert.
Stimulus:
- Backdoor force the FSM to any of the undefined values.
- Randomly force the FSM back to a defined state to ensure the error is latched and
won't go away until reset.
- Within the next few cycles, the FSM landing in an invalid state should trigger a
fatal alert.
- Repeat for ALL prim_fsm instances in the DUT.
Checks:
- Check that fatal alert is triggered.
- Check that err_code/fault_status is updated correctly and preserved until reset.
- Verify any operations that follow fail (as applicable).
|
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | Verify the countermeasure(s) CONFIG.SHADOW. |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | Verify the countermeasure(s) OP.CONFIG.REGWEN."
X-ref'ed with cfgen_during_op . |
V2S | sec_cm_reseed_config_regwen | keymgr_random
keymgr_csr_rw | Verify the countermeasure(s) RESEED.CONFIG.REGWEN.
X-ref'ed with random . |
V2S | sec_cm_sw_binding_config_regwen | keymgr_random
keymgr_csr_rw | Verify the countermeasure(s) SW_BINDING.CONFIG.REGWEN.
Test that sw_binding_regwen gates the *_sw_binding and
sw_binding_regwen will be cleared after a successful advance operation.
X-ref'ed with random . |
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random
keymgr_csr_rw | Verify the countermeasure(s) MAX_KEY_VER.CONFIG.REGWEN.
X-ref'ed with random . |
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI.
X-ref'ed with lc_disable . |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | Verify the countermeasure(s) CONSTANTS.CONSISTENCY.
X-ref'ed with invalid_hw_input . |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | Verify the countermeasure(s) INTERSIG.CONSISTENCY.
Test otp diversification input with all 0s or 1s.
X-ref'ed with invalid_hw_input . |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | Verify the countermeasure(s) HW.KEY.SW_NOACCESS.
The CSRs sw_share*_output are checked with expected values, which
should never match to HW sideload keys. |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | Verify the countermeasure(s) OUTPUT_KEYS.CTRL.REDUN.
- Randomly advance to a functional state and start a sideload operation.
- Flip either data_sw_en or data_valid.
- Read sw_share* for check:
- if hw_key_sel is flipped but data_sw_en is not, it doesn't match either the
previously flopped value or the sideload value.
- if hw_key_sel is not flipped but data_en is, you should see the previous value.
|
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | Verify the countermeasure(s) CTRL.FSM.SPARSE. |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | Verify the countermeasure(s) DATA.FSM.SPARSE. |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | Verify the countermeasure(s) CTRL.FSM.LOCAL_ESC.
X-ref'ed with sec_cm_additional_check . |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | Verify the countermeasure(s) CTRL.FSM.CONSISTENCY.
- Set
ral.control_shadowed to OpDisable, so that no Advance or Generate operation
is selected.
- Force internal
tb.dut.u_ctrl.adv_en_o or tb.dut.u_ctrl.gen_en_o to 1.
- Check the fatal alert is triggered and
fault_status.ctrl_fsm_chk is set.
|
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | Verify the countermeasure(s) CTRL.FSM.GLOBAL_ESC.
X-ref'ed with lc_disable . |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | Verify the countermeasure(s) CTRL.CTR.REDUN. |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | Verify the countermeasure(s) KMAC_IF.FSM.SPARSE. |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | Verify the countermeasure(s) KMAC_IF.CTR.REDUN. |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | Verify the countermeasure(s) KMAC_IF_CMD.CTRL.CONSISTENCY.
- Inject one of these faults:
- Verify violation of $onehot0 property of the ctrl bits leads to a fault:
- Force {u_ctrl.adv_en_o, u_ctrl.id_en_o, u_ctrl.gen_en_o} to a non-onehot and
non-zero value.
- Verify the modification of the ctrl bits during an active operation leads to a fault:
- Start a valid operation, then force {u_ctrl.adv_en_o, u_ctrl.id_en_o, u_ctrl.gen_en_o}
to a different onehot value during the operation. This simulates that an operation
is flipped to another operation before it finishes.
- Check the fatal alert is triggered and
fault_status.cmd is set.
|
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | Verify the countermeasure(s) KMAC_IF_DONE.CTRL.CONSISTENCY.
- Set
kmac_data_i.done when it's not in a valid done period.
- Valid done period is between dut sending out the last data and kmac returning
a response with
done .
- Check the fatal alert is triggered and
fault_status.kmac_done is set.
|
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | Verify the countermeasure(s) RESEED.CTR.REDUN. |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | Verify the countermeasure(s) SIDE_LOAD_SEL.CTRL.CONSISTENCY.
- Clear all sideload keys, and issue a sideload operation.
- Force
u_sideload_ctrl.valids to a different and none-zero value, so that it enables
more sideload interfaces than expected.
- Check the fatal alert is triggered and
fault_status.side_ctrl_sel is set.
|
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | Verify the countermeasure(s) SIDELOAD_CTRL.FSM.SPARSE. |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | Verify the countermeasure(s) CTRL.KEY.INTEGRITY.
- Flip up to 2 bits of the internal key (u_ctrl.key_state_q).
- Check the fatal alert is triggered and
fault_status.key_ecc is set.
|
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset.
After reset is asserted, the test will read and check all valid CSR registers. |