Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module uart has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO

Pin nameDirectionDescription
rxinputSerial receive bit
txoutputSerial transmit bit

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription


Interrupt NameTypeDescription
tx_watermarkStatusraised if the transmit FIFO is past the high-water mark.
rx_watermarkStatusraised if the receive FIFO is past the high-water mark.
tx_doneEventraised if the transmit FIFO has emptied and no transmit is ongoing.
rx_overflowEventraised if the receive FIFO has overflowed.
rx_frame_errEventraised if a framing error has been detected on receive.
rx_break_errEventraised if break condition has been detected on receive.
rx_timeoutEventraised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.
rx_parity_errEventraised if the receiver has detected a parity error.
tx_emptyStatusraised if the transmit FIFO is empty.

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure IDDescription
UART.BUS.INTEGRITYEnd-to-end bus integrity scheme.