Registers

Summary of the regs interface’s registers

ALERT_TEST

Alert Test Register

• Offset: 0x0
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}

LATE_DEBUG_ENABLE_REGWEN

Lock bit for LATE_DEBUG_ENABLE register.

• Offset: 0x4
• Reset default: 0x1
• Reset mask: 0x1

Fields

{"reg": [{"name": "LATE_DEBUG_ENABLE_REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 260}}

LATE_DEBUG_ENABLE

Debug enable register.

If the device is in the DEV lifecycle state and the DIS_RV_DM_LATE_DEBUG_IN_DEV has been programmed to kMuBi8False (or an invalid value), the RV_DM gating mechanisms are by default not ungated until SW writes kMuBi32True to this register.

This can be leveraged to implement a “late debug enable in DEV” policy, whereby ROM_EXT first locks out any sensitive areas and functionalities of the device before enabling debug access via RV_DM.

This register can be locked out via LATE_DEBUG_ENABLE_REGWEN.

This register does not have any effect in the following cases:

• If the device is in a DFT-enabled life cycle state (TEST_UNLOCKED*, RMA)
• If the device is in the DEV life cycle state and DIS_RV_DM_LATE_DEBUG_IN_DEV has been programmed to kMuBi8True
• If the device is in a life cycle state where hardware debugging is disabled (TEST_LOCKED*, PROD*, invalid states).
• Offset: 0x8
• Reset default: 0x69696969
• Reset mask: 0xffffffff
• Register enable: LATE_DEBUG_ENABLE_REGWEN

Fields

{"reg": [{"name": "LATE_DEBUG_ENABLE", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

Summary of the mem interface’s registers

HALTED

Written by a hart whenever it enters debug mode.

A hart entering debug mode must write its ID to this address to indicate that it has halted. When the debug module triggers a debug mode (aka halt) request to the hart, the hart will jump to the debug ROM. In that debug ROM, the hart must write its ID here to acknowledge completion of the request. When the write is received, the debug module will record that the hart is halted in its status register. In addition, the debug module may begin to accept abstract commands that run on that hart.

Note that this write upon entering debug mode is also important for indicating that a sequence of debug mode instructions completed. In that case, the hart would write to this address while it was already halted.

• Offset: 0x100
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "HALTED", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

GOING

Written by a hart to acknowledge a command.

A hart that receives an abstract command (indicated by its corresponds FLAGS register) must write to this address to acknowledge it received the command. The value written is unused, but it is conventionally 0.

Upon receiving the write, the debug module will reset the GO field in the selected hart’s FLAGS register. The debug module will transition to a state where it awaits the write to HALTED to indicate the command has completed.

• Offset: 0x108
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "GOING", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

RESUMING

Written by a hart to acknowledge a resume request.

A hart that receives the command to resume from debug mode (via the RESUME flag in its FLAGS register) must write its ID to this address.

This write tells the debug module that the command has been acknowledged, and the hart is no longer halted.

• Offset: 0x110
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "RESUMING", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}

EXCEPTION

An exception was triggered while the core was in debug mode.

• Offset: 0x118
• Reset default: 0x0
• Reset mask: 0x1

Fields

{"reg": [{"name": "EXCEPTION", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}}

WHERETO

A jump instruction the hart executes to begin a command.

When a debugger sends an abstract command to the debug module, the debug module indicates the instruction to run here, which is invariably a jump. The hart receiving the command must execute the instruction at this address after acknowledging the command with the write to GOING.

Similarly, when a debugger requests that a hart resume, the debug module supplies a jump instruction to execute here. In the resume request case, the hart must execute the indicated instruction after acknolwedging the request with the write to RESUMING.

• Offset: 0x300
• Reset default: 0x0
• Reset mask: 0xffffffff

Fields

{"reg": [{"name": "WHERETO", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ABSTRACTCMD

A ROM containing instructions for implementing abstract commands.

The hart executes these instructions at the debug modules behest. The debug module’s jump instruction at WHERETO will land here, except for the AccessRegister command with the “postexec” bit set and the “transfer” bit unset. See the RISC-V Debug Specification for more information on the encoding of abstract commands.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "ABSTRACTCMD", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

PROGRAM_BUFFER

A buffer for the debugger to write small debug mode programs.

The hart may run these programs by command from the debugger. See the RISC-V Debug Specification for more information about the Program Buffer and how it is used with abstract commands and the “postexec” bit.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "PROGRAM_BUFFER", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

DATAADDR

Message Registers for passing arguments and/or return values for abstract commands.

See the RISC-V Debug Specification for more information about Message Registers and their relationship to abstract commands.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "DATAADDR", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

FLAGS

Flags indicating what a hart in debug mode should do.

These flags are how a debug module signals whether a hart should execute an abstract command, resume from debug mode, or remain idle.

Each hart has its own FLAGS register that is a single byte. Bit 0 is the GO flag, indicating a request for the selected hart to execute the command. Bit 1 is the RESUME flag, indication a request for the selected hart to resume from halt/ debug mode. The other bits are reserved.

The hart finds its own FLAGS register by taking the base address of this group and adding the hart’s ID to the byte address.

These are written by the debug module. When a selected hart writes the GOING register, the corresponding GO flag is cleared. When a selected hart writes the RESUMING register, the corresponding RESUME flag is cleared.

• Reset default: 0x0
• Reset mask: 0xffffffff

Instances

Fields

{"reg": [{"name": "FLAGS", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}

ROM

Access window into the debug ROM.

• Word Aligned Offset Range: 0x800to0xffc
• Size (words): 512
• Access: ro
• Byte writes are not supported.

Summary of the dbg interface’s registers

dbg

Access window to DM CSRs.

• Word Aligned Offset Range: 0x0to0x1fc
• Size (words): 128
• Access: rw
• Byte writes are not supported.