Testplan

Testpoints

Stage V1 Testpoints

`smoke`

Test: lc_ctrl_smoke

Smoke test accessing lc_ctrl state transition datapath.

Stimulus:

Initialize lc_ctrl by sending pwrmgr req and otp_ctrl valid random data.
Request a valid next LC state by writing CSRs: transition_target, transition_token*, and transition_cmd.

Checks:

After lc_ctrl initialization finishes, check lc_ctrl broadcast outputs, check the value of lc_state and lc_transition_cnt CSRs, and check device_id and id_state CSRs.
After lc_ctrl state transition request, check status to ensure the transition is valid and successful.
Check token matching for both conditional and unconditional requests.
Once the transition is successful, check lc_ctrl broadcast outputs are all turned off.

`csr_hw_reset`

Test: lc_ctrl_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

Write all CSRs with a random value.
Apply reset to the DUT as well as the RAL model.
Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_rw`

Test: lc_ctrl_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

Loop through each CSR to write it with a random value.
Read the CSR back and check for correctness while adhering to its access policies.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_bit_bash`

Test: lc_ctrl_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

Walk a 1 through each CSR by flipping 1 bit at a time.
Read the CSR back and check for correctness while adhering to its access policies.
This verify that writing a specific bit within the CSR did not affect any of the other bits.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_aliasing`

Test: lc_ctrl_csr_aliasing

Verify no aliasing within the CSR address space.

Loop through each CSR to write it with a random value
Shuffle and read ALL CSRs back.
All CSRs except for the one that was written in this iteration should read back the previous value.
The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_mem_rw_with_rand_reset`

Test: lc_ctrl_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

Run csr_rw sequence to randomly access CSRs
If memory exists, run mem_partial_access in parallel with csr_rw
Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
It is mandatory to run this test for all available interfaces the CSRs are accessible from.

`regwen_csr_and_corresponding_lockable_csr`

Tests:

lc_ctrl_csr_rw
lc_ctrl_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

Randomly access all CSRs
Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

This test is based on smoke test. After smoke sequence, this test adds additional lc_state transition request before issuing reset. This should happen regardless if the transition is successful. Use scoreboard to ensure lc_ctrl ignores this additional lc_state transition request and check state count.

`regwen_during_op`

Test: lc_ctrl_regwen_during_op

Transition_regwen is RO register and it gates bunch of write access of other registers.

Checks:

Check transition_regwen register is set to 1 during lc_state transition request.
Check that accessing its locked CSRs is gated during the transition operation.

`rand_wr_claim_transition_if`

Test: lc_ctrl_claim_transition_if

claim_transition_if only accept Mubi8True or 0 value. This test will write random value to this register. Checks:

When write value Mubi8True to claim_transition_if register, the transition_regwen is set to 1.
When write any other value to claim_transition_if register, the transition_regwen register remains value 0.

`lc_prog_failure`

Test: lc_ctrl_prog_failure

This test checks lc_program failure by setting the error bit after otp program request.

Checks:

Check if status register reflects the correct error bit.
Check if lc_program_failure alert is triggered.
Check if lc_state moves to escalation state.

`lc_state_failure`

Test: lc_ctrl_state_failure

This test checks lc_state failure by:

Driving invalid data to lc_ctrl input otp_lc_data_i fields lc_state and lc_cnt.
Backdoor changing lc_ctrl FSM’s to invalid value. For invalid value, the testbench will test using random value and valid A/B/C/D values with different orders.

Checks:

Check if status register reflects the correct error bit.
Check if lc_state_failure alert is triggered.
Check if lc_state moves to escalation state.

`lc_errors`

Test: lc_ctrl_errors

This test randomly executes the error senarios:

otp_ctrl input lc_trans_cnt reaches 16
lc_ctrl state transition request is invalid
input LC token does not match the output from otp_ctrl
flash rma responses to lc_ctrl request with error
lc_ctrl clock bypass responses with error
input otp_lc_data’s error bit is set to 1 Note that all the above scenarios except the last one requires a reset to recover.

Checks:

Check if status register reflects the correct error bit.
Check if lc_state moves to correct exit state.
Check if lc_trans_cnt is incremented.

`security_escalation`

Tests:

lc_ctrl_security_escalation
lc_ctrl_errors
lc_ctrl_state_failure
lc_ctrl_prog_failure
lc_ctrl_jtag_errors
lc_ctrl_jtag_state_failure
lc_ctrl_jtag_prog_failure

This test checks two security escalation responses:

wipe secrets: permanently asserts lc_escalate_en signal
scrap state: lc_ctrl moves to escalation state, check the state will be cleared up upon next power cycle

`jtag_access`

Tests:

lc_ctrl_jtag_access
lc_ctrl_jtag_smoke
lc_ctrl_jtag_state_post_trans
lc_ctrl_jtag_errors
lc_ctrl_jtag_prog_failure
lc_ctrl_jtag_errors
lc_ctrl_jtag_regwen_during_op
lc_ctrl_jtag_csr_hw_reset
lc_ctrl_jtag_csr_rw
lc_ctrl_jtag_csr_bit_bash
lc_ctrl_jtag_csr_aliasing
lc_ctrl_jtag_same_csr_outstanding
lc_ctrl_jtag_csr_mem_rw_with_rand_reset
lc_ctrl_jtag_alert_test

This test checks jtag debug interface in lc_ctrl. This test will use both JTAG TAP and TLUL to access the CSR space. All above CSR sequences should be accessible via both interfaces.

`jtag_priority`

Test: lc_ctrl_jtag_priority

This test covers a corner case in JTAG and TLUL interfaces.

Stimulus:

Issue mux_claim operation from TLUL and JTAG interfaces at the same time.

Checks:

Ensure TAP interface has the priority.
Ensure right after the mux_claim operation, the non-prioritized interface returns 0 from the CSR readings. This checking ensures there is no token leakage between interfaces.

`lc_ctrl_volatile_unlock`

Test: lc_ctrl_volatile_unlock_smoke

This test covers lc_ctrl volatile_raw_unlock functionality.

Stimulus:

Claim the mutex.
Set volatile_raw_unlock to 1.
Trigger a lc_transition.
Trigger a second lc_transition without reset.

Checks:

If the current state is RawState, and transition state is TestUnlocked0, and if the input token is correct, expect the transition to be sucessful.
Check status and volatile_raw_unlock output.
If the raw unlock transition is successful, check the second lc_transition can be performed without any error.

`stress_all`

Test: lc_ctrl_stress_all

Combine above sequences in one test to run sequentially, except csr sequence.
Random selection of Tilelink or JTAG CSR for each sequence
Randomly add reset between each sequence.

`alert_test`

Test: lc_ctrl_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

Enable a random set of alert requests by writing random value to alert_test CSR.
Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
Repeat the above steps a bunch of times.

`tl_d_oob_addr_access`

Test: lc_ctrl_tl_errors

Access out of bounds address and verify correctness of response / behavior

`tl_d_illegal_access`

Test: lc_ctrl_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

TL-UL protocol error cases
- invalid opcode
- some mask bits not set when opcode is PutFullData
- mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
- mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
- address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
- size is greater than 2
OpenTitan defined error cases
- access unmapped address, expect d_error = 1 when devmode_i == 1
- write a CSR with unaligned address, e.g. a_address[1:0] != 0
- write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
- write a memory with a_mask != '1 when it doesn’t support partial accesses
- read a WO (write-only) memory
- write a RO (read-only) memory
- write with instr_type = True

`tl_d_outstanding_access`

Tests:

lc_ctrl_csr_hw_reset
lc_ctrl_csr_rw
lc_ctrl_csr_aliasing
lc_ctrl_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

`tl_d_partial_access`

Tests:

lc_ctrl_csr_hw_reset
lc_ctrl_csr_rw
lc_ctrl_csr_aliasing
lc_ctrl_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

`tl_intg_err`

Tests:

lc_ctrl_tl_intg_err
lc_ctrl_sec_cm

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

`sec_cm_bus_integrity`

Test: lc_ctrl_tl_intg_err

BUS.INTEGRITY:

Verify this countermeasure with a standardized test.

`sec_cm_transition_config_regwen`

Test: lc_ctrl_regwen_during_op

TRANSITION.CONFIG.REGWEN:

Verify that the transition interface registers cannot be modified anymore once a transition has been initiated (either via TL-UL or the JTAG interface, depending on which interface is being used to claim the mutex).

`sec_cm_manuf_state_sparse`

Tests:

lc_ctrl_sec_cm
lc_ctrl_state_failure

MANUF.STATE.SPARSE:

Verify this countermeasure with a standardized test.

`sec_cm_transition_ctr_sparse`

Tests:

lc_ctrl_sec_cm
lc_ctrl_state_failure

TRANSITION.CTR.SPARSE:

Verify this countermeasure with a standardized test.

`sec_cm_manuf_state_bkgn_chk`

Tests:

lc_ctrl_sec_cm
lc_ctrl_state_failure

MANUF.STATE.BKGN_CHK:

Verify this countermeasure with a standardized test.

`sec_cm_transition_ctr_bkgn_chk`

Tests:

lc_ctrl_sec_cm
lc_ctrl_state_failure

TRANSITION.CTR.BKGN_CHK:

Verify this countermeasure with a standardized test.

`sec_cm_state_config_sparse`

Tests:

lc_ctrl_sec_cm
lc_ctrl_state_failure

STATE.CONFIG.SPARSE:

Verify this countermeasure with a standardized test.

`sec_cm_main_fsm_sparse`

Tests:

lc_ctrl_sec_cm
lc_ctrl_state_failure

MAIN.FSM.SPARSE:

Verify this countermeasure with a standardized test.

`sec_cm_kmac_fsm_sparse`

Tests:

lc_ctrl_sec_cm
lc_ctrl_state_failure

KMAC.FSM.SPARSE:

Verify this countermeasure with a standardized test.

`sec_cm_main_fsm_local_esc`

Tests:

lc_ctrl_sec_cm
lc_ctrl_state_failure

MAIN.FSM.LOCAL_ESC:

Verify that the main FSM goes into the InvalidSt if

the FSM enum is glitched into an undefined state (MAIN.FSM.SPARSE),
the KMAC interface FSM is glitched into an undefined state (KMAC.FSM.SPARSE),
the life cycle state vector and transition counter (from OTP) have an invalid encoding (MANUF.STATE.BKGN_CHK, TRANSITION.CTR.BKGN_CHK).

`sec_cm_main_fsm_global_esc`

Test: lc_ctrl_security_escalation

MAIN.FSM.GLOBAL_ESC:

Verify that the main FSM goes into the EscalateSt if any of the two escalation channels (esc_scrap_state0/1) is asserted.

`sec_cm_main_ctrl_flow_consistency`

Tests:

lc_ctrl_state_post_trans
lc_ctrl_jtag_state_post_trans

MAIN.CTRL_FLOW.CONSISTENCY:

Verify that the control flow of the main FSM only ever progresses in one direction - i.e. that there are no transitions that move backwards into a state where the FSM has previously been (e.g. from InvalidSt back into IdleSt).

Note: This is expected to be formally proven by FPV test lc_ctrl_sec_cm_fsm but there is currently no mechanism to include this in the testplan.

`sec_cm_intersig_mubi`

Test: lc_ctrl_sec_mubi

INTERSIG.MUBI:

Verify the behavior of MUBI inputs as follows:

lc_clk_byp_ack_i: Verify that an inconsistent input value (lc_clk_byp_ack_i != lc_clk_byp_ack_o) causes an OTP_ERROR when a life cycle transition is initiated.

There are two ways this condition can be triggered: either no external clock is requested, and then setting lc_clk_byp_ack_i to any value other than ‘OFF’ when initiating the life cycle transition should trigger this error. If the external clock is requested, setting lc_clk_byp_ack_i to any value other than ‘ON’ after the main FSM has progressed through the ClkMuxSt state should trigger this error.

lc_flash_rma_ack_i: Verify that an inconsistent input value (lc_flash_rma_ack_i != lc_flash_rma_ack_o) causes a FLASH_RMA_ERROR when a life cycle transition is initiated.

There are two ways this condition can be triggered: either no RMA transition is requested, and then setting lc_flash_rma_ack_i to any value other than ‘OFF’ when initiating the life cycle transition should trigger this error. If an RMA transition is requested, setting lc_flash_rma_ack_i to any value other than ‘ON’ after the main FSM has progressed through the FlashRmaSt state should trigger this error.

The main life cycle FSM should not progress through the TransProgSt if this error occurs.

`sec_cm_token_valid_ctrl_mubi`

Test: lc_ctrl_sec_mubi

TOKEN_VALID.CTRL.MUBI:

Verify that any value other than ‘ON’ will lead to a TOKEN_ERROR in life cycle transitions where the associated token is being used. The main life cycle FSM should not progress through the TransProgSt if this error occurs.

`sec_cm_token_digest`

Test: lc_ctrl_sec_token_digest

TOKEN.DIGEST:

Life cycle tokens are hashed using an external SHA3 block, and checked multiple times internally. In order to verify this countermeasure, the following aspects should be tested:

All valid hashed token values (RAW_UNLOCK, TEST_UNLOCK, TEST_EXIT and RMA) should be tested in conjunction with the appropriate life cycle transition to make sure that the correct tokens are selected internally (the RAW_UNLOCK token is a netlist constant, while the other tokens are supplied by OTP).
The hashed token is checked three times overall in the TokenHashSt, TokenCheck0St and TokenCheck1St. Verify that a mismatch in any of these checks will lead to a TOKEN_ERROR.

`sec_cm_token_mux_ctrl_redun`

Test: lc_ctrl_sec_token_mux

TOKEN_MUX.CTRL.REDUN:

The token mux is split into two halves that are indexed separately. Verify that any inconsistency between the two indexes leads to a TRANSITION_ERROR, without the main FSM going through the TransProgSt state. To that end, an inconsistency is triggered by forcing the token_idx0/1 signals to different values when initiating a lifecycle transition.

Note: the same test as for TOKEN_VALID.MUX.REDUN can be used.

`sec_cm_token_valid_mux_redun`

Test: lc_ctrl_sec_token_mux

TOKEN_VALID.MUX.REDUN:

Note: the same test as for TOKEN_MUX.CTRL.REDUN can be used.

Stage V3 Testpoints

`stress_all_with_rand_reset`

Test: lc_ctrl_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

err_inj_cg

Indicates what error conditions have been injected.

lc_ctrl_fsm_cg

lc_ctrl_fsm states and arcs

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

sec_token_digest_error_cg

Indicates FSM states that a token digest error is detected

sec_token_mux_idx_error_cg

Indicates FSM states that a token mux index error is detected

tl_errors_cg

Cover the following error cases on TL-UL bus:

TL-UL protocol error cases.
OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.

volatile_raw_unlock_cg

Cover volatile_raw_unlock transition success and fail cases.