OpenTitan
Getting Started
1.
Getting Started
2.
Workflows
❱
2.1.
Design Verification
2.2.
Formal Verification
2.3.
Building (and Testing) Software
2.4.
Building Documentation
2.5.
Using OpenOCD
3.
Tools Setup
❱
3.1.
FPGA Setup
3.2.
Verilator Setup
3.3.
Installing Vivado
4.
Unofficial Guides
❱
4.1.
RedHat/Fedora
Hardware
5.
Introduction
6.
Top Earlgrey
❱
6.1.
Datasheet
6.2.
Design
6.3.
Design Verification
❱
6.3.1.
Chip Testplan
6.4.
Analog Sensor Top
❱
6.4.1.
Interfaces
6.5.
Alert Handler
❱
6.5.1.
Theory of Operation
6.5.2.
Design Verification
❱
6.5.2.1.
Testplan
6.5.3.
Programmer's Guide
6.5.4.
Interface and Registers
6.5.5.
Device Interface Functions
6.5.6.
Checklist
6.6.
Interrupt Controller
❱
6.6.1.
Theory of Operation
6.6.2.
Design Verification
❱
6.6.2.1.
Testplan
6.6.3.
Programmer's Guide
6.6.4.
Interface and Registers
6.6.5.
Device Interface Functions
6.6.6.
Checklist
6.7.
Sensor Control
❱
6.7.1.
Theory of Operation
6.7.2.
Programmer's Guide
6.7.3.
Interface and Registers
6.7.4.
Device Interface Functions
6.7.5.
Checklist
6.8.
TL-UL Checklist
6.9.
Pinmux Targets
❱
6.9.1.
ASIC Target Pinout and Pinmux Connectivity
6.9.2.
CW310 Target Pinout and Pinmux Connectivity
7.
Cores
❱
7.1.
Ibex RISC-V Core Wrapper
❱
7.1.1.
Theory of Operation
7.1.2.
Design Verification
7.1.3.
Programmer's Guide
7.1.4.
Hardware Interfaces
7.1.5.
Registers
7.1.6.
Checklist
7.2.
OTBN
❱
7.2.1.
Theory of Operation
7.2.2.
Developing OTBN
7.2.3.
ISA Guide
7.2.4.
Design Verification
❱
7.2.4.1.
Random Instruction Generator
❱
7.2.4.1.1.
Internals
7.2.4.1.2.
Configuration
7.2.4.2.
memutil wrapper
7.2.4.3.
OTBN Simulation Software
7.2.4.4.
Tracer
7.2.4.5.
Formal Masking Verification Using Alma
7.2.5.
Functional Coverage
7.2.6.
Programmer's Guide
7.2.7.
Hardware Interfaces
7.2.8.
Registers
7.2.9.
Checklist
8.
Hardware IP Blocks
❱
8.1.
Analog to Digital Converter Control
❱
8.1.1.
Theory of Operation
8.1.2.
Design Verification
❱
8.1.2.1.
Testplan
8.1.3.
Programmer's Guide
8.1.4.
Hardware Interfaces
8.1.5.
Registers
8.1.6.
Checklist
8.2.
AES
❱
8.2.1.
Theory of Operation
8.2.2.
Design Verification
❱
8.2.2.1.
Testplan
8.2.3.
Programmer's Guide
8.2.4.
Hardware Interfaces
8.2.5.
Registers
8.2.6.
Device Interface Functions
8.2.7.
Checklist
8.3.
AON Timer
❱
8.3.1.
Theory of Operation
8.3.2.
Design Verification
❱
8.3.2.1.
Testplan
8.3.3.
Programmer's Guide
8.3.4.
Hardware Interfaces
8.3.5.
Registers
8.3.6.
Device Interface Functions
8.3.7.
Checklist
8.4.
Clock Manager
❱
8.4.1.
Theory of Operation
8.4.2.
Design Verification
❱
8.4.2.1.
Testplan
8.4.3.
Programmer's Guide
8.4.4.
Hardware Interfaces
8.4.5.
Registers
8.4.6.
Device Interface Functions
8.4.7.
Checklist
8.5.
CSRNG
❱
8.5.1.
Theory of Operation
8.5.2.
Design Verification
❱
8.5.2.1.
Testplan
8.5.3.
Programmer's Guide
8.5.4.
Hardware Interfaces
8.5.5.
Registers
8.5.6.
Device Interface Functions
8.5.7.
Checklist
8.6.
EDN
❱
8.6.1.
Theory of Operation
8.6.2.
Design Verification
❱
8.6.2.1.
Testplan
8.6.3.
Programmer's Guide
8.6.4.
Hardware Interfaces
8.6.5.
Registers
8.6.6.
Device Interface Functions
8.6.7.
Checklist
8.7.
Entropy Source
❱
8.7.1.
Theory of Operation
8.7.2.
Design Verification
❱
8.7.2.1.
Testplan
8.7.3.
Programmer's Guide
8.7.4.
Hardware Interfaces
8.7.5.
Registers
8.7.6.
Device Interface Functions
8.7.7.
Checklist
8.8.
Flash Controller
❱
8.8.1.
Theory of Operation
8.8.2.
Design Verification
❱
8.8.2.1.
Testplan
8.8.3.
Programmer's Guide
8.8.4.
Hardware Interfaces
8.8.5.
Registers
8.8.6.
Device Interface Functions
8.8.7.
Checklist
8.9.
GPIO
❱
8.9.1.
Theory of Operation
8.9.2.
Design Verification
❱
8.9.2.1.
Testplan
8.9.3.
Programmer's Guide
8.9.4.
Hardware Interfaces
8.9.5.
Registers
8.9.6.
Device Interface Functions
8.9.7.
Checklist
8.10.
HMAC
❱
8.10.1.
Theory of Operation
8.10.2.
Design Verification
❱
8.10.2.1.
Testplan
8.10.3.
Programmer's Guide
8.10.4.
Hardware Interfaces
8.10.5.
Registers
8.10.6.
Device Interface Functions
8.10.7.
Checklist
8.11.
I2C
❱
8.11.1.
Theory of Operation
8.11.2.
Design Verification
❱
8.11.2.1.
Testplan
8.11.3.
Programmer's Guide
8.11.4.
Hardware Interfaces
8.11.5.
Registers
8.11.6.
Device Interface Functions
8.11.7.
Checklist
8.12.
Key Manager
❱
8.12.1.
Theory of Operation
8.12.2.
Design Verification
❱
8.12.2.1.
Testplan
8.12.3.
Programmer's Guide
8.12.4.
Hardware Interfaces
8.12.5.
Registers
8.12.6.
Device Interface Functions
8.12.7.
Checklist
8.13.
KMAC
❱
8.13.1.
Theory of Operation
8.13.2.
Design Verification
❱
8.13.2.1.
Testplan
8.13.3.
Programmer's Guide
8.13.4.
Hardware Interfaces
8.13.5.
Registers
8.13.6.
Device Interface Functions
8.13.7.
Checklist
8.14.
Life Cycle Controller
❱
8.14.1.
Theory of Operation
8.14.2.
Design Verification
❱
8.14.2.1.
Testplan
8.14.3.
Programmer's Guide
8.14.4.
Hardware Interfaces
8.14.5.
Registers
8.14.6.
Device Interface Functions
8.14.7.
Checklist
8.15.
OTP Controller
❱
8.15.1.
Theory of Operation
8.15.2.
Design Verification
❱
8.15.2.1.
Testplan
8.15.3.
Programmer's Guide
8.15.4.
Hardware Interfaces
8.15.5.
Registers
8.15.6.
Device Interface Functions
8.15.7.
Checklist
8.16.
Pattern Generator
❱
8.16.1.
Theory of Operation
8.16.2.
Design Verification
❱
8.16.2.1.
Testplan
8.16.3.
Programmer's Guide
8.16.4.
Hardware Interfaces
8.16.5.
Registers
8.16.6.
Device Interface Functions
8.16.7.
Checklist
8.17.
Pinmux
❱
8.17.1.
Theory of Operation
8.17.2.
Design Verification
❱
8.17.2.1.
Testplan
8.17.3.
Programmer's Guide
8.17.4.
Hardware Interfaces
8.17.5.
Registers
8.17.6.
Device Interface Functions
8.17.7.
Checklist
8.18.
Pulse Width Modulator
❱
8.18.1.
Theory of Operation
8.18.2.
Design Verification
❱
8.18.2.1.
Testplan
8.18.3.
Programmer's Guide
8.18.4.
Hardware Interfaces
8.18.5.
Registers
8.18.6.
Device Interface Functions
8.18.7.
Checklist
8.19.
Power Management
❱
8.19.1.
Theory of Operation
8.19.2.
Design Verification
❱
8.19.2.1.
Testplan
8.19.3.
Programmer's Guide
8.19.4.
Hardware Interfaces
8.19.5.
Registers
8.19.6.
Device Interface Functions
8.19.7.
Checklist
8.20.
ROM Control
❱
8.20.1.
Theory of Operation
8.20.2.
Design Verification
❱
8.20.2.1.
Testplan
8.20.3.
Programmer's Guide
8.20.4.
Hardware Interfaces
8.20.5.
Registers
8.20.6.
Device Interface Functions
8.20.7.
Checklist
8.21.
Reset Manager
❱
8.21.1.
Theory of Operation
8.21.2.
Design Verification
❱
8.21.2.1.
Testplan
8.21.3.
Programmer's Guide
8.21.4.
Hardware Interfaces
8.21.5.
Registers
8.21.6.
Device Interface Functions
8.21.7.
Checklist
8.22.
RISC-V Debug Manager
❱
8.22.1.
Theory of Operation
8.22.2.
Design Verification
❱
8.22.2.1.
Testplan
8.22.3.
Programmer's Guide
8.22.4.
Hardware Interfaces
8.22.5.
Registers
8.22.6.
Checklist
8.23.
SPI Device
❱
8.23.1.
Theory of Operation
8.23.2.
Design Verification
❱
8.23.2.1.
Testplan
8.23.3.
Programmer's Guide
8.23.4.
Hardware Interfaces
8.23.5.
Registers
8.23.6.
Device Interface Functions
8.23.7.
Checklist
8.24.
SPI Host
❱
8.24.1.
Theory of Operation
8.24.2.
Design Verification
❱
8.24.2.1.
Testplan
8.24.3.
Programmer's Guide
8.24.4.
Hardware Interfaces
8.24.5.
Registers
8.24.6.
Device Interface Functions
8.24.7.
Checklist
8.25.
SRAM Controller
❱
8.25.1.
Theory of Operation
8.25.2.
Design Verification
❱
8.25.2.1.
Testplan
8.25.3.
Programmer's Guide
8.25.4.
Hardware Interfaces
8.25.5.
Registers
8.25.6.
Device Interface Functions
8.25.7.
Checklist
8.26.
System Reset Controller
❱
8.26.1.
Theory of Operation
8.26.2.
Design Verification
❱
8.26.2.1.
Testplan
8.26.3.
Hardware Interfaces
8.26.4.
Registers
8.26.5.
Device Interface Functions
8.26.6.
Checklist
8.27.
Timer
❱
8.27.1.
Theory of Operation
8.27.2.
Design Verification
❱
8.27.2.1.
Testplan
8.27.3.
Programmer's Guide
8.27.4.
Hardware Interfaces
8.27.5.
Registers
8.27.6.
Device Interface Functions
8.27.7.
Checklist
8.28.
TL-UL Bus
❱
8.28.1.
Design Verification
❱
8.28.1.1.
Testplan
8.28.1.2.
Protocol Checker
8.29.
UART
❱
8.29.1.
Theory of Operation
8.29.2.
Design Verification
❱
8.29.2.1.
Testplan
8.29.3.
Programmer's Guide
8.29.4.
Hardware Interfaces
8.29.5.
Registers
8.29.6.
Device Interface Functions
8.29.7.
Checklist
8.30.
USB 2.0
❱
8.30.1.
Theory of Operation
8.30.2.
Design Verification
❱
8.30.2.1.
Testplan
8.30.3.
Programmer's Guide
8.30.4.
Suspending and Resuming
8.30.5.
Hardware Interfaces
8.30.6.
Registers
8.30.7.
Device Interface Functions
8.30.8.
Checklist
8.31.
lowRISC Hardware Primitives
❱
8.31.1.
Two Input Clock
8.31.2.
Flash Wrapper
8.31.3.
Keccak Permutation
8.31.4.
Linear Feedback Shift Register
8.31.5.
Packer
8.31.6.
Packer FIFO
8.31.7.
Present Scrambler
8.31.8.
Prince Scrambler
8.31.9.
SRAM Scrambler
8.31.10.
Pseudo Random Number Generator
9.
Common SystemVerilog and UVM Components
❱
9.1.
ALERT_ESC Agent
9.2.
Bus Params Package
9.3.
Comportable IP Testbench Architecture
9.4.
Common Interfaces
9.5.
CSR Utils
9.6.
CSRNG Agent
9.7.
DV Library Classes
9.8.
DV Utils
9.9.
FLASH_PHY_PRIM Agent
9.10.
I2C Agent
9.11.
JTAG Agent
9.12.
JTAG DMI Agent
9.13.
JTAG RISCV Agent
9.14.
KEY_SIDELOAD Agent
9.15.
KMAC_APP Agent
9.16.
Memory Backdoor Scoreboard
9.17.
Memory Backdoor Utility
9.18.
Memory Model
9.19.
PATTGEN Agent
9.20.
PUSH_PULL Agent
9.21.
PWM Monitor
9.22.
RNG Agent
9.23.
Scoreboard
9.24.
Simulation SRAM
9.25.
SPI Agent
9.26.
String Utils
9.27.
Test Vectors
9.28.
Tile Link Agent
9.29.
UART Agent
9.30.
USB20 Agent
Software
10.
Introduction
11.
Build Software
12.
Device Software
❱
12.1.
Device Libraries
❱
12.1.1.
DIF Library
❱
12.1.1.1.
ADC Checklist
12.1.1.2.
AES Checklist
12.1.1.3.
Alert Handler Checklist
12.1.1.4.
Always-On Timer Checklist
12.1.1.5.
Clock Manager Checklist
12.1.1.6.
CSRNG Checklist
12.1.1.7.
EDN Checklist
12.1.1.8.
Entropy Source Checklist
12.1.1.9.
Flash Controller Checklist
12.1.1.10.
GPIO Checklist
12.1.1.11.
HMAC Checklist
12.1.1.12.
I2C Checklist
12.1.1.13.
Key Manager Checklist
12.1.1.14.
KMAC Checklist
12.1.1.15.
Lifecycle Checklist
12.1.1.16.
OTBN Checklist
12.1.1.17.
OTP Controller Checklist
12.1.1.18.
Pattern Generator Checklist
12.1.1.19.
Pin Multiplexer Checklist
12.1.1.20.
PWM Checklist
12.1.1.21.
Power Manager Checklist
12.1.1.22.
ROM Checklist
12.1.1.23.
Reset Manager Checklist
12.1.1.24.
RV Core Ibex Checklist
12.1.1.25.
PLIC Checklist
12.1.1.26.
RV Timer Checklist
12.1.1.27.
Sensor Controller Checklist
12.1.1.28.
SPI Device Checklist
12.1.1.29.
SPI Host Checklist
12.1.1.30.
SRAM Controller Checklist
12.1.1.31.
System Reset Controller Checklist
12.1.1.32.
UART Checklist
12.1.1.33.
USB Checklist
12.1.2.
Top-Level Test Libraries
❱
12.1.2.1.
On-Device Test Framework
12.1.3.
OpenTitan Standard Library
❱
12.1.3.1.
Freestanding C Headers
12.2.
Silicon Creator Software
❱
12.2.1.
Manufacturing Firmware
❱
12.2.1.1.
Test Plan
12.2.2.
ROM
❱
12.2.2.1.
ROM Specification
12.2.2.2.
Bootstrap
12.2.2.3.
Memory Protection
12.2.2.4.
E2E tests
12.2.2.5.
Signing Keys
12.2.2.6.
Signature Verification
12.2.2.7.
Test Plan
12.2.2.8.
Signoff Test Plan
12.2.2.9.
Shutdown Specification
12.2.3.
Manifest Format
12.2.4.
Boot Log
12.3.
Top-Level Tests
❱
12.3.1.
Manufacturer Test Hooks
12.3.2.
Crypto Library Tests
13.
Host Software
❱
13.1.
Hardware Security Module (HSM) tool
❱
13.1.1.
Requirements
13.2.
OpenTitanLib
13.3.
OpenTitanSession
13.4.
OpenTitanTool
13.5.
TPM2 Test Server
Tooling
14.
Tools Overview
15.
Design-Related Tooling
16.
dvsim
❱
16.1.
Design Document
16.2.
Testplanner
16.3.
Glossary
17.
fpvgen: Initial FPV Testbench Generation
18.
reggen & regtool: Register Generator
❱
18.1.
Setup and use of regtool
19.
ralgen: FuseSoC UVM RAL Generator
20.
uvmdvgen: Initial Testbench Auto-generation
21.
tlgen: Crossbar Generation
22.
ipgen: Generate IP Blocks from IP Templates
23.
topgen: Top Generator
24.
vendor: Vendoring In Tool
25.
i2csvg: Generate SVGs of I2C Commands
Contributing
26.
Contributing
❱
26.1.
Detailed Contribution Guide
26.2.
Directory Structure
26.3.
Contributing to Documentation
❱
26.3.1.
An Example IP Block's Documentation
26.4.
Continuous Intergration
26.5.
Top-Level Design and Targets
26.6.
GitHub Notes
26.7.
Bazel Notes
26.8.
Using the Container
27.
Contributing to Hardware
❱
27.1.
Comportability
27.2.
Hardware Design
27.3.
Design Methodology
27.4.
Vendoring in Hardware
27.5.
Linting
27.6.
Synthesis Flow
28.
Contributing to Verification
❱
28.1.
Verification Methodology
28.2.
Security Countermeasure Verification Framework
28.3.
Assertions
29.
Contributing to Software
❱
29.1.
Device Interface Functions
29.2.
Writing and Building Software for OTBN
30.
Style Guides
❱
30.1.
HJSON
30.2.
Python
30.3.
C & C++
30.4.
Markdown
30.5.
RISC-V Assembly
30.6.
OTBN Assembly
30.7.
Guidance for Volatile
31.
Developing on an FPGA
❱
31.1.
Get a Board
31.2.
FPGA Reference Manual
31.3.
Debugging with an ILA
Project Governance
32.
Introduction
33.
Committers
34.
RFC Process
35.
Generalized Priority Definitions
36.
OpenTitan Technical Committee
37.
Hardware Development Stages
38.
Signoff Checklist
Security
39.
Security
40.
Cryptography Library
❱
40.1.
API Documentation
41.
Implementation Guidelines
❱
41.1.
Secure Hardware Design Guidelines
42.
Logical Security Model
43.
Security Model Specification
❱
43.1.
Device Attestation
43.2.
Device Life Cycle
43.3.
Device Provisioning
43.4.
Firmware Update
43.5.
Identities and Root Keys
43.6.
Ownership Transfer
43.7.
Secure Boot
44.
Lightweight Threat Model
Use Cases
45.
Use Cases
46.
Platform Integrity Module
47.
Trusted Platform Module
48.
Universal 2nd-Factor Security Key
Rust for C Developers
49.
Rust for Embedded C Programmers
Appendix
50.
Glossary
OpenTitan Light
opentitan.org
Common SystemVerilog and UVM Components