OpenTitan
Hardware
1.
Introduction
2.
Top Earlgrey
❱
2.1.
Datasheet
2.2.
Design
2.3.
Design Verification
2.4.
Analog Sensor Top
2.5.
Alert Handler
❱
2.5.1.
Theory of Operation
2.5.2.
Design Verification
❱
2.5.2.1.
Testplan
2.5.3.
Programmer's Guide
2.5.4.
Interface and Registers
2.5.5.
Device Interface Functions
2.5.6.
Checklist
2.6.
Interrupt Controller
❱
2.6.1.
Theory of Operation
2.6.2.
Design Verification
❱
2.6.2.1.
Testplan
2.6.3.
Programmer's Guide
2.6.4.
Interface and Registers
2.6.5.
Device Interface Functions
2.6.6.
Checklist
2.7.
Sensor Control
❱
2.7.1.
Theory of Operation
2.7.2.
Programmer's Guide
2.7.3.
Interface and Registers
2.7.4.
Device Interface Functions
2.7.5.
Checklist
2.8.
TL-UL Checklist
2.9.
Pinmux Targets
❱
2.9.1.
ASIC Target Pinout and Pinmux Connectivity
2.9.2.
CW310 Target Pinout and Pinmux Connectivity
2.9.3.
NEXYSVIDEO Target Pinout and Pinmux Connectivity
3.
Cores
❱
3.1.
Ibex RISC-V Core Wrapper
❱
3.1.1.
Design Verification
3.1.2.
Interface and Registers
3.1.3.
Checklist
3.2.
OTBN
❱
3.2.1.
Developer Guide
3.2.2.
ISA Guide
3.2.3.
Design Verification
❱
3.2.3.1.
Random Instruction Generator
❱
3.2.3.1.1.
Internals
3.2.3.1.2.
Configuration
3.2.3.2.
memutil wrapper
3.2.3.3.
OTBN Simulation Software
3.2.3.4.
Tracer
3.2.3.5.
Formal Masking Verification Using Alma
3.2.4.
Functional Coverage
3.2.5.
Interface and Registers
3.2.6.
Checklist
4.
Hardware IP Blocks
❱
4.1.
Analog to Digital Converter Control
❱
4.1.1.
Theory of Operation
4.1.2.
Design Verification
❱
4.1.2.1.
Testplan
4.1.3.
Programmer's Guide
4.1.4.
Checklist
4.1.5.
Interface and Registers
4.2.
AES
❱
4.2.1.
Theory of Operation
4.2.2.
Design Verification
❱
4.2.2.1.
Testplan
4.2.3.
Programmer's Guide
4.2.4.
Interface and Registers
4.2.5.
Device Interface Functions
4.2.6.
Checklist
4.3.
AON Timer
❱
4.3.1.
Theory of Operation
4.3.2.
Design Verification
❱
4.3.2.1.
Testplan
4.3.3.
Programmer's Guide
4.3.4.
Interface and Registers
4.3.5.
Device Interface Functions
4.3.6.
Checklist
4.4.
Clock Manager
❱
4.4.1.
Theory of Operation
4.4.2.
Design Verification
❱
4.4.2.1.
Testplan
4.4.3.
Programmer's Guide
4.4.4.
Interface and Registers
4.4.5.
Device Interface Functions
4.4.6.
Checklist
4.5.
CSRNG
❱
4.5.1.
Theory of Operation
4.5.2.
Design Verification
❱
4.5.2.1.
Testplan
4.5.3.
Programmer's Guide
4.5.4.
Interface and Registers
4.5.5.
Device Interface Functions
4.5.6.
Checklist
4.6.
EDN
❱
4.6.1.
Theory of Operation
4.6.2.
Design Verification
❱
4.6.2.1.
Testplan
4.6.3.
Programmer's Guide
4.6.4.
Interface and Registers
4.6.5.
Device Interface Functions
4.6.6.
Checklist
4.7.
Entropy Source
❱
4.7.1.
Theory of Operation
4.7.2.
Design Verification
❱
4.7.2.1.
Testplan
4.7.3.
Programmer's Guide
4.7.4.
Interface and Registers
4.7.5.
Device Interface Functions
4.7.6.
Checklist
4.8.
Flash Controller
❱
4.8.1.
Theory of Operation
4.8.2.
Design Verification
❱
4.8.2.1.
Testplan
4.8.3.
Programmer's Guide
4.8.4.
Interface and Registers
4.8.5.
Device Interface Functions
4.8.6.
Checklist
4.9.
GPIO
❱
4.9.1.
Theory of Operation
4.9.2.
Design Verification
❱
4.9.2.1.
Testplan
4.9.3.
Programmer's Guide
4.9.4.
Interface and Registers
4.9.5.
Device Interface Functions
4.9.6.
Checklist
4.10.
HMAC
❱
4.10.1.
Theory of Operation
4.10.2.
Design Verification
❱
4.10.2.1.
Testplan
4.10.3.
Programmer's Guide
4.10.4.
Interface and Registers
4.10.5.
Device Interface Functions
4.10.6.
Checklist
4.11.
I2C
❱
4.11.1.
Theory of Operation
4.11.2.
Design Verification
❱
4.11.2.1.
Testplan
4.11.3.
Programmer's Guide
4.11.4.
Interface and Registers
4.11.5.
Device Interface Functions
4.11.6.
Checklist
4.12.
Key Manager
❱
4.12.1.
Theory of Operation
4.12.2.
Design Verification
❱
4.12.2.1.
Testplan
4.12.3.
Programmer's Guide
4.12.4.
Interface and Registers
4.12.5.
Device Interface Functions
4.12.6.
Checklist
4.13.
KMAC
❱
4.13.1.
Theory of Operation
4.13.2.
Design Verification
❱
4.13.2.1.
Testplan
4.13.3.
Programmer's Guide
4.13.4.
Interface and Registers
4.13.5.
Device Interface Functions
4.13.6.
Checklist
4.14.
Life Cycle Controller
❱
4.14.1.
Theory of Operation
4.14.2.
Design Verification
❱
4.14.2.1.
Testplan
4.14.3.
Programmer's Guide
4.14.4.
Interface and Registers
4.14.5.
Device Interface Functions
4.14.6.
Checklist
4.15.
OTP Controller
❱
4.15.1.
Theory of Operation
4.15.2.
Design Verification
❱
4.15.2.1.
Testplan
4.15.3.
Programmer's Guide
4.15.4.
Interface and Registers
4.15.5.
Device Interface Functions
4.15.6.
Checklist
4.16.
Pattern Generator
❱
4.16.1.
Theory of Operation
4.16.2.
Design Verification
❱
4.16.2.1.
Testplan
4.16.3.
Programmer's Guide
4.16.4.
Interface and Registers
4.16.5.
Device Interface Functions
4.16.6.
Checklist
4.17.
Pinmux
❱
4.17.1.
Theory of Operation
4.17.2.
Design Verification
❱
4.17.2.1.
Testplan
4.17.3.
Programmer's Guide
4.17.4.
Interface and Registers
4.17.5.
Device Interface Functions
4.17.6.
Checklist
4.18.
Pulse Width Modulator
❱
4.18.1.
Theory of Operation
4.18.2.
Design Verification
❱
4.18.2.1.
Testplan
4.18.3.
Programmer's Guide
4.18.4.
Interface and Registers
4.18.5.
Device Interface Functions
4.18.6.
Checklist
4.19.
Power Management
❱
4.19.1.
Theory of Operation
4.19.2.
Design Verification
❱
4.19.2.1.
Testplan
4.19.3.
Programmer's Guide
4.19.4.
Interface and Registers
4.19.5.
Device Interface Functions
4.19.6.
Checklist
4.20.
ROM Control
❱
4.20.1.
Theory of Operation
4.20.2.
Design Verification
❱
4.20.2.1.
Testplan
4.20.3.
Programmer's Guide
4.20.4.
Interface and Registers
4.20.5.
Device Interface Functions
4.20.6.
Checklist
4.21.
Reset Manager
❱
4.21.1.
Theory of Operation
4.21.2.
Design Verification
❱
4.21.2.1.
Testplan
4.21.3.
Programmer's Guide
4.21.4.
Interface and Registers
4.21.5.
Device Interface Functions
4.21.6.
Checklist
4.22.
RISC-V Debug Manager
❱
4.22.1.
Design Verification
❱
4.22.1.1.
Testplan
4.22.2.
Interface and Registers
4.22.3.
Checklist
4.23.
SPI Device
❱
4.23.1.
Theory of Operation
4.23.2.
Design Verification
❱
4.23.2.1.
Testplan
4.23.3.
Programmer's Guide
4.23.4.
Interface and Registers
4.23.5.
Device Interface Functions
4.23.6.
Checklist
4.24.
SPI Host
❱
4.24.1.
Theory of Operation
4.24.2.
Design Verification
❱
4.24.2.1.
Testplan
4.24.3.
Programmer's Guide
4.24.4.
Interface and Registers
4.24.5.
Device Interface Functions
4.24.6.
Checklist
4.25.
SRAM Controller
❱
4.25.1.
Theory of Operation
4.25.2.
Design Verification
❱
4.25.2.1.
Testplan
4.25.3.
Programmer's Guide
4.25.4.
Interface and Registers
4.25.5.
Device Interface Functions
4.25.6.
Checklist
4.26.
System Reset Controller
❱
4.26.1.
Design Verification
❱
4.26.1.1.
Testplan
4.26.2.
Interface and Registers
4.26.3.
Device Interface Functions
4.26.4.
Checklist
4.27.
Timer
❱
4.27.1.
Theory of Operation
4.27.2.
Design Verification
❱
4.27.2.1.
Testplan
4.27.3.
Programmer's Guide
4.27.4.
Interface and Registers
4.27.5.
Device Interface Functions
4.27.6.
Checklist
4.28.
TL-UL Bus
❱
4.28.1.
Design Verification
❱
4.28.1.1.
Testplan
4.28.1.2.
Protocol Checker
4.29.
UART
❱
4.29.1.
Theory of Operation
4.29.2.
Design Verification
❱
4.29.2.1.
Testplan
4.29.3.
Programmer's Guide
4.29.4.
Interface and Registers
4.29.5.
Device Interface Functions
4.29.6.
Checklist
4.30.
USB 2.0
❱
4.30.1.
Theory of Operation
4.30.2.
Design Verification
❱
4.30.2.1.
Testplan
4.30.3.
Programmer's Guide
4.30.4.
Suspending and Resuming
4.30.5.
Interface and Registers
4.30.6.
Device Interface Functions
4.30.7.
Checklist
4.31.
lowRISC Hardware Primitives
❱
4.31.1.
Two Input Clock
4.31.2.
Flash Wrapper
4.31.3.
Keccak Permutation
4.31.4.
Linear Feedback Shift Register
4.31.5.
Packer
4.31.6.
Packer FIFO
4.31.7.
Present Scrambler
4.31.8.
Prince Scrambler
4.31.9.
SRAM Scrambler
4.31.10.
Pseudo Random Number Generator
5.
Common SystemVerilog and UVM Components
❱
5.1.
ALERT_ESC Agent
5.2.
Bus Params Package
5.3.
Comportable IP Testbench Architecture
5.4.
Common Interfaces
5.5.
CSR Utils
5.6.
CSRNG Agent
5.7.
DV Library Classes
5.8.
DV Utils
5.9.
FLASH_PHY_PRIM Agent
5.10.
I2C Agent
5.11.
JTAG Agent
5.12.
JTAG DMI Agent
5.13.
JTAG RISCV Agent
5.14.
KEY_SIDELOAD Agent
5.15.
KMAC_APP Agent
5.16.
Memory Backdoor Scoreboard
5.17.
Memory Backdoor Utility
5.18.
Memory Model
5.19.
PATTGEN Agent
5.20.
PUSH_PULL Agent
5.21.
PWM Monitor
5.22.
RNG Agent
5.23.
Scoreboard
5.24.
Simulation SRAM
5.25.
SPI Agent
5.26.
String Utils
5.27.
Test Vectors
5.28.
Tile Link Agent
5.29.
UART Agent
5.30.
USB20 Agent
Software
6.
Introduction
7.
Build Software
8.
Device Software
❱
8.1.
Device Libraries
❱
8.1.1.
DIF Library
❱
8.1.1.1.
ADC Checklist
8.1.1.2.
AES Checklist
8.1.1.3.
Alert Handler Checklist
8.1.1.4.
Always-On Timer Checklist
8.1.1.5.
Clock Manager Checklist
8.1.1.6.
CSRNG Checklist
8.1.1.7.
EDN Checklist
8.1.1.8.
Entropy Source Checklist
8.1.1.9.
Flash Controller Checklist
8.1.1.10.
GPIO Checklist
8.1.1.11.
HMAC Checklist
8.1.1.12.
I2C Checklist
8.1.1.13.
Key Manager Checklist
8.1.1.14.
KMAC Checklist
8.1.1.15.
Lifecycle Checklist
8.1.1.16.
OTBN Checklist
8.1.1.17.
OTP Controller Checklist
8.1.1.18.
Pattern Generator Checklist
8.1.1.19.
Pin Multiplexer Checklist
8.1.1.20.
PWM Checklist
8.1.1.21.
Power Manager Checklist
8.1.1.22.
ROM Checklist
8.1.1.23.
Reset Manager Checklist
8.1.1.24.
RV Core Ibex Checklist
8.1.1.25.
PLIC Checklist
8.1.1.26.
RV Timer Checklist
8.1.1.27.
Sensor Controller Checklist
8.1.1.28.
SPI Device Checklist
8.1.1.29.
SPI Host Checklist
8.1.1.30.
SRAM Controller Checklist
8.1.1.31.
System Reset Controller Checklist
8.1.1.32.
UART Checklist
8.1.1.33.
USB Checklist
8.1.2.
Top-Level Test Libraries
❱
8.1.2.1.
On-Device Test Framework
8.1.3.
OpenTitan Standard Library
❱
8.1.3.1.
Freestanding C Headers
8.2.
Silicon Creator Software
❱
8.2.1.
Manufacturing Firmware
❱
8.2.1.1.
Test Plan
8.2.2.
ROM
❱
8.2.2.1.
Memory Protection
8.2.2.2.
E2E tests
8.2.2.3.
Signing Keys
8.2.2.4.
Test Plan
8.2.2.5.
Signoff Test Plan
8.2.3.
Manifest Format
8.3.
Top-Level Tests
❱
8.3.1.
Manufacturer Test Hooks
8.3.2.
Crypto Library Tests
9.
Host Software
Tooling
10.
Tools Overview
11.
Design-Related Tooling
12.
dvsim
❱
12.1.
Design Document
12.2.
Testplanner
12.3.
Glossary
13.
fpvgen: Initial FPV Testbench Generation
14.
reggen & regtool: Register Generator
❱
14.1.
Setup and use of regtool
15.
ralgen: FuseSoC UVM RAL Generator
16.
uvmdvgen: Initial Testbench Auto-generation
17.
tlgen: Crossbar Generation
18.
ipgen: Generate IP Blocks from IP Templates
19.
topgen: Top Generator
20.
vendor: Vendoring In Tool
21.
i2csvg: Generate SVGs of I2C Commands
Contributing
22.
Contributing
❱
22.1.
Detailed Contribution Guide
22.2.
Directory Structure
22.3.
Continueous Intergration
22.4.
Top-Level Design and Targets
22.5.
GitHub Notes
22.6.
Bazel Notes
22.7.
Using the Container
23.
Contributing to Hardware
❱
23.1.
Comportability
23.2.
Hardware Design
23.3.
Design Methodology
23.4.
Vendoring in Hardware
23.5.
Linting
23.6.
Synthesis Flow
24.
Contributing to Verification
❱
24.1.
Verification Methodology
24.2.
Security Countermeasure Verification Framework
24.3.
Assertions
25.
Contributing to Software
❱
25.1.
Device Interface Functions
25.2.
Writing and Building Software for OTBN
26.
Style Guides
❱
26.1.
HJSON
26.2.
Python
26.3.
C & C++
26.4.
Markdown
26.5.
RISC-V Assembly
26.6.
OTBN Assembly
26.7.
Guidance for Volatile
27.
Developing on an FPGA
❱
27.1.
Get a Board
27.2.
FPGA Reference Manual
Project Governance
28.
Introduction
29.
Committers
30.
RFC Process
31.
Generalized Priority Definitions
32.
OpenTitan Technical Committee
33.
Hardware Development Stages
34.
Signoff Checklist
Security
35.
Security
36.
Implementation Guidelines
❱
36.1.
Secure Hardware Design Guidelines
37.
Logical Security Model
38.
Security Model Specification
❱
38.1.
Device Attestation
38.2.
Device Life Cycle
38.3.
Device Provisioning
38.4.
Firmware Update
38.5.
Identities and Root Keys
38.6.
Ownership Transfer
38.7.
Secure Boot
39.
Lightweight Threat Model
Use Cases
40.
Use Cases
41.
Platform Integrity Module
42.
Trusted Platform Module
43.
Universal 2nd-Factor Security Key
Rust for C Developers
44.
Rust for Embedded C Programmers
Light
Rust
Coal
Navy
Ayu
OpenTitan Documentation
Common SystemVerilog and UVM Components
Content
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