Registers

Summary

NameOffsetLengthDescription
sysrst_ctrl.INTR_STATE0x04Interrupt State Register
sysrst_ctrl.INTR_ENABLE0x44Interrupt Enable Register
sysrst_ctrl.INTR_TEST0x84Interrupt Test Register
sysrst_ctrl.ALERT_TEST0xc4Alert Test Register
sysrst_ctrl.REGWEN0x104Configuration write enable control register
sysrst_ctrl.EC_RST_CTL0x144EC reset control register
sysrst_ctrl.ULP_AC_DEBOUNCE_CTL0x184Ultra low power AC debounce control register
sysrst_ctrl.ULP_LID_DEBOUNCE_CTL0x1c4Ultra low power lid debounce control register
sysrst_ctrl.ULP_PWRB_DEBOUNCE_CTL0x204Ultra low power pwrb debounce control register
sysrst_ctrl.ULP_CTL0x244Ultra low power control register
sysrst_ctrl.ULP_STATUS0x284Ultra low power status
sysrst_ctrl.WKUP_STATUS0x2c4wakeup status
sysrst_ctrl.KEY_INVERT_CTL0x304configure key input output invert property
sysrst_ctrl.PIN_ALLOWED_CTL0x344This register determines which override values are allowed for a given output.
sysrst_ctrl.PIN_OUT_CTL0x384Enables the override function for a specific pin.
sysrst_ctrl.PIN_OUT_VALUE0x3c4Sets the pin override value. Note that only the values
sysrst_ctrl.PIN_IN_VALUE0x404For SW to read the sysrst_ctrl inputs like GPIO
sysrst_ctrl.KEY_INTR_CTL0x444Define the keys or inputs that can trigger the interrupt
sysrst_ctrl.KEY_INTR_DEBOUNCE_CTL0x484Debounce timer control register for key-triggered interrupt
sysrst_ctrl.AUTO_BLOCK_DEBOUNCE_CTL0x4c4Debounce timer control register for pwrb_in H2L transition
sysrst_ctrl.AUTO_BLOCK_OUT_CTL0x504configure the key outputs to auto-override and their value
sysrst_ctrl.COM_PRE_SEL_CTL_00x544To define the keys that define the pre-condition of the combo
sysrst_ctrl.COM_PRE_SEL_CTL_10x584To define the keys that define the pre-condition of the combo
sysrst_ctrl.COM_PRE_SEL_CTL_20x5c4To define the keys that define the pre-condition of the combo
sysrst_ctrl.COM_PRE_SEL_CTL_30x604To define the keys that define the pre-condition of the combo
sysrst_ctrl.COM_PRE_DET_CTL_00x644To define the duration that the combo pre-condition should be pressed
sysrst_ctrl.COM_PRE_DET_CTL_10x684To define the duration that the combo pre-condition should be pressed
sysrst_ctrl.COM_PRE_DET_CTL_20x6c4To define the duration that the combo pre-condition should be pressed
sysrst_ctrl.COM_PRE_DET_CTL_30x704To define the duration that the combo pre-condition should be pressed
sysrst_ctrl.COM_SEL_CTL_00x744To define the keys that trigger the combo
sysrst_ctrl.COM_SEL_CTL_10x784To define the keys that trigger the combo
sysrst_ctrl.COM_SEL_CTL_20x7c4To define the keys that trigger the combo
sysrst_ctrl.COM_SEL_CTL_30x804To define the keys that trigger the combo
sysrst_ctrl.COM_DET_CTL_00x844To define the duration that the combo should be pressed
sysrst_ctrl.COM_DET_CTL_10x884To define the duration that the combo should be pressed
sysrst_ctrl.COM_DET_CTL_20x8c4To define the duration that the combo should be pressed
sysrst_ctrl.COM_DET_CTL_30x904To define the duration that the combo should be pressed
sysrst_ctrl.COM_OUT_CTL_00x944To define the actions once the combo is detected
sysrst_ctrl.COM_OUT_CTL_10x984To define the actions once the combo is detected
sysrst_ctrl.COM_OUT_CTL_20x9c4To define the actions once the combo is detected
sysrst_ctrl.COM_OUT_CTL_30xa04To define the actions once the combo is detected
sysrst_ctrl.COMBO_INTR_STATUS0xa44Combo interrupt source. These registers will only be set if the
sysrst_ctrl.KEY_INTR_STATUS0xa84key interrupt source

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0event_detectedCommon interrupt triggered by combo or keyboard events.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0event_detectedEnable interrupt when INTR_STATE.event_detected is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0event_detectedWrite 1 to force INTR_STATE.event_detected to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

REGWEN

Configuration write enable control register

  • Offset: 0x10
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1write_enconfig write enable. 0: cfg is locked(not writable); 1: cfg is not locked(writable)

EC_RST_CTL

EC reset control register

  • Offset: 0x14
  • Reset default: 0x7d0
  • Reset mask: 0xffff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:16Reserved
15:0rw0x7d0ec_rst_pulseConfigure the pulse width of ec_rst_l. Each step is 5 us for a 200 kHz clock.

ULP_AC_DEBOUNCE_CTL

Ultra low power AC debounce control register

  • Offset: 0x18
  • Reset default: 0x1f40
  • Reset mask: 0xffff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:16Reserved
15:0rw0x1f40ulp_ac_debounce_timerConfigure the debounce timer for the AC input in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

ULP_LID_DEBOUNCE_CTL

Ultra low power lid debounce control register

  • Offset: 0x1c
  • Reset default: 0x1f40
  • Reset mask: 0xffff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:16Reserved
15:0rw0x1f40ulp_lid_debounce_timerConfigure the debounce timer for the lid in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

ULP_PWRB_DEBOUNCE_CTL

Ultra low power pwrb debounce control register

  • Offset: 0x20
  • Reset default: 0x1f40
  • Reset mask: 0xffff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:16Reserved
15:0rw0x1f40ulp_pwrb_debounce_timerConfigure the debounce timer for the power button in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

ULP_CTL

Ultra low power control register

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0ulp_enable0: disable ULP wakeup feature and reset the ULP FSM; 1: enable ULP wakeup feature

ULP_STATUS

Ultra low power status

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0ulp_wakeup0: ULP wakeup not detected; 1: ULP wakeup event is detected

WKUP_STATUS

wakeup status

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0wakeup_sts0: wakeup event not detected; 1: wakeup event is detected

KEY_INVERT_CTL

configure key input output invert property

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0xfff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:12Reserved
11rw0x0z3_wakeup0: don’t invert; 1: invert
10rw0x0lid_open0: don’t invert; 1: invert
9rw0x0bat_disable0: don’t invert; 1: invert
8rw0x0ac_present0: don’t invert; 1: invert
7rw0x0pwrb_out0: don’t invert; 1: invert
6rw0x0pwrb_in0: don’t invert; 1: invert
5rw0x0key2_out0: don’t invert; 1: invert
4rw0x0key2_in0: don’t invert; 1: invert
3rw0x0key1_out0: don’t invert; 1: invert
2rw0x0key1_in0: don’t invert; 1: invert
1rw0x0key0_out0: don’t invert; 1: invert
0rw0x0key0_in0: don’t invert; 1: invert

PIN_ALLOWED_CTL

This register determines which override values are allowed for a given output. If an override value programmed via PIN_OUT_VALUE is not configured as an allowed value, it will not have any effect.

  • Offset: 0x34
  • Reset default: 0x82
  • Reset mask: 0xffff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:16Reserved
15rw0x0flash_wp_l_10: not allowed; 1: allowed
14rw0x0z3_wakeup_10: not allowed; 1: allowed
13rw0x0key2_out_10: not allowed; 1: allowed
12rw0x0key1_out_10: not allowed; 1: allowed
11rw0x0key0_out_10: not allowed; 1: allowed
10rw0x0pwrb_out_10: not allowed; 1: allowed
9rw0x0ec_rst_l_10: not allowed; 1: allowed
8rw0x0bat_disable_10: not allowed; 1: allowed
7rw0x1flash_wp_l_00: not allowed; 1: allowed
6rw0x0z3_wakeup_00: not allowed; 1: allowed
5rw0x0key2_out_00: not allowed; 1: allowed
4rw0x0key1_out_00: not allowed; 1: allowed
3rw0x0key0_out_00: not allowed; 1: allowed
2rw0x0pwrb_out_00: not allowed; 1: allowed
1rw0x1ec_rst_l_00: not allowed; 1: allowed
0rw0x0bat_disable_00: not allowed; 1: allowed

PIN_OUT_CTL

Enables the override function for a specific pin.

  • Offset: 0x38
  • Reset default: 0x82
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7rw0x1flash_wp_l0: disable override; 1: enable override
6rw0x0z3_wakeup0: disable override; 1: enable override
5rw0x0key2_out0: disable override; 1: enable override
4rw0x0key1_out0: disable override; 1: enable override
3rw0x0key0_out0: disable override; 1: enable override
2rw0x0pwrb_out0: disable override; 1: enable override
1rw0x1ec_rst_l0: disable override; 1: enable override
0rw0x0bat_disable0: disable override; 1: enable override

PIN_OUT_VALUE

Sets the pin override value. Note that only the values configured as ‘allowed’ in PIN_ALLOWED_CTL will have an effect. Otherwise the pin value will not be overridden.

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7rw0x0flash_wp_l0: override to 1b0; 1: override to 1b1
6rw0x0z3_wakeup0: override to 1b0; 1: override to 1b1
5rw0x0key2_out0: override to 1b0; 1: override to 1b1
4rw0x0key1_out0: override to 1b0; 1: override to 1b1
3rw0x0key0_out0: override to 1b0; 1: override to 1b1
2rw0x0pwrb_out0: override to 1b0; 1: override to 1b1
1rw0x0ec_rst_l0: override to 1b0; 1: override to 1b1
0rw0x0bat_disable0: override to 1b0; 1: override to 1b1

PIN_IN_VALUE

For SW to read the sysrst_ctrl inputs like GPIO

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7ro0x0flash_wp_lraw flash_wp_l value; before the invert logic
6ro0x0ec_rst_lraw ec_rst_l value; before the invert logic
5ro0x0ac_presentraw ac_present value; before the invert logic
4ro0x0lid_openraw lid_open value; before the invert logic
3ro0x0key2_inraw key2_in value; before the invert logic
2ro0x0key1_inraw key1_in value; before the invert logic
1ro0x0key0_inraw key0_in value; before the invert logic
0ro0x0pwrb_inraw pwrb_in value; before the invert logic

KEY_INTR_CTL

Define the keys or inputs that can trigger the interrupt

  • Offset: 0x44
  • Reset default: 0x0
  • Reset mask: 0x3fff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:14Reserved
13rw0x0flash_wp_l_L2H0: disable, 1: enable
12rw0x0ec_rst_l_L2H0: disable, 1: enable
11rw0x0ac_present_L2H0: disable, 1: enable
10rw0x0key2_in_L2H0: disable, 1: enable
9rw0x0key1_in_L2H0: disable, 1: enable
8rw0x0key0_in_L2H0: disable, 1: enable
7rw0x0pwrb_in_L2H0: disable, 1: enable
6rw0x0flash_wp_l_H2L0: disable, 1: enable
5rw0x0ec_rst_l_H2L0: disable, 1: enable
4rw0x0ac_present_H2L0: disable, 1: enable
3rw0x0key2_in_H2L0: disable, 1: enable
2rw0x0key1_in_H2L0: disable, 1: enable
1rw0x0key0_in_H2L0: disable, 1: enable
0rw0x0pwrb_in_H2L0: disable, 1: enable

KEY_INTR_DEBOUNCE_CTL

Debounce timer control register for key-triggered interrupt

  • Offset: 0x48
  • Reset default: 0x7d0
  • Reset mask: 0xffff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:16Reserved
15:0rw0x7d0debounce_timerDefine the timer value so that the key or input is not oscillating in clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

AUTO_BLOCK_DEBOUNCE_CTL

Debounce timer control register for pwrb_in H2L transition

  • Offset: 0x4c
  • Reset default: 0x7d0
  • Reset mask: 0x1ffff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:17Reserved
16rw0x0auto_block_enable0: disable, 1: enable
15:0rw0x7d0debounce_timerDefine the timer value so that the pwrb_in is not oscillating in clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

AUTO_BLOCK_OUT_CTL

configure the key outputs to auto-override and their value

  • Offset: 0x50
  • Reset default: 0x0
  • Reset mask: 0x77
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:7Reserved
6rw0x0key2_out_value0: override to 1’b0; 1: override to 1’b1
5rw0x0key1_out_value0: override to 1’b0; 1: override to 1’b1
4rw0x0key0_out_value0: override to 1’b0; 1: override to 1’b1
3Reserved
2rw0x0key2_out_sel0: disable auto-block; 1: enable auto-block
1rw0x0key1_out_sel0: disable auto-block; 1: enable auto-block
0rw0x0key0_out_sel0: disable auto-block; 1: enable auto-block

COM_PRE_SEL_CTL

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

  • Reset default: 0x0
  • Reset mask: 0x1f

Instances

NameOffset
COM_PRE_SEL_CTL_00x54
COM_PRE_SEL_CTL_10x58
COM_PRE_SEL_CTL_20x5c
COM_PRE_SEL_CTL_30x60

Fields

BitsTypeResetNameDescription
31:5Reserved
4rw0x0ac_present_sel0: disable, 1: enable
3rw0x0pwrb_in_sel0: disable, 1: enable
2rw0x0key2_in_sel0: disable, 1: enable
1rw0x0key1_in_sel0: disable, 1: enable
0rw0x0key0_in_sel0: disable, 1: enable

COM_PRE_DET_CTL

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
COM_PRE_DET_CTL_00x64
COM_PRE_DET_CTL_10x68
COM_PRE_DET_CTL_20x6c
COM_PRE_DET_CTL_30x70

Fields

BitsTypeResetNameDescription
31:0rw0x0precondition_timer0-60s, each step is 5us(200KHz clock)

COM_SEL_CTL

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

  • Reset default: 0x0
  • Reset mask: 0x1f

Instances

NameOffset
COM_SEL_CTL_00x74
COM_SEL_CTL_10x78
COM_SEL_CTL_20x7c
COM_SEL_CTL_30x80

Fields

BitsTypeResetNameDescription
31:5Reserved
4rw0x0ac_present_sel0: disable, 1: enable
3rw0x0pwrb_in_sel0: disable, 1: enable
2rw0x0key2_in_sel0: disable, 1: enable
1rw0x0key1_in_sel0: disable, 1: enable
0rw0x0key0_in_sel0: disable, 1: enable

COM_DET_CTL

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
COM_DET_CTL_00x84
COM_DET_CTL_10x88
COM_DET_CTL_20x8c
COM_DET_CTL_30x90

Fields

BitsTypeResetNameDescription
31:0rw0x0detection_timer0-60s, each step is 5us(200KHz clock)

COM_OUT_CTL

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

  • Reset default: 0x0
  • Reset mask: 0xf

Instances

NameOffset
COM_OUT_CTL_00x94
COM_OUT_CTL_10x98
COM_OUT_CTL_20x9c
COM_OUT_CTL_30xa0

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw0x0rst_req0: disable, 1: enable
2rw0x0ec_rst0: disable, 1: enable
1rw0x0interrupt0: disable, 1: enable
0rw0x0bat_disable0: disable, 1: enable

COMBO_INTR_STATUS

Combo interrupt source. These registers will only be set if the interrupt action is configured in the corresponding COM_OUT_CTL register.

  • Offset: 0xa4
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw1c0x0combo3_H2L0: case not detected;1: case detected
2rw1c0x0combo2_H2L0: case not detected;1: case detected
1rw1c0x0combo1_H2L0: case not detected;1: case detected
0rw1c0x0combo0_H2L0: case not detected;1: case detected

KEY_INTR_STATUS

key interrupt source

  • Offset: 0xa8
  • Reset default: 0x0
  • Reset mask: 0x3fff

Fields

BitsTypeResetNameDescription
31:14Reserved
13rw1c0x0flash_wp_l_L2H0: case not detected;1: case detected
12rw1c0x0ec_rst_l_L2H0: case not detected;1: case detected
11rw1c0x0ac_present_L2H0: case not detected;1: case detected
10rw1c0x0key2_in_L2H0: case not detected;1: case detected
9rw1c0x0key1_in_L2H0: case not detected;1: case detected
8rw1c0x0key0_in_L2H0: case not detected;1: case detected
7rw1c0x0pwrb_L2H0: case not detected;1: case detected
6rw1c0x0flash_wp_l_H2L0: case not detected;1: case detected
5rw1c0x0ec_rst_l_H2L0: case not detected;1: case detected
4rw1c0x0ac_present_H2L0: case not detected;1: case detected
3rw1c0x0key2_in_H2L0: case not detected;1: case detected
2rw1c0x0key1_in_H2L0: case not detected;1: case detected
1rw1c0x0key0_in_H2L0: case not detected;1: case detected
0rw1c0x0pwrb_H2L0: case not detected;1: case detected