1. OpenTitan
  3. Hardware
  4. 1. Introduction
  5. 2. Top Earlgrey
    ❱
    1. 2.1. Datasheet
    2. 2.2. Design
    3. 2.3. Design Verification
    4. 2.4. Analog Sensor Top
    5. 2.5. Alert Handler
      ❱
      1. 2.5.1. Theory of Operation
      2. 2.5.2. Design Verification
        ❱
        1. 2.5.2.1. Testplan
      4. 2.5.3. Programmer's Guide
      5. 2.5.4. Interface and Registers
      6. 2.5.5. Device Interface Functions
      7. 2.5.6. Checklist
    7. 2.6. Interrupt Controller
      ❱
      1. 2.6.1. Theory of Operation
      2. 2.6.2. Design Verification
        ❱
        1. 2.6.2.1. Testplan
      4. 2.6.3. Programmer's Guide
      5. 2.6.4. Interface and Registers
      6. 2.6.5. Device Interface Functions
      7. 2.6.6. Checklist
    9. 2.7. Sensor Control
      ❱
      1. 2.7.1. Theory of Operation
      2. 2.7.2. Programmer's Guide
      3. 2.7.3. Interface and Registers
      4. 2.7.4. Device Interface Functions
      5. 2.7.5. Checklist
    11. 2.8. TL-UL Checklist
    12. 2.9. Pinmux Targets
      ❱
      1. 2.9.1. ASIC Target Pinout and Pinmux Connectivity
      2. 2.9.2. CW310 Target Pinout and Pinmux Connectivity
      3. 2.9.3. NEXYSVIDEO Target Pinout and Pinmux Connectivity
  7. 3. Cores
    ❱
    1. 3.1. Ibex RISC-V Core Wrapper
      ❱
      1. 3.1.1. Design Verification
      2. 3.1.2. Interface and Registers
      3. 3.1.3. Checklist
    3. 3.2. OTBN
      ❱
      1. 3.2.1. Developer Guide
      2. 3.2.2. ISA Guide
      3. 3.2.3. Design Verification
        ❱
        1. 3.2.3.1. Random Instruction Generator
          ❱
          1. 3.2.3.1.1. Internals
          2. 3.2.3.1.2. Configuration
        3. 3.2.3.2. memutil wrapper
        4. 3.2.3.3. OTBN Simulation Software
        5. 3.2.3.4. Tracer
        6. 3.2.3.5. Formal Masking Verification Using Alma
      5. 3.2.4. Functional Coverage
      6. 3.2.5. Interface and Registers
      7. 3.2.6. Checklist
  9. 4. Hardware IP Blocks
    ❱
    1. 4.1. Analog to Digital Converter Control
      ❱
      1. 4.1.1. Theory of Operation
      2. 4.1.2. Design Verification
        ❱
        1. 4.1.2.1. Testplan
      4. 4.1.3. Programmer's Guide
      5. 4.1.4. Checklist
      6. 4.1.5. Interface and Registers
    3. 4.2. AES
      ❱
      1. 4.2.1. Theory of Operation
      2. 4.2.2. Design Verification
        ❱
        1. 4.2.2.1. Testplan
      4. 4.2.3. Programmer's Guide
      5. 4.2.4. Interface and Registers
      6. 4.2.5. Device Interface Functions
      7. 4.2.6. Checklist
    5. 4.3. AON Timer
      ❱
      1. 4.3.1. Theory of Operation
      2. 4.3.2. Design Verification
        ❱
        1. 4.3.2.1. Testplan
      4. 4.3.3. Programmer's Guide
      5. 4.3.4. Interface and Registers
      6. 4.3.5. Device Interface Functions
      7. 4.3.6. Checklist
    7. 4.4. Clock Manager
      ❱
      1. 4.4.1. Theory of Operation
      2. 4.4.2. Design Verification
        ❱
        1. 4.4.2.1. Testplan
      4. 4.4.3. Programmer's Guide
      5. 4.4.4. Interface and Registers
      6. 4.4.5. Device Interface Functions
      7. 4.4.6. Checklist
    9. 4.5. CSRNG
      ❱
      1. 4.5.1. Theory of Operation
      2. 4.5.2. Design Verification
        ❱
        1. 4.5.2.1. Testplan
      4. 4.5.3. Programmer's Guide
      5. 4.5.4. Interface and Registers
      6. 4.5.5. Device Interface Functions
      7. 4.5.6. Checklist
    11. 4.6. EDN
      ❱
      1. 4.6.1. Theory of Operation
      2. 4.6.2. Design Verification
        ❱
        1. 4.6.2.1. Testplan
      4. 4.6.3. Programmer's Guide
      5. 4.6.4. Interface and Registers
      6. 4.6.5. Device Interface Functions
      7. 4.6.6. Checklist
    13. 4.7. Entropy Source
      ❱
      1. 4.7.1. Theory of Operation
      2. 4.7.2. Design Verification
        ❱
        1. 4.7.2.1. Testplan
      4. 4.7.3. Programmer's Guide
      5. 4.7.4. Interface and Registers
      6. 4.7.5. Device Interface Functions
      7. 4.7.6. Checklist
    15. 4.8. Flash Controller
      ❱
      1. 4.8.1. Theory of Operation
      2. 4.8.2. Design Verification
        ❱
        1. 4.8.2.1. Testplan
      4. 4.8.3. Programmer's Guide
      5. 4.8.4. Interface and Registers
      6. 4.8.5. Device Interface Functions
      7. 4.8.6. Checklist
    17. 4.9. GPIO
      ❱
      1. 4.9.1. Theory of Operation
      2. 4.9.2. Design Verification
        ❱
        1. 4.9.2.1. Testplan
      4. 4.9.3. Programmer's Guide
      5. 4.9.4. Interface and Registers
      6. 4.9.5. Device Interface Functions
      7. 4.9.6. Checklist
    19. 4.10. HMAC
      ❱
      1. 4.10.1. Theory of Operation
      2. 4.10.2. Design Verification
        ❱
        1. 4.10.2.1. Testplan
      4. 4.10.3. Programmer's Guide
      5. 4.10.4. Interface and Registers
      6. 4.10.5. Device Interface Functions
      7. 4.10.6. Checklist
    21. 4.11. I2C
      ❱
      1. 4.11.1. Theory of Operation
      2. 4.11.2. Design Verification
        ❱
        1. 4.11.2.1. Testplan
      4. 4.11.3. Programmer's Guide
      5. 4.11.4. Interface and Registers
      6. 4.11.5. Device Interface Functions
      7. 4.11.6. Checklist
    23. 4.12. Key Manager
      ❱
      1. 4.12.1. Theory of Operation
      2. 4.12.2. Design Verification
        ❱
        1. 4.12.2.1. Testplan
      4. 4.12.3. Programmer's Guide
      5. 4.12.4. Interface and Registers
      6. 4.12.5. Device Interface Functions
      7. 4.12.6. Checklist
    25. 4.13. KMAC
      ❱
      1. 4.13.1. Theory of Operation
      2. 4.13.2. Design Verification
        ❱
        1. 4.13.2.1. Testplan
      4. 4.13.3. Programmer's Guide
      5. 4.13.4. Interface and Registers
      6. 4.13.5. Device Interface Functions
      7. 4.13.6. Checklist
    27. 4.14. Life Cycle Controller
      ❱
      1. 4.14.1. Theory of Operation
      2. 4.14.2. Design Verification
        ❱
        1. 4.14.2.1. Testplan
      4. 4.14.3. Programmer's Guide
      5. 4.14.4. Interface and Registers
      6. 4.14.5. Device Interface Functions
      7. 4.14.6. Checklist
    29. 4.15. OTP Controller
      ❱
      1. 4.15.1. Theory of Operation
      2. 4.15.2. Design Verification
        ❱
        1. 4.15.2.1. Testplan
      4. 4.15.3. Programmer's Guide
      5. 4.15.4. Interface and Registers
      6. 4.15.5. Device Interface Functions
      7. 4.15.6. Checklist
    31. 4.16. Pattern Generator
      ❱
      1. 4.16.1. Theory of Operation
      2. 4.16.2. Design Verification
        ❱
        1. 4.16.2.1. Testplan
      4. 4.16.3. Programmer's Guide
      5. 4.16.4. Interface and Registers
      6. 4.16.5. Device Interface Functions
      7. 4.16.6. Checklist
    33. 4.17. Pinmux
      ❱
      1. 4.17.1. Theory of Operation
      2. 4.17.2. Design Verification
        ❱
        1. 4.17.2.1. Testplan
      4. 4.17.3. Programmer's Guide
      5. 4.17.4. Interface and Registers
      6. 4.17.5. Device Interface Functions
      7. 4.17.6. Checklist
    35. 4.18. Pulse Width Modulator
      ❱
      1. 4.18.1. Theory of Operation
      2. 4.18.2. Design Verification
        ❱
        1. 4.18.2.1. Testplan
      4. 4.18.3. Programmer's Guide
      5. 4.18.4. Interface and Registers
      6. 4.18.5. Device Interface Functions
      7. 4.18.6. Checklist
    37. 4.19. Power Management
      ❱
      1. 4.19.1. Theory of Operation
      2. 4.19.2. Design Verification
        ❱
        1. 4.19.2.1. Testplan
      4. 4.19.3. Programmer's Guide
      5. 4.19.4. Interface and Registers
      6. 4.19.5. Device Interface Functions
      7. 4.19.6. Checklist
    39. 4.20. ROM Control
      ❱
      1. 4.20.1. Theory of Operation
      2. 4.20.2. Design Verification
        ❱
        1. 4.20.2.1. Testplan
      4. 4.20.3. Programmer's Guide
      5. 4.20.4. Interface and Registers
      6. 4.20.5. Device Interface Functions
      7. 4.20.6. Checklist
    41. 4.21. Reset Manager
      ❱
      1. 4.21.1. Theory of Operation
      2. 4.21.2. Design Verification
        ❱
        1. 4.21.2.1. Testplan
      4. 4.21.3. Programmer's Guide
      5. 4.21.4. Interface and Registers
      6. 4.21.5. Device Interface Functions
      7. 4.21.6. Checklist
    43. 4.22. RISC-V Debug Manager
      ❱
      1. 4.22.1. Design Verification
        ❱
        1. 4.22.1.1. Testplan
      3. 4.22.2. Interface and Registers
      4. 4.22.3. Checklist
    45. 4.23. SPI Device
      ❱
      1. 4.23.1. Theory of Operation
      2. 4.23.2. Design Verification
        ❱
        1. 4.23.2.1. Testplan
      4. 4.23.3. Programmer's Guide
      5. 4.23.4. Interface and Registers
      6. 4.23.5. Device Interface Functions
      7. 4.23.6. Checklist
    47. 4.24. SPI Host
      ❱
      1. 4.24.1. Theory of Operation
      2. 4.24.2. Design Verification
        ❱
        1. 4.24.2.1. Testplan
      4. 4.24.3. Programmer's Guide
      5. 4.24.4. Interface and Registers
      6. 4.24.5. Device Interface Functions
      7. 4.24.6. Checklist
    49. 4.25. SRAM Controller
      ❱
      1. 4.25.1. Theory of Operation
      2. 4.25.2. Design Verification
        ❱
        1. 4.25.2.1. Testplan
      4. 4.25.3. Programmer's Guide
      5. 4.25.4. Interface and Registers
      6. 4.25.5. Device Interface Functions
      7. 4.25.6. Checklist
    51. 4.26. System Reset Controller
      ❱
      1. 4.26.1. Design Verification
        ❱
        1. 4.26.1.1. Testplan
      3. 4.26.2. Interface and Registers
      4. 4.26.3. Device Interface Functions
      5. 4.26.4. Checklist
    53. 4.27. Timer
      ❱
      1. 4.27.1. Theory of Operation
      2. 4.27.2. Design Verification
        ❱
        1. 4.27.2.1. Testplan
      4. 4.27.3. Programmer's Guide
      5. 4.27.4. Interface and Registers
      6. 4.27.5. Device Interface Functions
      7. 4.27.6. Checklist
    55. 4.28. TL-UL Bus
      ❱
      1. 4.28.1. Design Verification
        ❱
        1. 4.28.1.1. Testplan
        2. 4.28.1.2. Protocol Checker
    57. 4.29. UART
      ❱
      1. 4.29.1. Theory of Operation
      2. 4.29.2. Design Verification
        ❱
        1. 4.29.2.1. Testplan
      4. 4.29.3. Programmer's Guide
      5. 4.29.4. Interface and Registers
      6. 4.29.5. Device Interface Functions
      7. 4.29.6. Checklist
    59. 4.30. USB 2.0
      ❱
      1. 4.30.1. Theory of Operation
      2. 4.30.2. Design Verification
        ❱
        1. 4.30.2.1. Testplan
      4. 4.30.3. Programmer's Guide
      5. 4.30.4. Suspending and Resuming
      6. 4.30.5. Interface and Registers
      7. 4.30.6. Device Interface Functions
      8. 4.30.7. Checklist
    61. 4.31. lowRISC Hardware Primitives
      ❱
      1. 4.31.1. Two Input Clock
      2. 4.31.2. Flash Wrapper
      3. 4.31.3. Keccak Permutation
      4. 4.31.4. Linear Feedback Shift Register
      5. 4.31.5. Packer
      6. 4.31.6. Packer FIFO
      7. 4.31.7. Present Scrambler
      8. 4.31.8. Prince Scrambler
      9. 4.31.9. SRAM Scrambler
      10. 4.31.10. Pseudo Random Number Generator
  11. 5. Common SystemVerilog and UVM Components
    ❱
    1. 5.1. ALERT_ESC Agent
    2. 5.2. Bus Params Package
    3. 5.3. Comportable IP Testbench Architecture
    4. 5.4. Common Interfaces
    5. 5.5. CSR Utils
    6. 5.6. CSRNG Agent
    7. 5.7. DV Library Classes
    8. 5.8. DV Utils
    9. 5.9. FLASH_PHY_PRIM Agent
    10. 5.10. I2C Agent
    11. 5.11. JTAG Agent
    12. 5.12. JTAG DMI Agent
    13. 5.13. JTAG RISCV Agent
    14. 5.14. KEY_SIDELOAD Agent
    15. 5.15. KMAC_APP Agent
    16. 5.16. Memory Backdoor Scoreboard
    17. 5.17. Memory Backdoor Utility
    18. 5.18. Memory Model
    19. 5.19. PATTGEN Agent
    20. 5.20. PUSH_PULL Agent
    21. 5.21. PWM Monitor
    22. 5.22. RNG Agent
    23. 5.23. Scoreboard
    24. 5.24. Simulation SRAM
    25. 5.25. SPI Agent
    26. 5.26. String Utils
    27. 5.27. Test Vectors
    28. 5.28. Tile Link Agent
    29. 5.29. UART Agent
    30. 5.30. USB20 Agent
  14. Software
  15. 6. Introduction
  16. 7. Build Software
  17. 8. Device Software
    ❱
    1. 8.1. Device Libraries
      ❱
      1. 8.1.1. DIF Library
        ❱
        1. 8.1.1.1. ADC Checklist
        2. 8.1.1.2. AES Checklist
        3. 8.1.1.3. Alert Handler Checklist
        4. 8.1.1.4. Always-On Timer Checklist
        5. 8.1.1.5. Clock Manager Checklist
        6. 8.1.1.6. CSRNG Checklist
        7. 8.1.1.7. EDN Checklist
        8. 8.1.1.8. Entropy Source Checklist
        9. 8.1.1.9. Flash Controller Checklist
        10. 8.1.1.10. GPIO Checklist
        11. 8.1.1.11. HMAC Checklist
        12. 8.1.1.12. I2C Checklist
        13. 8.1.1.13. Key Manager Checklist
        14. 8.1.1.14. KMAC Checklist
        15. 8.1.1.15. Lifecycle Checklist
        16. 8.1.1.16. OTBN Checklist
        17. 8.1.1.17. OTP Controller Checklist
        18. 8.1.1.18. Pattern Generator Checklist
        19. 8.1.1.19. Pin Multiplexer Checklist
        20. 8.1.1.20. PWM Checklist
        21. 8.1.1.21. Power Manager Checklist
        22. 8.1.1.22. ROM Checklist
        23. 8.1.1.23. Reset Manager Checklist
        24. 8.1.1.24. RV Core Ibex Checklist
        25. 8.1.1.25. PLIC Checklist
        26. 8.1.1.26. RV Timer Checklist
        27. 8.1.1.27. Sensor Controller Checklist
        28. 8.1.1.28. SPI Device Checklist
        29. 8.1.1.29. SPI Host Checklist
        30. 8.1.1.30. SRAM Controller Checklist
        31. 8.1.1.31. System Reset Controller Checklist
        32. 8.1.1.32. UART Checklist
        33. 8.1.1.33. USB Checklist
      3. 8.1.2. Top-Level Test Libraries
        ❱
        1. 8.1.2.1. On-Device Test Framework
      5. 8.1.3. OpenTitan Standard Library
        ❱
        1. 8.1.3.1. Freestanding C Headers
    3. 8.2. Silicon Creator Software
      ❱
      1. 8.2.1. Manufacturing Firmware
      2. 8.2.2. ROM
        ❱
        1. 8.2.2.1. Memory Protection
        2. 8.2.2.2. E2E tests
        3. 8.2.2.3. Signing Keys
      4. 8.2.3. Manifest Format
    5. 8.3. Top-Level Tests
      ❱
      1. 8.3.1. Manufacturer Test Hooks
      2. 8.3.2. Crypto Library Tests
  19. 9. Host Software
  21. Tooling
  22. 10. Tools Overview
  23. 11. Design-Related Tooling
  24. 12. dvsim
    ❱
    1. 12.1. Design Document
    2. 12.2. Testplanner
    3. 12.3. Glossary
  26. 13. fpvgen: Initial FPV Testbench Generation
  27. 14. reggen & regtool: Register Generator
    ❱
    1. 14.1. Setup and use of regtool
  29. 15. ralgen: FuseSoC UVM RAL Generator
  30. 16. uvmdvgen: Initial Testbench Auto-generation
  31. 17. tlgen: Crossbar Generation
  32. 18. ipgen: Generate IP Blocks from IP Templates
  33. 19. topgen: Top Generator
  34. 20. vendor: Vendoring In Tool
  35. 21. i2csvg: Generate SVGs of I2C Commands
  37. Contributing
  38. 22. Contributing
    ❱
    1. 22.1. Detailed Contribution Guide
    2. 22.2. Directory Structure
    3. 22.3. Continueous Intergration
    4. 22.4. Top-Level Design and Targets
    5. 22.5. GitHub Notes
    6. 22.6. Bazel Notes
    7. 22.7. Using the Container
  40. 23. Contributing to Hardware
    ❱
    1. 23.1. Comportability
    2. 23.2. Hardware Design
    3. 23.3. Design Methodology
    4. 23.4. Vendoring in Hardware
    5. 23.5. Linting
    6. 23.6. Synthesis Flow
  42. 24. Contributing to Verification
    ❱
    1. 24.1. Verification Methodology
    2. 24.2. Security Countermeasure Verification Framework
    3. 24.3. Assertions
  44. 25. Contributing to Software
    ❱
    1. 25.1. Device Interface Functions
    2. 25.2. Writing and Building Software for OTBN
  46. 26. Style Guides
    ❱
    1. 26.1. HJSON
    2. 26.2. Python
    3. 26.3. C & C++
    4. 26.4. Markdown
    5. 26.5. RISC-V Assembly
    6. 26.6. OTBN Assembly
    7. 26.7. Guidance for Volatile
  48. 27. Developing on an FPGA
    ❱
    1. 27.1. Get a Board
    2. 27.2. FPGA Reference Manual
  51. Project Governance
  52. 28. Introduction
  53. 29. Committers
  54. 30. RFC Process
  55. 31. Generalized Priority Definitions
  56. 32. OpenTitan Technical Committee
  57. 33. Hardware Development Stages
  58. 34. Signoff Checklist
  60. Security
  61. 35. Security
  62. 36. Implementation Guidelines
    ❱
    1. 36.1. Secure Hardware Design Guidelines
  64. 37. Logical Security Model
  65. 38. Security Model Specification
    ❱
    1. 38.1. Device Attestation
    2. 38.2. Device Life Cycle
    3. 38.3. Device Provisioning
    4. 38.4. Firmware Update
    5. 38.5. Identities and Root Keys
    6. 38.6. Ownership Transfer
    7. 38.7. Secure Boot
  67. 39. Lightweight Threat Model
  69. Use Cases
  70. 40. Use Cases
  71. 41. Platform Integrity Module
  72. 42. Trusted Platform Module
  73. 43. Universal 2nd-Factor Security Key
  75. Rust for C Developers
  76. 44. Rust for Embedded C Programmers

OpenTitan Documentation