Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module mbx has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): core_tl_d, soc_tl_d
  • Bus Host Interfaces (TL-UL): sram_tl_h
  • Peripheral Pins for Chip IO: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
doe_intr_supportlogicunireq1
doe_intr_enlogicunireq1
doe_intrlogicunireq1
doe_async_msg_supportlogicunireq1
racl_policiestop_racl_pkg::racl_policy_vecunircv1Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register.
racl_errortop_racl_pkg::racl_error_logunireq1RACL error log information of this module.
sram_tl_htlul_pkg::tlreq_rspreq1
core_tl_dtlul_pkg::tlreq_rsprsp1
soc_tl_dtlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
mbx_readyEventA new object was received in the inbound mailbox.
mbx_abortEventAn abort request was received from the requester.
mbx_errorEventThe mailbox instance generated an error.

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
recov_faultThis recoverable alert is triggered when memory with invalid ECC (e.g., uninitialized memory) or at an invalid address is accessed.

Security Countermeasures

Countermeasure IDDescription
MBX.BUS.INTEGRITYEnd-to-end bus integrity scheme.
MBX.ADDRESS_RANGE.CONFIG.REGWEN_MUBIPrivate SRAM memory range is software multibit lockable.