Primitive Component: Packer FIFO


prim_packer_fifo is a module that supports three modes of operation: packing, unpacking, and single depth FIFO modes. Packing mode is where the input data width is less than the output data width. Unpacking mode is where the input data width is greater than the output data width. Single depth FIFO is where the input and output data widths are the same. Because masking options are not supported, the larger data size must be an even multiple of the smaller size. The controls for this module are modeled after the prim_fifo_sync module, both in name and functional behavior. It is one of a set of shared primitive modules available for use within OpenTitan as referred to in the Comportability Specification section on shared primitives.


InWintInput data width
OutWintOutput data width

Signal Interfaces

clk_iinputInput clock
rst_niinputInput reset, negative active
clr_iinputInput clear, clears all internal flops.
wvalid_iinputWrites data into the first available position.
wdata_i[InW]inputInput data.
wready_ooutputIndicates if prim_packer_fifo is able to accept data.
rvalid_ooutputIndicates if output data is valid.
rdata_o[OutW]outputOutput data.
rready_iinputOutput data is popped from the FIFO.
depth_ooutputIndicates the fullness of the FIFO.

Theory of Operations

wvalid_i   |          |      rvalid_o
---------->|          |--------------->
wdata_i    |   Flop   |      rdata_o
=====/====>|   FIFO   |=======/=======>
  [InW]    |          |      [OutW]
           |          |      depth_o
           |          |--------------->
wready_o   |          |      rready_i
<----------|          |<---------------
           |          |

In pack mode, prim_packer_fifo accepts InW bits of data. On a wvalid_i/ wready_o handshake, wdata_i is stored to internal registers and accumulated until OutW data has been gathered. Once the FIFO is full, a single pop (when rvalid_o and rready_i are coincident), will clear the data and depth values on the next clock cycle. The complimentary flow occurs when theprim_packer_fifo module is in unpack mode.

The internal register size is the greater of InW and OutW bits. Timing diagrams are shown in the header of the prim_packer_fifo module.