Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module ac_range_check has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
range_check_overwriteprim_mubi_pkg::mubi8unircv1Overwrites all ranges and let all requests pass through.
ctn_tl_h2dtlul_pkg::tl_h2dunircv1TL-UL input port (request part), synchronous
ctn_tl_d2htlul_pkg::tl_d2hunireq1TL-UL input port (response part), synchronous
ctn_filtered_tl_h2dtlul_pkg::tl_h2dunireq1Filtered TL-UL output port (request part), synchronous
ctn_filtered_tl_d2htlul_pkg::tl_d2hunircv1Filtered TL-UL output port (response part), synchronous
racl_policiestop_racl_pkg::racl_policy_vecunircv1Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register.
racl_errortop_racl_pkg::racl_error_logunireq1RACL error log information of this module.
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
deny_cnt_reachedEventDeny counter has reached threshold.

Security Alerts

Alert NameDescription
recov_ctrl_update_errThis recoverable alert is triggered upon detecting an update error in the shadowed Control Register.
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected or the internal counter has an error.

Security Countermeasures

Countermeasure IDDescription
AC_RANGE_CHECK.BUS.INTEGRITYEnd-to-end bus integrity scheme.