RSTMGR DV document
- Verify all RSTMGR IP features by running dynamic simulations with a SV/UVM based testbench
- Develop and run all tests based on the testplan below towards closing code and functional coverage on the IP and all of its sub-modules
- Verify TileLink device protocol compliance with an SVA based testbench
For detailed information on RSTMGR design features, please see the RSTMGR HWIP technical specification.
RSTMGR testbench has been constructed based on the CIP testbench architecture.
Top level testbench
The top level testbench is located at
It instantiates the RSTMGR DUT module
In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into
- Clock and reset interface
- TileLink host interface
- RSTMGR interface
- Alerts (
- Devmode (
Common DV utility components
The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
Global types & methods
All common types and methods defined at the package level can be found in
rstmgr_env_pkg. Some of them in use are:
typedef logic [NumSwResets-1:0] sw_rst_t; typedef logic [$bits(alert_pkg::alert_crashdump_t)-1:0] linearized_alert_dump_t; typedef virtual pwrmgr_rstmgr_sva_if #(.CHECK_RSTREQS(0)) parameterized_pwrmgr_rstmgr_sva_vif;
The RSTMGR testbench instantiates (already handled in CIP base env) tl_agent. This provides the ability to drive and independently monitor random traffic via the TL host interface into the RSTMGR device.
RSTMGR testbench instantiates (already handled in CIP base env) alert_agents: [list alert names]. The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in RSTMGR device.
UVM RAL Model
The RSTMGR RAL model is created with the
ralgen FuseSoC generator script automatically when the simulation is at the build stage.
It can be created manually by invoking
The following test sequences and covergroups are described in more detail in the testplan at
hw/ip/pwrmgr/data/rstmgr_testplan.hjson, and also included below.
This IP is only reset via the
por_n_i input, and by
scan_rst_ni qualified by
scanmode_i being active.
rst_ni input is connected to its own
resets_o.rst_por_io_div4_n output, so the reset output from
clk_rst_if is not connected.
Similarly, all reset outputs from other
clk_rst_if instances are ignored, and only their clock output is used.
This is consistent with this IP being in charge of all derived resets in the chip.
Besides the POR resets above, the test sequences mostly assert various reset requests from pwrmgr and trigger resets vir RESET_REQ CSR. Alert and CPU dump info is randomized and checked on resets.
The test sequences reside in
All test sequences are extended from
rstmgr_base_vseq, which is extended from
cip_base_vseq and serves as a starting point.
It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
Some of the most commonly used tasks / functions are as follows:
wait_for_cpu_out_of_reset: Waits for the
resets_o.rst_sys_noutput to go high, indicating the CPU is out of reset and CSRs can be accessed.
check_cpu_dump_info: Reads and compares each field in the
cpu_infoCSR against the given cpu dump.
check_software_reset_csr_and_pins: Reads and compares the
sw_rst_ctrl_nCSR and the output reset ports against the given value.
Other sequences follow:
rstmgr_smoke_vseqtests the rstmgr through software initiated low power, peripheral reset, ndm reset, and software initiated resets.
resets_o.rst_por_aon_noutput is asserted after 32 stable cycles of
rstmgr_sw_rst_vseqtests the functionality provided by the
reset_infoCSR contents correspond to the different resets.
cpu_infoCSR contents capture to the
cpu_dump_ipresent at the time of a reset.
alert_infoCSR contents capture to the
alert_dump_ipresent at the time of a reset.
To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model. The following covergroups have been developed to prove that the test intent has been adequately met:
Most self checking is done using SVA, and via explicit CSR reads. The latter are described in the testplan.
- TLUL assertions: The
tb/rstmgr_bind.svfile binds the
tlul_assertassertions to the IP to ensure TileLink interface protocol compliance.
- Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
- Response to pwrmgr’s
rst_sys_reqinputs: these trigger transitions in
rst_sys_rst_noutputs. Checked via SVAs in
- Response to
cpu_i.ndmreset_reqinput: after it is asserted, rstmgr’s
rst_sys_src_nshould go active. Checked via SVA in
- Resets cascade hierarchically per Reset Topology.
Checked via SVA in
- POR must be active for at least 32 consecutive cycles before going inactive before output resets go inactive.
Checked via SVA in
- The scan reset
scanmode_itriggers all cascaded resets that
por_n_idoes. Checked via SVA in
- Software resets to peripherals also cascade hierarchically.
Checked via SVA in
- The output
rst_en_ofor alert_handler tracks their corresponding resets. Checked via SVA in both
cpu_info_attrindicate the number of 32-bit words needed to capture their inputs. Checked via SVA in
Testing V2S components
The rstmgr_cnsty_chk module is a D2S component.
It depends on very specific timing, and requires tampering stimulus to verify its functionality.
It has its own separate dv environment and tests at
It is excluded from coverage for the rstmgr dv tests.
Building and running tests
We are using our in-house developed regression tool for building and running our tests and regressions. Please take a look at the link for detailed information on the usage, capabilities, features and known issues. Here’s how to run a smoke test:
$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/rstmgr/dv/rstmgr_sim_cfg.hjson -i rstmgr_smoke