Randomly read, program or erase (page or a bank) a randomized chunk of flash memory. Only the data partition is accessed. No extra features enabled. Flash memory is invalidated and the targeted chunk is initialized with random data for reads and all 1s for writes. Interrupts are not enabled, Completion is ascertained through polling. The success of each operation is verified via backdoor.
Perform host direct read on the single page of Data partition. First Flash memory is initialized with random values and then it is being read directly by Host interface. Finally, backdoor read is used for checking read data.
Verify the reset values as indicated in the RAL specification.
Verify accessibility of CSRs as indicated in the RAL specification.
Verify no aliasing within individual bits of a CSR.
Verify no aliasing within the CSR address space.
Verify random reset during CSR/memory access.
Verify regwen CSR and its corresponding lockable CSRs.
This is only applicable if the block contains regwen and locakable CSRs.
Verify accessibility of all memories in the design.
Verify partial-accessibility of all memories in the design.
Perform flash protocol controller read, program and erase on the single page of one bank within Data partition. Finally perform read on same location in order to test if previous operation was done successfully.
Perform back-to-back direct reads via Host in order to test bandwidth of hardware host interface. In addition, perform stalls to test pipeline structure. Enable scramble to test pipeline structure.
Perform RMA entry requests and check afterwards that the software has no access to the Flash. After RMA entry, verify that the content of the flash is wiped out.
Perform operations via the Flash Software Interface, and at the same time invoke a Hardware RMA operation. This verifies the arbitration within the Flash Protocol Controller. The arbiter should allow any outstanding Software operations to complete before the RMA starts. When the RMA completes the RMA FSM remains in its final state until Reset and software access is blocked.
Perform erase suspend when erase is ongoing and also when erase is not ongoing. Check if request is immediately cleared in case when no erase is ongoing. Check if request is cleared in case when suspend is handled. Read affected bank in order to verify erase suspension feature.
Reset controller at every state of programming operation and check if controller doesn't have any residue for the next operation.
Entire memory is accessed by Controller and directly by Host. In addition, Data partitions can be directly read by Software(Flash controller) and hardware hosts, while Info partitions can be read only by the Flash controller.
Perform following sequences of operations: read/program/read and read/erase/read in order to test read buffer eviction properly. Read should be executed by both Software and Host interface. All combinations should be tested. Covergroup for this hazardous behavior is rd_buff_evict_cg.
Run read eviction test with multiple memory protection configs. Each config should enable read but randomize all other fields including scramble and ecc enable.
Test arbitration within Flash Physical Controller by reading from both interfaces at the same time. Perform continuously direct read data from host interface and at the same time, perform all operations READ/PROGRAM/ERASE from the flash controller is in progress. Perform parallel operations at addresses of different banks and also on same bank. Expect that operations are successfully executed.
At same time, perform two read operations and the same time via host and via controller. At same time, perform read operation via host and program operation via controller. Perform mentioned parallel operations at different addresses and on the same address. Expect that operations are successfully executed.
Perform READ/ PROGRAM/ ERASE operations over protected regions and pages of data and info partitions. Use set and reset values of corresponding read, program and erase enable bits. Test boundary values of regions. Test overlap of regions in which lower region wins arbitration.
Verify the Code Fetch Feature. Reads for instructions via the Hardware Interface are allowed if a specific value is written to the EXEC csr.
Sanity + both, legal data and info partitions are accessed. In future, support for multiple info partitions may be added - those will be covered as well.
Perform accesses in order to provoke memory permission errors. Test the Software interface (Erase, Program, Read). Related covergroup is sw_error_cg.
Perform accesses in order to provoke the 'program resolution' error. Test via the Software interface. Related covergroup is sw_error_cg.
Perform accesses in order to provoke the 'program type' error. Test via the Software interface. Related covergroup is sw_error_cg.
Create sw read error during hw seed read process. Check all errors are properly detected.
Send following error transactions with normal traffic and see any catastrophic event happens.
Set flash ctrl disable by hw (lc_escalate_en = On) or sw (flash_ctrl.dis = MuBi4True). And try to access flash ctrl and check the access attempt to be failed.
Check jtag input / output ports connectivity with lc_nvm_debug_en. Connections are set only when lc_nvm_debug_en = On.
Verify the secret information partitions. Accessibility is controlled by the Life Cycle Controller Seeds are read upon flash controller initialization and sent to the Key Manager, additionally verify that scramble Keys are Read from the OTP and sent into the Flash Ctlr. Also erify that programmed Secret Partitions retain their values through a Reset Cycle.
Verify the isolated information partitions. Accessablity is controlled by Life Cycle Controller. Verify Partition can be erase, written and programmed, with HW control, and wipes after an RMA.
Perform accesses in order to raise all interrupts given in register map. Check behaviour of Interrupt Enable and Status Registers.
Send invalid command in order to check that it does not affect memory content. Check that recovery alert is triggered.
Flash middle operation reset test. Send reset via power ready signal in the middle of operation program, read, erase and erase suspend.
Run read / write test and inject double bit error randomly for read transactions -- both direct and controller read. Check op_status.err and err_code.rd_err are asserted for ctrl read and tlul response error for host read. Check fatal alert is asserted for reliability ecc errors (double bits) and integrity ECC errors.
Run read only or read write test with randomly injected single bit error. All single bit error should be corrected and all read data should be matched with expected written value.
Run read / write test and inject single bit error randomly for read transactions. - both direct and controller read - Adjust error injection ratio s.t. counter is not saturated. Compare counter values for both bank with expected counter values.
Run read / write test and inject a single bit error randomly either direct or controller read. Once error is injected a certain transaction, wait for the transaction to be completed and compare ecc_single_err_addr register with the expected value. Do this for multiple rounds for both banks.
Enable scrambling, along with randomized scramble keys. Program a fresh chunk of memory and read back (both, via controller and host) to ensure data integrity. On program, verify via backdoor scrambling was done on the raw data correctly. When reading via host, read the same memory via host multiple times back-to-back and ensure the timing is correct (subsequent reads should be faster). When scrambling is not enabled, ensure that the raw data is written and read back.
Enable ECC and disable scrambling for all regions. Initialize flash with erased state (FlashMemInitSet). Execute random number of writes without writing the same location twice. Record all write locations(Minimum resolution of location is 8bytes). After that, execute write and read back test for random page and check
Verify error handling process duing the rma wipe process. In normal rma process, inject bit error at the write path (tb.dut.u_eflash.gen_flash_cores.u_core.gen_prog_data.u_prog.pack_data). This should make debug_state to flash_ctrl_env_pkg::FlashLcIvalid and fatal error (std_fault_status.lcmgr_err) should be triggered.
Verify common intr_test CSRs that allows SW to mock-inject interrupts.
Access out of bounds address and verify correctness of response / behavior
Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.
Verify shadowed registers' update error.
Verify reading a shadowed register will clear its staged value.
Verify shadowed registers' storage error.
Verify toggle shadowed_rst_n pin can trigger storage error.
Run shadow_reg_update_error sequence in parallel with csr_rw sequence.
Verify that the data integrity check violation generates an alert.
Verify the countermeasure(s) REG.BUS.INTEGRITY. This entry is covered by tl_access_test (hw/dv/tools/dvsim/tests/tl_access_tests.hjson)
Verify the countermeasure(s) HOST.BUS.INTEGRITY. This entry is covered by tl_access_test (hw/dv/tools/dvsim/tests/tl_access_tests.hjson)
Verify the countermeasure(s) MEM.BUS.INTEGRITY. For read path, inject error to tb.dut.u_eflash.gen_flash_cores[*].u_core.u_rd.gen_bufs. u_rd_buf.data_i read data error will trigger fault_status.phy_storage_err and err_code.rd_err. For write path, inject error to tb.dut.u_prog_fifo.wdata_i This will trigger fatal_std_err.prog_intg_err and err_code.prog_err
Verify the countermeasure(s) SCRAMBLE.KEY.SIDELOAD. The scrambling key is sideloaded from OTP and thus unreadable by SW. TBD
Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI.
Verify the countermeasure(s) CTRL.CONFIG.REGWEN.
Verify the countermeasure(s) DATA_REGIONS.CONFIG.REGWEN.
Verify the countermeasure(s) DATA_REGIONS.CONFIG.SHADOW.
Verify the countermeasure(s) INFO_REGIONS.CONFIG.REGWEN.
Verify the countermeasure(s) INFO_REGIONS.CONFIG.SHADOW.
Verify the countermeasure(s) BANK.CONFIG.REGWEN.
Verify the countermeasure(s) BANK.CONFIG.SHADOW.
Verify the countermeasure(s) MEM.CTRL.GLOBAL_ESC. Send a few flash access commands and disable flash access by setting lc_escalate_en to lc_ctrl_pkg::On. Check
Verify the countermeasure(s) MEM.CTRL.LOCAL_ESC. Send a few flash access commands and disable flash access by triggering std_fault. Check
Verify the countermeasure(s) MEM_DISABLE.CONFIG.MUBI.
Verify the countermeasure(s) EXEC.CONFIG.REDUN.
Verify the countermeasure(s) MEM.SCRAMBLE.
Verify the countermeasure(s) MEM.INTEGRITY.
Verify the countermeasure(s) RMA_ENTRY.MEM.SEC_WIPE. RMA entry wipes flash memory with random data.
Verify the countermeasure(s) CTRL.FSM.SPARSE. Error is injected by global test. Follwing state machines are in this category.
Verify the countermeasure(s) PHY.FSM.SPARSE. Error is injected by global test on tb.dut.u_eflash.gen_flash_cores[*].u_core.state_q. Error from this state machine will trigger std_fault_status.phy_fsm_err.
Verify the countermeasure(s) PHY_PROG.FSM.SPARSE. Error is injected by global test on tb.dut.u_eflash.gen_flash_cores[*].u_core.gen_prog_data.u_prog.state_q. Error from this state machine will trigger std_fault_status.phy_fsm_err.
Verify the countermeasure(s) CTR.REDUN. Error is injected by global test. Follwing counters are in this category.
Verify the countermeasure(s) PHY_ARBITER.CTRL.REDUN.
The phy arbiter for controller and host is redundant. The arbiter has two instance underneath that are constantly compared to each other. tb.dut.u_eflash.gen_flash_cores.u_core.u_host_arb.gen_input_bufs.u_req_buf.out_o[1:0] tb.dut.u_eflash.gen_flash_cores.u_core.u_host_arb.gen_input_bufs.u_req_buf.out_o[1:0]
Make output of both mismatch and check fault_status.arb_err is triggered.
Verify the countermeasure(s) PHY_HOST_GRANT.CTRL.CONSISTENCY.
A host transaction was granted to the muxed partition, this is illegal. @ tb.dut.u_eflash.gen_flash_cores.u_core.host_gnt, force tb.dut.u_eflash.gen_flash_cores.u_core.muxed_part = 1 and check fault_status.host_gnt_err.
Verify the countermeasure(s) PHY_ACK.CTRL.CONSISTENCY.
Trigger tb.dut.u_eflash.gen_flash_cores.u_core.spurious_ack_o as follows: @ tb.dut.u_eflash.gen_flash_cores.u_core.ctrl_fsm_idle force tb.dut.u_eflash.gen_flash_cores.u_core.ctrl_rsp_vld = 1 or @ tb.dut.u_eflash.gen_flash_cores.u_core.host_outstanding[1:0] == 0 force tb.dut.u_eflash.gen_flash_cores.u_core.host_req_done_o = 1 Check fault_status.spurious_ack
Verify the countermeasure(s) FIFO.CTR.REDUN. Error is injected by global test. Follwing fifos are in this category.
Verify the countermeasure(s) MEM_TL_LC_GATE.FSM.SPARSE.
Verify the countermeasure(s) PROG_TL_LC_GATE.FSM.SPARSE.
Create 'fast' and 'slow' read path using scramble enable. Send flash read requst over slow path followed by fast path. While return data comes from fast path first but they are expected to be returned in request order.
This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.
Covers that all operations READ/PROGRAM/ERASE/UNKNOWN have been tested. Covers that ERASE operation is performed on a page and on entire bank. Covers data and info partitions selection. All valid combinations of the above will also be crossed.
Covers if request of erase suspension occured.
Covers eviction with mp_region_cfgs for data and info regions. Sample all 4 rd_buf status. When each buffer hazard is set, capture the address stored in the buffer. Then search from tb data base to see which region the address belong to. After that record the config value (scrambe_en and ecc_en) of the region. Use cross over buffer index, the operation to cause the eviction and the region config values.
Covers whether dut received valid or invalid key value from ral.exec register. Cross with tlul.instr_types.
Covers that all possible fifo statuses generate interrupts for operations READ/PROGRAM. Covers both boundary values 0 and 31. Also covers acceptable distributions within ranges.
Covers that all possible combinations for following sequences of operations READ/PROGRAM/READ and READ/ERASE/READ are executed. Software Interface can perform all three operations READ/PROGRAM/ERASE while Host Interface can perform direct READ.
Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs.
Cover rma operation is executed regardless of when flash_init started. flash_ctrl_hw_rma runs rma operation and flash init in parallel thread. In this test, sample rma state when flash init starts. If rma state is StRmaIdle, which means rma is not started. So it confirms rma start after flash init start. If rma state is [StRmaPageSel:StRmaInvalid], which mean rma is on going. So it confirms rma start before flash init start.
Cover all shadow register errors for each register field.
For all register fields within the shadowed register, this coverpoint covers the following errors:
Covers following error scenarios given in Flash error code register:
Cover the following error cases on TL-UL bus:
Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.
Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.