Testplan - OpenTitan Documentation

Testpoints

Stage	Name	Tests	Description
V1	smoke	flash_ctrl_smoke	Randomly read, program or erase (page or a bank) a randomized chunk of flash memory. Only the data partition is accessed. No extra features enabled. Flash memory is invalidated and the targeted chunk is initialized with random data for reads and all 1s for writes. Interrupts are not enabled, Completion is ascertained through polling. The success of each operation is verified via backdoor.
V1	smoke_hw	flash_ctrl_smoke_hw	Perform host direct read on the single page of Data partition. First Flash memory is initialized with random values and then it is being read directly by Host interface. Finally, backdoor read is used for checking read data.
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	Verify the reset values as indicated in the RAL specification. Write all CSRs with a random value. Apply reset to the DUT as well as the RAL model. Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_rw	flash_ctrl_csr_rw	Verify accessibility of CSRs as indicated in the RAL specification. Loop through each CSR to write it with a random value. Read the CSR back and check for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	Verify no aliasing within individual bits of a CSR. Walk a 1 through each CSR by flipping 1 bit at a time. Read the CSR back and check for correctness while adhering to its access policies. This verify that writing a specific bit within the CSR did not affect any of the other bits. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_aliasing	flash_ctrl_csr_aliasing	Verify no aliasing within the CSR address space. Loop through each CSR to write it with a random value Shuffle and read ALL CSRs back. All CSRs except for the one that was written in this iteration should read back the previous value. The CSR that was written in this iteration is checked for correctness while adhering to its access policies. It is mandatory to run this test for all available interfaces the CSRs are accessible from. Shuffle the list of CSRs first to remove the effect of ordering.
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	Verify random reset during CSR/memory access. Run csr_rw sequence to randomly access CSRs If memory exists, run mem_partial_access in parallel with csr_rw Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw flash_ctrl_csr_aliasing	Verify regwen CSR and its corresponding lockable CSRs. Randomly access all CSRs Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers Note: If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing. If regwen CSR is HW updated, a separate test should be created to test it. This is only applicable if the block contains regwen and locakable CSRs.
V1	mem_walk	flash_ctrl_mem_walk	Verify accessibility of all memories in the design. Run the standard UVM mem walk sequence on all memories in the RAL model. It is mandatory to run this test from all available interfaces the memories are accessible from.
V1	mem_partial_access	flash_ctrl_mem_partial_access	Verify partial-accessibility of all memories in the design. Do partial reads and writes into the memories and verify the outcome for correctness. Also test outstanding access on memories
V2	sw_op	flash_ctrl_sw_op	Perform flash protocol controller read, program and erase on the single page of one bank within Data partition. Finally perform read on same location in order to test if previous operation was done successfully.
V2	host_read_direct	flash_ctrl_host_dir_rd	Perform back-to-back direct reads via Host in order to test bandwidth of hardware host interface. In addition, perform stalls to test pipeline structure. Enable scramble to test pipeline structure.
V2	rma_hw_if	flash_ctrl_hw_rma flash_ctrl_hw_rma_reset flash_ctrl_lcmgr_intg	Perform RMA entry requests and check afterwards that the software has no access to the Flash. After RMA entry, verify that the content of the flash is wiped out.
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	Perform operations via the Flash Software Interface, and at the same time invoke a Hardware RMA operation. This verifies the arbitration within the Flash Protocol Controller. The arbiter should allow any outstanding Software operations to complete before the RMA starts. When the RMA completes the RMA FSM remains in its final state until Reset and software access is blocked.
V2	erase_suspend	flash_ctrl_erase_suspend	Perform erase suspend when erase is ongoing and also when erase is not ongoing. Check if request is immediately cleared in case when no erase is ongoing. Check if request is cleared in case when suspend is handled. Read affected bank in order to verify erase suspension feature.
V2	program_reset	flash_ctrl_prog_reset	Reset controller at every state of programming operation and check if controller doesn't have any residue for the next operation.
V2	full_memory_access	flash_ctrl_full_mem_access	Entire memory is accessed by Controller and directly by Host. In addition, Data partitions can be directly read by Software(Flash controller) and hardware hosts, while Info partitions can be read only by the Flash controller.
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	Perform following sequences of operations: read/program/read and read/erase/read in order to test read buffer eviction properly. Read should be executed by both Software and Host interface. All combinations should be tested. Covergroup for this hazardous behavior is rd_buff_evict_cg.
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict flash_ctrl_re_evict flash_ctrl_rw_evict_all_en	Run read eviction test with multiple memory protection configs. Each config should enable read but randomize all other fields including scramble and ecc enable.
V2	host_arb	flash_ctrl_phy_arb	Test arbitration within Flash Physical Controller by reading from both interfaces at the same time. Perform continuously direct read data from host interface and at the same time, perform all operations READ/PROGRAM/ERASE from the flash controller is in progress. Perform parallel operations at addresses of different banks and also on same bank. Expect that operations are successfully executed.
V2	host_interleave	flash_ctrl_phy_arb	At same time, perform two read operations and the same time via host and via controller. At same time, perform read operation via host and program operation via controller. Perform mentioned parallel operations at different addresses and on the same address. Expect that operations are successfully executed.
V2	memory_protection	flash_ctrl_mp_regions	Perform READ/ PROGRAM/ ERASE operations over protected regions and pages of data and info partitions. Use set and reset values of corresponding read, program and erase enable bits. Test boundary values of regions. Test overlap of regions in which lower region wins arbitration.
V2	fetch_code	flash_ctrl_fetch_code	Verify the Code Fetch Feature. Reads for instructions via the Hardware Interface are allowed if a specific value is written to the EXEC csr.
V2	all_partitions	flash_ctrl_rand_ops	Sanity + both, legal data and info partitions are accessed. In future, support for multiple info partitions may be added - those will be covered as well.
V2	error_mp	flash_ctrl_error_mp	Perform accesses in order to provoke memory permission errors. Test the Software interface (Erase, Program, Read). Related covergroup is sw_error_cg.
V2	error_prog_win	flash_ctrl_error_prog_win	Perform accesses in order to provoke the 'program resolution' error. Test via the Software interface. Related covergroup is sw_error_cg.
V2	error_prog_type	flash_ctrl_error_prog_type	Perform accesses in order to provoke the 'program type' error. Test via the Software interface. Related covergroup is sw_error_cg.
V2	error_read_seed	flash_ctrl_hw_read_seed_err	Create sw read error during hw seed read process. Check all errors are properly detected.
V2	read_write_overflow	flash_ctrl_oversize_error	Send following error transactions with normal traffic and see any catastrophic event happens. Program flash size longer than 64 bytes. This wil cause prog_win_err. Read flash from controller without settting start op. Issue rd_fifo read more thatn CONTROL.NUM field value. Both will cause d_error in tlul response. Each transaction is terminated gracefully and should not cause data path lock up. Also error status should be check per each transaction.
V2	flash_ctrl_disable	flash_ctrl_disable	Set flash ctrl disable by hw (lc_escalate_en = On) or sw (flash_ctrl.dis = MuBi4True). And try to access flash ctrl and check the access attempt to be failed.
V2	flash_ctrl_connect	flash_ctrl_connect	Check jtag input / output ports connectivity with lc_nvm_debug_en. Connections are set only when lc_nvm_debug_en = On.
V2	stress_all	flash_ctrl_stress_all	combine above sequences in one test to run sequentially, except csr sequence randomly add reset between each sequence
V2	secret_partition	flash_ctrl_hw_sec_otp flash_ctrl_otp_reset	Verify the secret information partitions. Accessibility is controlled by the Life Cycle Controller Seeds are read upon flash controller initialization and sent to the Key Manager, additionally verify that scramble Keys are Read from the OTP and sent into the Flash Ctlr. Also erify that programmed Secret Partitions retain their values through a Reset Cycle.
V2	isolation_partition	flash_ctrl_hw_rma	Verify the isolated information partitions. Accessablity is controlled by Life Cycle Controller. Verify Partition can be erase, written and programmed, with HW control, and wipes after an RMA.
V2	interrupts	flash_ctrl_intr_rd flash_ctrl_intr_wr flash_ctrl_intr_rd_slow_flash flash_ctrl_intr_wr_slow_flash	Perform accesses in order to raise all interrupts given in register map. Check behaviour of Interrupt Enable and Status Registers.
V2	invalid_op	flash_ctrl_invalid_op	Send invalid command in order to check that it does not affect memory content. Check that recovery alert is triggered.
V2	mid_op_rst	flash_ctrl_mid_op_rst	Flash middle operation reset test. Send reset via power ready signal in the middle of operation program, read, erase and erase suspend.
V2	double_bit_err	flash_ctrl_read_word_sweep_derr flash_ctrl_ro_derr flash_ctrl_rw_derr flash_ctrl_derr_detect flash_ctrl_integrity	Run read / write test and inject double bit error randomly for read transactions -- both direct and controller read. Check op_status.err and err_code.rd_err are asserted for ctrl read and tlul response error for host read. Check fatal alert is asserted for reliability ecc errors (double bits) and integrity ECC errors.
V2	single_bit_err	flash_ctrl_read_word_sweep_serr flash_ctrl_ro_serr flash_ctrl_rw_serr	Run read only or read write test with randomly injected single bit error. All single bit error should be corrected and all read data should be matched with expected written value.
V2	singlebit_err_counter	flash_ctrl_serr_counter	Run read / write test and inject single bit error randomly for read transactions. - both direct and controller read - Adjust error injection ratio s.t. counter is not saturated. Compare counter values for both bank with expected counter values.
V2	singlebit_err_address	flash_ctrl_serr_address	Run read / write test and inject a single bit error randomly either direct or controller read. Once error is injected a certain transaction, wait for the transaction to be completed and compare ecc_single_err_addr register with the expected value. Do this for multiple rounds for both banks.
V2	scramble	flash_ctrl_wo flash_ctrl_ro flash_ctrl_rw flash_ctrl_write_word_sweep flash_ctrl_read_word_sweep	Enable scrambling, along with randomized scramble keys. Program a fresh chunk of memory and read back (both, via controller and host) to ensure data integrity. On program, verify via backdoor scrambling was done on the raw data correctly. When reading via host, read the same memory via host multiple times back-to-back and ensure the timing is correct (subsequent reads should be faster). When scrambling is not enabled, ensure that the raw data is written and read back.
V2	filesystem_support	flash_ctrl_fs_sup	Enable ECC and disable scrambling for all regions. Initialize flash with erased state (FlashMemInitSet). Execute random number of writes without writing the same location twice. Record all write locations(Minimum resolution of location is 8bytes). After that, execute write and read back test for random page and check If the locations are in the written record, write data should be all 0 and readback data should match with the written data. If the locations are not in the written record, write data should be random and readback data should match with the written data.
V2	rma_write_process_error	flash_ctrl_rma_err flash_ctrl_hw_prog_rma_wipe_err	Verify error handling process duing the rma wipe process. In normal rma process, inject bit error at the write path (tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.pack_data). This should make debug_state to flash_ctrl_env_pkg::FlashLcIvalid and fatal error (std_fault_status.lcmgr_err) should be triggered.
V2	alert_test	flash_ctrl_alert_test	Verify common `alert_test` CSR that allows SW to mock-inject alert requests. Enable a random set of alert requests by writing random value to alert_test CSR. Check each `alert_tx.alert_p` pin to verify that only the requested alerts are triggered. During alert_handshakes, write `alert_test` CSR again to verify that: If `alert_test` writes to current ongoing alert handshake, the `alert_test` request will be ignored. If `alert_test` writes to current idle alert handshake, a new alert_handshake should be triggered. Wait for the alert handshakes to finish and verify `alert_tx.alert_p` pins all sets back to 0. Repeat the above steps a bunch of times.
V2	intr_test	flash_ctrl_intr_test	Verify common intr_test CSRs that allows SW to mock-inject interrupts. Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s). Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s). Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR. Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set. Clear a random set of interrupts by writing a randomly value to intr_state CSR(s). Repeat the above steps a bunch of times.
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	Access out of bounds address and verify correctness of response / behavior
V2	tl_d_illegal_access	flash_ctrl_tl_errors	Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec TL-UL protocol error cases invalid opcode some mask bits not set when opcode is `PutFullData` mask does not match the transfer size, e.g. `a_address = 0x00`, `a_size = 0`, `a_mask = 'b0010` mask and address misaligned, e.g. `a_address = 0x01`, `a_mask = 'b0001` address and size aren't aligned, e.g. `a_address = 0x01`, `a_size != 0` size is greater than 2 OpenTitan defined error cases access unmapped address, expect `d_error = 1` when `devmode_i == 1` write a CSR with unaligned address, e.g. `a_address[1:0] != 0` write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte write a memory with `a_mask != '1` when it doesn't support partial accesses read a WO (write-only) memory write a RO (read-only) memory write with `instr_type = True`
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset flash_ctrl_csr_rw flash_ctrl_csr_aliasing flash_ctrl_same_csr_outstanding	Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset flash_ctrl_csr_rw flash_ctrl_csr_aliasing flash_ctrl_same_csr_outstanding	Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	Verify shadowed registers' update error. Randomly pick a shadowed register in the DUT. Write it twice with different values. Verify that the update error alert is triggered and the register value remains unchanged. Verify the update_error status register field is set to 1. Repeat the above steps a bunch of times.
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	Verify reading a shadowed register will clear its staged value. Randomly pick a shadowed register in the DUT. Write it once and read it back to clear the staged value. Then write it twice with the same new value (but different from the previous step). Read it back to verify the new value and ensure that the update error alert did not trigger. Verify the update_error status register field remains the same value. Repeat the above steps a bunch of times.
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	Verify shadowed registers' storage error. Randomly pick a shadowed register in the DUT. Backdoor write to shadowed or committed flops to create a storage fatal alert. Check if fatal alert continuously fires until reset. Verify that all other frontdoor write attempts are blocked during the storage error. Verify that storage_error status register field is set to 1. Reset the DUT. Read all CSRs to ensure the DUT is properly reset. Repeat the above steps a bunch of times.
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	Verify toggle shadowed_rst_n pin can trigger storage error. Randomly drive `shadowed_rst_n` pin to low or `rst_n` pin to low. check if any registers have been written before the reset. If so check if storage error fatal alert is triggered. Check status register. Drive `shadowed_rst_n` pin or `rst_n` pin back to high. If fatal alert is triggered, reset the DUT. Read all CSRs to ensure the DUT is properly reset. Repeat the above steps a bunch of times.
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	Run shadow_reg_update_error sequence in parallel with csr_rw sequence. Randomly select one of the above sequences. Apply csr_rw sequence in parallel but disable the `csr_access_abort` to ensure all shadowed registers' write/read to be executed without aborting. Repeat the above steps a bunch of times.
V2S	tl_intg_err	flash_ctrl_tl_intg_err flash_ctrl_sec_cm	Verify that the data integrity check violation generates an alert. Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert. Inject a fault at the onehot check in `u_reg.u_prim_reg_we_check` and verify the corresponding fatal alert occurs
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	Verify the countermeasure(s) REG.BUS.INTEGRITY. This entry is covered by tl_access_test (hw/dv/tools/dvsim/tests/tl_access_tests.hjson)
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	Verify the countermeasure(s) HOST.BUS.INTEGRITY. This entry is covered by tl_access_test (hw/dv/tools/dvsim/tests/tl_access_tests.hjson)
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg flash_ctrl_wr_intg	Verify the countermeasure(s) MEM.BUS.INTEGRITY. For read path, inject error to tb.dut.u_eflash.gen_flash_cores[*].u_core.u_rd.gen_bufs[0]. u_rd_buf.data_i read data error will trigger fault_status.phy_storage_err and err_code.rd_err. For write path, inject error to tb.dut.u_prog_fifo.wdata_i This will trigger fatal_std_err.prog_intg_err and err_code.prog_err
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	Verify the countermeasure(s) SCRAMBLE.KEY.SIDELOAD. The scrambling key is sideloaded from OTP and thus unreadable by SW. TBD
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_sec_info_access flash_ctrl_disable flash_ctrl_connect flash_ctrl_otp_reset	Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI. Creator info partition can be read, written, erased when lc_creator_seed_sw_rw_en is true. Owner info partition can be read, written, erased when lc_owner_seed_sw_rw_en is true. Isolated info partition can be written whwen lc_iso_part_sw_wr_en is true, and can be read when lc_iso_part_sw_rd_en is true. Run test for each partition and check whether each partition can be accessed only when each lc_ctrl input is valid. If lc_ctrl inputs are invalid, the access to the secret info region will trigger recoverable fatal alert. lc_seed_hw_rd_en is covered by flash_ctrl_otp_reset test. lc_escalate_en_i is covered by flash_ctrl_disable test. See 'flash_ctrl_disable` from the flash_ctrl_testpan.hjson lc_nvm_debug_en_i is covered by flash_ctrl_connect. See 'flash_ctrl_connect' from the flash_ctrl_testplan.hjson
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	Verify the countermeasure(s) CTRL.CONFIG.REGWEN.
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	Verify the countermeasure(s) DATA_REGIONS.CONFIG.REGWEN.
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	Verify the countermeasure(s) DATA_REGIONS.CONFIG.SHADOW.
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	Verify the countermeasure(s) INFO_REGIONS.CONFIG.REGWEN.
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	Verify the countermeasure(s) INFO_REGIONS.CONFIG.SHADOW.
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	Verify the countermeasure(s) BANK.CONFIG.REGWEN.
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	Verify the countermeasure(s) BANK.CONFIG.SHADOW.
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	Verify the countermeasure(s) MEM.CTRL.GLOBAL_ESC. Send a few flash access commands and disable flash access by setting lc_escalate_en to lc_ctrl_pkg::On. Check Ctrl initiated traffic : mp error Host initiated traffic : tlul errors Outstanding traffic: Program or erase will be completed. Read will be dropped. Debug state is changed to 'flash_ctrl_env_pkg::FlashLcDisabled' state
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg flash_ctrl_access_after_disable	Verify the countermeasure(s) MEM.CTRL.LOCAL_ESC. Send a few flash access commands and disable flash access by triggering std_fault. Check Ctrl initiated traffic : mp error Host initiated traffic : tlul errors Outstanding traffic: Program or erase will be completed. Read will be dropped. Debug state is changed to 'flash_ctrl_env_pkg::FlashLcDisabled' state
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	Verify the countermeasure(s) MEM_DISABLE.CONFIG.MUBI.
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	Verify the countermeasure(s) EXEC.CONFIG.REDUN.
V2S	sec_cm_mem_scramble	flash_ctrl_rw	Verify the countermeasure(s) MEM.SCRAMBLE.
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr flash_ctrl_rw_derr flash_ctrl_integrity	Verify the countermeasure(s) MEM.INTEGRITY.
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	Verify the countermeasure(s) RMA_ENTRY.MEM.SEC_WIPE. RMA entry wipes flash memory with random data.
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	Verify the countermeasure(s) CTRL.FSM.SPARSE. Error is injected by global test. Follwing state machines are in this category. tb.dut.u_ctrl_arb.state_q : Error from this state machine will trigger std_fault_status.arb_fsm_err. tb.dut.u_flash_hw_if.state_q, tb.dut.u_flash_hw_if.rma_state_q Error from these state machines will trigger std_fault_status.lcmgr_err.
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	Verify the countermeasure(s) PHY.FSM.SPARSE. Error is injected by global test on tb.dut.u_eflash.gen_flash_cores[*].u_core.state_q. Error from this state machine will trigger std_fault_status.phy_fsm_err.
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	Verify the countermeasure(s) PHY_PROG.FSM.SPARSE. Error is injected by global test on tb.dut.u_eflash.gen_flash_cores[*].u_core.gen_prog_data.u_prog.state_q. Error from this state machine will trigger std_fault_status.phy_fsm_err.
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	Verify the countermeasure(s) CTR.REDUN. Error is injected by global test. Follwing counters are in this category. tb.dut.u_flash_hw_if.seed_cnt_q tb.dut.u_flash_hw_if.addr_cnt_q tb.dut.u_flash_hw_if.page_cnt tb.dut.u_flash_hw_if.word_cnt tb.dut.u_flash_hw_if.rma_wipe_idx Error from these counters will trigger std_fault_status.lcmgr_err.
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	Verify the countermeasure(s) PHY_ARBITER.CTRL.REDUN. The phy arbiter for controller and host is redundant. The arbiter has two instance underneath that are constantly compared to each other. tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].u_req_buf.out_o[1:0] tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].u_req_buf.out_o[1:0] Make output of both mismatch and check fault_status.arb_err is triggered.
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	Verify the countermeasure(s) PHY_HOST_GRANT.CTRL.CONSISTENCY. A host transaction was granted to the muxed partition, this is illegal. @ tb.dut.u_eflash.gen_flash_cores[0].u_core.host_gnt, force tb.dut.u_eflash.gen_flash_cores[0].u_core.muxed_part = 1 and check fault_status.host_gnt_err.
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	Verify the countermeasure(s) PHY_ACK.CTRL.CONSISTENCY. Trigger tb.dut.u_eflash.gen_flash_cores[0].u_core.spurious_ack_o as follows: @ tb.dut.u_eflash.gen_flash_cores[0].u_core.ctrl_fsm_idle force tb.dut.u_eflash.gen_flash_cores[0].u_core.ctrl_rsp_vld = 1 or @ tb.dut.u_eflash.gen_flash_cores[0].u_core.host_outstanding[1:0] == 0 force tb.dut.u_eflash.gen_flash_cores[0].u_core.host_req_done_o = 1 Check fault_status.spurious_ack
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	Verify the countermeasure(s) FIFO.CTR.REDUN. Error is injected by global test. Follwing fifos are in this category. dut.u_to_rd_fifo, dut.u_eflash.gen_flash_cores[].u_core.u_rd.u_rsp_order_fifo, dut.u_eflash.gen_flash_cores[].u_core.u_rd.u_rd_storage Error from these fifos will trigger std_fault_status.fifo_err.
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse		Verify the countermeasure(s) MEM_TL_LC_GATE.FSM.SPARSE.
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse		Verify the countermeasure(s) PROG_TL_LC_GATE.FSM.SPARSE.
V3	asymmetric_read_path	flash_ctrl_rd_ooo	Create 'fast' and 'slow' read path using scramble enable. Send flash read requst over slow path followed by fast path. While return data comes from fast path first but they are expected to be returned in request order.
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset	This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

Name	Description
control_cg	Covers that all operations READ/PROGRAM/ERASE/UNKNOWN have been tested. Covers that ERASE operation is performed on a page and on entire bank. Covers data and info partitions selection. All valid combinations of the above will also be crossed.
erase_susp_cg	Covers if request of erase suspension occured.
eviction_cg	Covers eviction with mp_region_cfgs for data and info regions. Sample all 4 rd_buf status. When each buffer hazard is set, capture the address stored in the buffer. Then search from tb data base to see which region the address belong to. After that record the config value (scrambe_en and ecc_en) of the region. Use cross over buffer index, the operation to cause the eviction and the region config values.
fetch_code_cg	Covers whether dut received valid or invalid key value from ral.exec register. Cross with tlul.instr_types.
msgfifo_level_cg	Covers that all possible fifo statuses generate interrupts for operations READ/PROGRAM. Covers both boundary values 0 and 31. Also covers acceptable distributions within ranges.
rd_buff_evict_cg	Covers that all possible combinations for following sequences of operations READ/PROGRAM/READ and READ/ERASE/READ are executed. Software Interface can perform all three operations READ/PROGRAM/ERASE while Host Interface can perform direct READ.
regwen_val_when_new_value_written_cg	Cover each lockable reg field with these 2 cases: When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that. When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that. This is only applicable if the block contains regwen and locakable CSRs.
rma_init_cg	Cover rma operation is executed regardless of when flash_init started. flash_ctrl_hw_rma runs rma operation and flash init in parallel thread. In this test, sample rma state when flash init starts. If rma state is StRmaIdle, which means rma is not started. So it confirms rma start after flash init start. If rma state is [StRmaPageSel:StRmaInvalid], which mean rma is on going. So it confirms rma start before flash init start.
shadow_field_errs_cg	Cover all shadow register errors for each register field. For all register fields within the shadowed register, this coverpoint covers the following errors: Update error Storage error
sw_error_cg	Covers following error scenarios given in Flash error code register: op_err: Undefined operation. mp_err: Flash access has encountered an access permission error. rd_err: Flash read has an uncorrectable data error. prog_err: Flash program has an error. prog_win_err: Flash program has a window resolution error. prog_type_err: Flash program selected unavailable type. update_err: A shadow register encountered an update error.
tl_errors_cg	Cover the following error cases on TL-UL bus: TL-UL protocol error cases. OpenTitan defined error cases, refer to testpoint `tl_d_illegal_access`.
tl_intg_err_cg	Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.