Registers

The register description below matches the instance in the Earl Grey top level design.

Similar register descriptions can be generated with different parameterizations.

Summary

NameOffsetLengthDescription
pinmux.ALERT_TEST0x04Alert Test Register
pinmux.MIO_PERIPH_INSEL_REGWEN_00x44Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_10x84Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_20xc4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_30x104Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_40x144Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_50x184Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_60x1c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_70x204Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_80x244Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_90x284Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_100x2c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_110x304Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_120x344Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_130x384Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_140x3c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_150x404Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_160x444Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_170x484Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_180x4c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_190x504Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_200x544Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_210x584Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_220x5c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_230x604Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_240x644Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_250x684Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_260x6c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_270x704Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_280x744Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_290x784Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_300x7c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_310x804Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_320x844Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_330x884Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_340x8c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_350x904Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_360x944Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_370x984Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_380x9c4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_390xa04Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_400xa44Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_410xa84Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_420xac4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_430xb04Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_440xb44Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_450xb84Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_460xbc4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_470xc04Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_480xc44Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_490xc84Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_500xcc4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_510xd04Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_520xd44Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_530xd84Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_540xdc4Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_550xe04Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_560xe44Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_00xe84For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_10xec4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_20xf04For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_30xf44For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_40xf84For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_50xfc4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_60x1004For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_70x1044For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_80x1084For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_90x10c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_100x1104For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_110x1144For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_120x1184For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_130x11c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_140x1204For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_150x1244For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_160x1284For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_170x12c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_180x1304For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_190x1344For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_200x1384For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_210x13c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_220x1404For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_230x1444For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_240x1484For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_250x14c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_260x1504For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_270x1544For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_280x1584For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_290x15c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_300x1604For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_310x1644For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_320x1684For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_330x16c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_340x1704For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_350x1744For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_360x1784For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_370x17c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_380x1804For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_390x1844For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_400x1884For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_410x18c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_420x1904For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_430x1944For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_440x1984For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_450x19c4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_460x1a04For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_470x1a44For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_480x1a84For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_490x1ac4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_500x1b04For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_510x1b44For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_520x1b84For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_530x1bc4For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_540x1c04For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_550x1c44For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_560x1c84For each peripheral input, this selects the muxable pad input.
pinmux.MIO_OUTSEL_REGWEN_00x1cc4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_10x1d04Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_20x1d44Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_30x1d84Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_40x1dc4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_50x1e04Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_60x1e44Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_70x1e84Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_80x1ec4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_90x1f04Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_100x1f44Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_110x1f84Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_120x1fc4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_130x2004Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_140x2044Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_150x2084Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_160x20c4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_170x2104Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_180x2144Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_190x2184Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_200x21c4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_210x2204Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_220x2244Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_230x2284Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_240x22c4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_250x2304Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_260x2344Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_270x2384Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_280x23c4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_290x2404Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_300x2444Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_310x2484Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_320x24c4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_330x2504Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_340x2544Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_350x2584Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_360x25c4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_370x2604Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_380x2644Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_390x2684Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_400x26c4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_410x2704Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_420x2744Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_430x2784Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_440x27c4Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_450x2804Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_460x2844Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_00x2884For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_10x28c4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_20x2904For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_30x2944For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_40x2984For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_50x29c4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_60x2a04For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_70x2a44For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_80x2a84For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_90x2ac4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_100x2b04For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_110x2b44For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_120x2b84For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_130x2bc4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_140x2c04For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_150x2c44For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_160x2c84For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_170x2cc4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_180x2d04For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_190x2d44For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_200x2d84For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_210x2dc4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_220x2e04For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_230x2e44For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_240x2e84For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_250x2ec4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_260x2f04For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_270x2f44For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_280x2f84For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_290x2fc4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_300x3004For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_310x3044For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_320x3084For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_330x30c4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_340x3104For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_350x3144For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_360x3184For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_370x31c4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_380x3204For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_390x3244For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_400x3284For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_410x32c4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_420x3304For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_430x3344For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_440x3384For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_450x33c4For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_460x3404For each muxable pad, this selects the peripheral output.
pinmux.MIO_PAD_ATTR_REGWEN_00x3444Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_10x3484Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_20x34c4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_30x3504Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_40x3544Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_50x3584Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_60x35c4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_70x3604Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_80x3644Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_90x3684Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_100x36c4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_110x3704Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_120x3744Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_130x3784Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_140x37c4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_150x3804Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_160x3844Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_170x3884Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_180x38c4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_190x3904Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_200x3944Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_210x3984Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_220x39c4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_230x3a04Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_240x3a44Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_250x3a84Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_260x3ac4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_270x3b04Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_280x3b44Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_290x3b84Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_300x3bc4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_310x3c04Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_320x3c44Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_330x3c84Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_340x3cc4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_350x3d04Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_360x3d44Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_370x3d84Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_380x3dc4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_390x3e04Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_400x3e44Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_410x3e84Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_420x3ec4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_430x3f04Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_440x3f44Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_450x3f84Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_460x3fc4Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_00x4004Muxed pad attributes.
pinmux.MIO_PAD_ATTR_10x4044Muxed pad attributes.
pinmux.MIO_PAD_ATTR_20x4084Muxed pad attributes.
pinmux.MIO_PAD_ATTR_30x40c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_40x4104Muxed pad attributes.
pinmux.MIO_PAD_ATTR_50x4144Muxed pad attributes.
pinmux.MIO_PAD_ATTR_60x4184Muxed pad attributes.
pinmux.MIO_PAD_ATTR_70x41c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_80x4204Muxed pad attributes.
pinmux.MIO_PAD_ATTR_90x4244Muxed pad attributes.
pinmux.MIO_PAD_ATTR_100x4284Muxed pad attributes.
pinmux.MIO_PAD_ATTR_110x42c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_120x4304Muxed pad attributes.
pinmux.MIO_PAD_ATTR_130x4344Muxed pad attributes.
pinmux.MIO_PAD_ATTR_140x4384Muxed pad attributes.
pinmux.MIO_PAD_ATTR_150x43c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_160x4404Muxed pad attributes.
pinmux.MIO_PAD_ATTR_170x4444Muxed pad attributes.
pinmux.MIO_PAD_ATTR_180x4484Muxed pad attributes.
pinmux.MIO_PAD_ATTR_190x44c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_200x4504Muxed pad attributes.
pinmux.MIO_PAD_ATTR_210x4544Muxed pad attributes.
pinmux.MIO_PAD_ATTR_220x4584Muxed pad attributes.
pinmux.MIO_PAD_ATTR_230x45c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_240x4604Muxed pad attributes.
pinmux.MIO_PAD_ATTR_250x4644Muxed pad attributes.
pinmux.MIO_PAD_ATTR_260x4684Muxed pad attributes.
pinmux.MIO_PAD_ATTR_270x46c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_280x4704Muxed pad attributes.
pinmux.MIO_PAD_ATTR_290x4744Muxed pad attributes.
pinmux.MIO_PAD_ATTR_300x4784Muxed pad attributes.
pinmux.MIO_PAD_ATTR_310x47c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_320x4804Muxed pad attributes.
pinmux.MIO_PAD_ATTR_330x4844Muxed pad attributes.
pinmux.MIO_PAD_ATTR_340x4884Muxed pad attributes.
pinmux.MIO_PAD_ATTR_350x48c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_360x4904Muxed pad attributes.
pinmux.MIO_PAD_ATTR_370x4944Muxed pad attributes.
pinmux.MIO_PAD_ATTR_380x4984Muxed pad attributes.
pinmux.MIO_PAD_ATTR_390x49c4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_400x4a04Muxed pad attributes.
pinmux.MIO_PAD_ATTR_410x4a44Muxed pad attributes.
pinmux.MIO_PAD_ATTR_420x4a84Muxed pad attributes.
pinmux.MIO_PAD_ATTR_430x4ac4Muxed pad attributes.
pinmux.MIO_PAD_ATTR_440x4b04Muxed pad attributes.
pinmux.MIO_PAD_ATTR_450x4b44Muxed pad attributes.
pinmux.MIO_PAD_ATTR_460x4b84Muxed pad attributes.
pinmux.DIO_PAD_ATTR_REGWEN_00x4bc4Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_10x4c04Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_20x4c44Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_30x4c84Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_40x4cc4Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_50x4d04Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_60x4d44Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_70x4d84Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_80x4dc4Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_90x4e04Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_100x4e44Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_110x4e84Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_120x4ec4Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_130x4f04Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_140x4f44Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_150x4f84Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_00x4fc4Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_10x5004Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_20x5044Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_30x5084Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_40x50c4Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_50x5104Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_60x5144Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_70x5184Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_80x51c4Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_90x5204Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_100x5244Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_110x5284Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_120x52c4Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_130x5304Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_140x5344Dedicated pad attributes.
pinmux.DIO_PAD_ATTR_150x5384Dedicated pad attributes.
pinmux.MIO_PAD_SLEEP_STATUS_00x53c4Register indicating whether the corresponding pad is in sleep mode.
pinmux.MIO_PAD_SLEEP_STATUS_10x5404Register indicating whether the corresponding pad is in sleep mode.
pinmux.MIO_PAD_SLEEP_REGWEN_00x5444Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_10x5484Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_20x54c4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_30x5504Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_40x5544Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_50x5584Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_60x55c4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_70x5604Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_80x5644Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_90x5684Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_100x56c4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_110x5704Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_120x5744Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_130x5784Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_140x57c4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_150x5804Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_160x5844Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_170x5884Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_180x58c4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_190x5904Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_200x5944Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_210x5984Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_220x59c4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_230x5a04Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_240x5a44Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_250x5a84Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_260x5ac4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_270x5b04Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_280x5b44Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_290x5b84Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_300x5bc4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_310x5c04Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_320x5c44Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_330x5c84Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_340x5cc4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_350x5d04Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_360x5d44Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_370x5d84Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_380x5dc4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_390x5e04Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_400x5e44Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_410x5e84Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_420x5ec4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_430x5f04Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_440x5f44Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_450x5f84Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_460x5fc4Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_EN_00x6004Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_10x6044Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_20x6084Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_30x60c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_40x6104Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_50x6144Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_60x6184Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_70x61c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_80x6204Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_90x6244Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_100x6284Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_110x62c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_120x6304Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_130x6344Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_140x6384Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_150x63c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_160x6404Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_170x6444Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_180x6484Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_190x64c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_200x6504Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_210x6544Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_220x6584Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_230x65c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_240x6604Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_250x6644Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_260x6684Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_270x66c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_280x6704Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_290x6744Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_300x6784Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_310x67c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_320x6804Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_330x6844Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_340x6884Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_350x68c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_360x6904Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_370x6944Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_380x6984Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_390x69c4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_400x6a04Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_410x6a44Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_420x6a84Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_430x6ac4Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_440x6b04Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_450x6b44Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_460x6b84Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_00x6bc4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_10x6c04Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_20x6c44Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_30x6c84Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_40x6cc4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_50x6d04Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_60x6d44Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_70x6d84Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_80x6dc4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_90x6e04Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_100x6e44Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_110x6e84Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_120x6ec4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_130x6f04Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_140x6f44Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_150x6f84Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_160x6fc4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_170x7004Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_180x7044Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_190x7084Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_200x70c4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_210x7104Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_220x7144Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_230x7184Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_240x71c4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_250x7204Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_260x7244Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_270x7284Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_280x72c4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_290x7304Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_300x7344Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_310x7384Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_320x73c4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_330x7404Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_340x7444Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_350x7484Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_360x74c4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_370x7504Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_380x7544Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_390x7584Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_400x75c4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_410x7604Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_420x7644Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_430x7684Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_440x76c4Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_450x7704Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_460x7744Defines sleep behavior of the corresponding muxed pad.
pinmux.DIO_PAD_SLEEP_STATUS0x7784Register indicating whether the corresponding pad is in sleep mode.
pinmux.DIO_PAD_SLEEP_REGWEN_00x77c4Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_10x7804Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_20x7844Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_30x7884Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_40x78c4Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_50x7904Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_60x7944Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_70x7984Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_80x79c4Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_90x7a04Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_100x7a44Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_110x7a84Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_120x7ac4Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_130x7b04Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_140x7b44Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_150x7b84Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_EN_00x7bc4Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_10x7c04Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_20x7c44Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_30x7c84Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_40x7cc4Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_50x7d04Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_60x7d44Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_70x7d84Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_80x7dc4Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_90x7e04Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_100x7e44Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_110x7e84Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_120x7ec4Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_130x7f04Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_140x7f44Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_150x7f84Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_00x7fc4Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_10x8004Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_20x8044Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_30x8084Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_40x80c4Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_50x8104Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_60x8144Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_70x8184Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_80x81c4Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_90x8204Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_100x8244Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_110x8284Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_120x82c4Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_130x8304Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_140x8344Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_150x8384Defines sleep behavior of the corresponding dedicated pad.
pinmux.WKUP_DETECTOR_REGWEN_00x83c4Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_10x8404Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_20x8444Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_30x8484Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_40x84c4Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_50x8504Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_60x8544Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_70x8584Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_EN_00x85c4Enables for the wakeup detectors.
pinmux.WKUP_DETECTOR_EN_10x8604Enables for the wakeup detectors.
pinmux.WKUP_DETECTOR_EN_20x8644Enables for the wakeup detectors.
pinmux.WKUP_DETECTOR_EN_30x8684Enables for the wakeup detectors.
pinmux.WKUP_DETECTOR_EN_40x86c4Enables for the wakeup detectors.
pinmux.WKUP_DETECTOR_EN_50x8704Enables for the wakeup detectors.
pinmux.WKUP_DETECTOR_EN_60x8744Enables for the wakeup detectors.
pinmux.WKUP_DETECTOR_EN_70x8784Enables for the wakeup detectors.
pinmux.WKUP_DETECTOR_00x87c4Configuration of wakeup condition detectors.
pinmux.WKUP_DETECTOR_10x8804Configuration of wakeup condition detectors.
pinmux.WKUP_DETECTOR_20x8844Configuration of wakeup condition detectors.
pinmux.WKUP_DETECTOR_30x8884Configuration of wakeup condition detectors.
pinmux.WKUP_DETECTOR_40x88c4Configuration of wakeup condition detectors.
pinmux.WKUP_DETECTOR_50x8904Configuration of wakeup condition detectors.
pinmux.WKUP_DETECTOR_60x8944Configuration of wakeup condition detectors.
pinmux.WKUP_DETECTOR_70x8984Configuration of wakeup condition detectors.
pinmux.WKUP_DETECTOR_CNT_TH_00x89c4Counter thresholds for wakeup condition detectors.
pinmux.WKUP_DETECTOR_CNT_TH_10x8a04Counter thresholds for wakeup condition detectors.
pinmux.WKUP_DETECTOR_CNT_TH_20x8a44Counter thresholds for wakeup condition detectors.
pinmux.WKUP_DETECTOR_CNT_TH_30x8a84Counter thresholds for wakeup condition detectors.
pinmux.WKUP_DETECTOR_CNT_TH_40x8ac4Counter thresholds for wakeup condition detectors.
pinmux.WKUP_DETECTOR_CNT_TH_50x8b04Counter thresholds for wakeup condition detectors.
pinmux.WKUP_DETECTOR_CNT_TH_60x8b44Counter thresholds for wakeup condition detectors.
pinmux.WKUP_DETECTOR_CNT_TH_70x8b84Counter thresholds for wakeup condition detectors.
pinmux.WKUP_DETECTOR_PADSEL_00x8bc4Pad selects for pad wakeup condition detectors.
pinmux.WKUP_DETECTOR_PADSEL_10x8c04Pad selects for pad wakeup condition detectors.
pinmux.WKUP_DETECTOR_PADSEL_20x8c44Pad selects for pad wakeup condition detectors.
pinmux.WKUP_DETECTOR_PADSEL_30x8c84Pad selects for pad wakeup condition detectors.
pinmux.WKUP_DETECTOR_PADSEL_40x8cc4Pad selects for pad wakeup condition detectors.
pinmux.WKUP_DETECTOR_PADSEL_50x8d04Pad selects for pad wakeup condition detectors.
pinmux.WKUP_DETECTOR_PADSEL_60x8d44Pad selects for pad wakeup condition detectors.
pinmux.WKUP_DETECTOR_PADSEL_70x8d84Pad selects for pad wakeup condition detectors.
pinmux.WKUP_CAUSE0x8dc4Cause registers for wakeup detectors.

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

MIO_PERIPH_INSEL_REGWEN

Register write enable for MIO peripheral input selects.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
MIO_PERIPH_INSEL_REGWEN_00x4
MIO_PERIPH_INSEL_REGWEN_10x8
MIO_PERIPH_INSEL_REGWEN_20xc
MIO_PERIPH_INSEL_REGWEN_30x10
MIO_PERIPH_INSEL_REGWEN_40x14
MIO_PERIPH_INSEL_REGWEN_50x18
MIO_PERIPH_INSEL_REGWEN_60x1c
MIO_PERIPH_INSEL_REGWEN_70x20
MIO_PERIPH_INSEL_REGWEN_80x24
MIO_PERIPH_INSEL_REGWEN_90x28
MIO_PERIPH_INSEL_REGWEN_100x2c
MIO_PERIPH_INSEL_REGWEN_110x30
MIO_PERIPH_INSEL_REGWEN_120x34
MIO_PERIPH_INSEL_REGWEN_130x38
MIO_PERIPH_INSEL_REGWEN_140x3c
MIO_PERIPH_INSEL_REGWEN_150x40
MIO_PERIPH_INSEL_REGWEN_160x44
MIO_PERIPH_INSEL_REGWEN_170x48
MIO_PERIPH_INSEL_REGWEN_180x4c
MIO_PERIPH_INSEL_REGWEN_190x50
MIO_PERIPH_INSEL_REGWEN_200x54
MIO_PERIPH_INSEL_REGWEN_210x58
MIO_PERIPH_INSEL_REGWEN_220x5c
MIO_PERIPH_INSEL_REGWEN_230x60
MIO_PERIPH_INSEL_REGWEN_240x64
MIO_PERIPH_INSEL_REGWEN_250x68
MIO_PERIPH_INSEL_REGWEN_260x6c
MIO_PERIPH_INSEL_REGWEN_270x70
MIO_PERIPH_INSEL_REGWEN_280x74
MIO_PERIPH_INSEL_REGWEN_290x78
MIO_PERIPH_INSEL_REGWEN_300x7c
MIO_PERIPH_INSEL_REGWEN_310x80
MIO_PERIPH_INSEL_REGWEN_320x84
MIO_PERIPH_INSEL_REGWEN_330x88
MIO_PERIPH_INSEL_REGWEN_340x8c
MIO_PERIPH_INSEL_REGWEN_350x90
MIO_PERIPH_INSEL_REGWEN_360x94
MIO_PERIPH_INSEL_REGWEN_370x98
MIO_PERIPH_INSEL_REGWEN_380x9c
MIO_PERIPH_INSEL_REGWEN_390xa0
MIO_PERIPH_INSEL_REGWEN_400xa4
MIO_PERIPH_INSEL_REGWEN_410xa8
MIO_PERIPH_INSEL_REGWEN_420xac
MIO_PERIPH_INSEL_REGWEN_430xb0
MIO_PERIPH_INSEL_REGWEN_440xb4
MIO_PERIPH_INSEL_REGWEN_450xb8
MIO_PERIPH_INSEL_REGWEN_460xbc
MIO_PERIPH_INSEL_REGWEN_470xc0
MIO_PERIPH_INSEL_REGWEN_480xc4
MIO_PERIPH_INSEL_REGWEN_490xc8
MIO_PERIPH_INSEL_REGWEN_500xcc
MIO_PERIPH_INSEL_REGWEN_510xd0
MIO_PERIPH_INSEL_REGWEN_520xd4
MIO_PERIPH_INSEL_REGWEN_530xd8
MIO_PERIPH_INSEL_REGWEN_540xdc
MIO_PERIPH_INSEL_REGWEN_550xe0
MIO_PERIPH_INSEL_REGWEN_560xe4

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENRegister write enable bit. If this is cleared to 0, the corresponding MIO_PERIPH_INSEL is not writable anymore.

MIO_PERIPH_INSEL

For each peripheral input, this selects the muxable pad input.

  • Reset default: 0x0
  • Reset mask: 0x3f

Instances

NameOffset
MIO_PERIPH_INSEL_00xe8
MIO_PERIPH_INSEL_10xec
MIO_PERIPH_INSEL_20xf0
MIO_PERIPH_INSEL_30xf4
MIO_PERIPH_INSEL_40xf8
MIO_PERIPH_INSEL_50xfc
MIO_PERIPH_INSEL_60x100
MIO_PERIPH_INSEL_70x104
MIO_PERIPH_INSEL_80x108
MIO_PERIPH_INSEL_90x10c
MIO_PERIPH_INSEL_100x110
MIO_PERIPH_INSEL_110x114
MIO_PERIPH_INSEL_120x118
MIO_PERIPH_INSEL_130x11c
MIO_PERIPH_INSEL_140x120
MIO_PERIPH_INSEL_150x124
MIO_PERIPH_INSEL_160x128
MIO_PERIPH_INSEL_170x12c
MIO_PERIPH_INSEL_180x130
MIO_PERIPH_INSEL_190x134
MIO_PERIPH_INSEL_200x138
MIO_PERIPH_INSEL_210x13c
MIO_PERIPH_INSEL_220x140
MIO_PERIPH_INSEL_230x144
MIO_PERIPH_INSEL_240x148
MIO_PERIPH_INSEL_250x14c
MIO_PERIPH_INSEL_260x150
MIO_PERIPH_INSEL_270x154
MIO_PERIPH_INSEL_280x158
MIO_PERIPH_INSEL_290x15c
MIO_PERIPH_INSEL_300x160
MIO_PERIPH_INSEL_310x164
MIO_PERIPH_INSEL_320x168
MIO_PERIPH_INSEL_330x16c
MIO_PERIPH_INSEL_340x170
MIO_PERIPH_INSEL_350x174
MIO_PERIPH_INSEL_360x178
MIO_PERIPH_INSEL_370x17c
MIO_PERIPH_INSEL_380x180
MIO_PERIPH_INSEL_390x184
MIO_PERIPH_INSEL_400x188
MIO_PERIPH_INSEL_410x18c
MIO_PERIPH_INSEL_420x190
MIO_PERIPH_INSEL_430x194
MIO_PERIPH_INSEL_440x198
MIO_PERIPH_INSEL_450x19c
MIO_PERIPH_INSEL_460x1a0
MIO_PERIPH_INSEL_470x1a4
MIO_PERIPH_INSEL_480x1a8
MIO_PERIPH_INSEL_490x1ac
MIO_PERIPH_INSEL_500x1b0
MIO_PERIPH_INSEL_510x1b4
MIO_PERIPH_INSEL_520x1b8
MIO_PERIPH_INSEL_530x1bc
MIO_PERIPH_INSEL_540x1c0
MIO_PERIPH_INSEL_550x1c4
MIO_PERIPH_INSEL_560x1c8

Fields

{"reg": [{"name": "IN", "bits": 6, "attr": ["rw"], "rotate": 0}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:6Reserved
5:0rw0x0IN0: tie constantly to zero, 1: tie constantly to 1, >=2: MIO pads (i.e., add 2 to the native MIO pad index).

MIO_OUTSEL_REGWEN

Register write enable for MIO output selects.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
MIO_OUTSEL_REGWEN_00x1cc
MIO_OUTSEL_REGWEN_10x1d0
MIO_OUTSEL_REGWEN_20x1d4
MIO_OUTSEL_REGWEN_30x1d8
MIO_OUTSEL_REGWEN_40x1dc
MIO_OUTSEL_REGWEN_50x1e0
MIO_OUTSEL_REGWEN_60x1e4
MIO_OUTSEL_REGWEN_70x1e8
MIO_OUTSEL_REGWEN_80x1ec
MIO_OUTSEL_REGWEN_90x1f0
MIO_OUTSEL_REGWEN_100x1f4
MIO_OUTSEL_REGWEN_110x1f8
MIO_OUTSEL_REGWEN_120x1fc
MIO_OUTSEL_REGWEN_130x200
MIO_OUTSEL_REGWEN_140x204
MIO_OUTSEL_REGWEN_150x208
MIO_OUTSEL_REGWEN_160x20c
MIO_OUTSEL_REGWEN_170x210
MIO_OUTSEL_REGWEN_180x214
MIO_OUTSEL_REGWEN_190x218
MIO_OUTSEL_REGWEN_200x21c
MIO_OUTSEL_REGWEN_210x220
MIO_OUTSEL_REGWEN_220x224
MIO_OUTSEL_REGWEN_230x228
MIO_OUTSEL_REGWEN_240x22c
MIO_OUTSEL_REGWEN_250x230
MIO_OUTSEL_REGWEN_260x234
MIO_OUTSEL_REGWEN_270x238
MIO_OUTSEL_REGWEN_280x23c
MIO_OUTSEL_REGWEN_290x240
MIO_OUTSEL_REGWEN_300x244
MIO_OUTSEL_REGWEN_310x248
MIO_OUTSEL_REGWEN_320x24c
MIO_OUTSEL_REGWEN_330x250
MIO_OUTSEL_REGWEN_340x254
MIO_OUTSEL_REGWEN_350x258
MIO_OUTSEL_REGWEN_360x25c
MIO_OUTSEL_REGWEN_370x260
MIO_OUTSEL_REGWEN_380x264
MIO_OUTSEL_REGWEN_390x268
MIO_OUTSEL_REGWEN_400x26c
MIO_OUTSEL_REGWEN_410x270
MIO_OUTSEL_REGWEN_420x274
MIO_OUTSEL_REGWEN_430x278
MIO_OUTSEL_REGWEN_440x27c
MIO_OUTSEL_REGWEN_450x280
MIO_OUTSEL_REGWEN_460x284

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENRegister write enable bit. If this is cleared to 0, the corresponding MIO_OUTSEL is not writable anymore.

MIO_OUTSEL

For each muxable pad, this selects the peripheral output.

  • Reset default: 0x2
  • Reset mask: 0x7f

Instances

NameOffset
MIO_OUTSEL_00x288
MIO_OUTSEL_10x28c
MIO_OUTSEL_20x290
MIO_OUTSEL_30x294
MIO_OUTSEL_40x298
MIO_OUTSEL_50x29c
MIO_OUTSEL_60x2a0
MIO_OUTSEL_70x2a4
MIO_OUTSEL_80x2a8
MIO_OUTSEL_90x2ac
MIO_OUTSEL_100x2b0
MIO_OUTSEL_110x2b4
MIO_OUTSEL_120x2b8
MIO_OUTSEL_130x2bc
MIO_OUTSEL_140x2c0
MIO_OUTSEL_150x2c4
MIO_OUTSEL_160x2c8
MIO_OUTSEL_170x2cc
MIO_OUTSEL_180x2d0
MIO_OUTSEL_190x2d4
MIO_OUTSEL_200x2d8
MIO_OUTSEL_210x2dc
MIO_OUTSEL_220x2e0
MIO_OUTSEL_230x2e4
MIO_OUTSEL_240x2e8
MIO_OUTSEL_250x2ec
MIO_OUTSEL_260x2f0
MIO_OUTSEL_270x2f4
MIO_OUTSEL_280x2f8
MIO_OUTSEL_290x2fc
MIO_OUTSEL_300x300
MIO_OUTSEL_310x304
MIO_OUTSEL_320x308
MIO_OUTSEL_330x30c
MIO_OUTSEL_340x310
MIO_OUTSEL_350x314
MIO_OUTSEL_360x318
MIO_OUTSEL_370x31c
MIO_OUTSEL_380x320
MIO_OUTSEL_390x324
MIO_OUTSEL_400x328
MIO_OUTSEL_410x32c
MIO_OUTSEL_420x330
MIO_OUTSEL_430x334
MIO_OUTSEL_440x338
MIO_OUTSEL_450x33c
MIO_OUTSEL_460x340

Fields

{"reg": [{"name": "OUT", "bits": 7, "attr": ["rw"], "rotate": 0}, {"bits": 25}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:7Reserved
6:0rw0x2OUT0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z, >=3: peripheral outputs (i.e., add 3 to the native peripheral pad index).

MIO_PAD_ATTR_REGWEN

Register write enable for MIO PAD attributes.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
MIO_PAD_ATTR_REGWEN_00x344
MIO_PAD_ATTR_REGWEN_10x348
MIO_PAD_ATTR_REGWEN_20x34c
MIO_PAD_ATTR_REGWEN_30x350
MIO_PAD_ATTR_REGWEN_40x354
MIO_PAD_ATTR_REGWEN_50x358
MIO_PAD_ATTR_REGWEN_60x35c
MIO_PAD_ATTR_REGWEN_70x360
MIO_PAD_ATTR_REGWEN_80x364
MIO_PAD_ATTR_REGWEN_90x368
MIO_PAD_ATTR_REGWEN_100x36c
MIO_PAD_ATTR_REGWEN_110x370
MIO_PAD_ATTR_REGWEN_120x374
MIO_PAD_ATTR_REGWEN_130x378
MIO_PAD_ATTR_REGWEN_140x37c
MIO_PAD_ATTR_REGWEN_150x380
MIO_PAD_ATTR_REGWEN_160x384
MIO_PAD_ATTR_REGWEN_170x388
MIO_PAD_ATTR_REGWEN_180x38c
MIO_PAD_ATTR_REGWEN_190x390
MIO_PAD_ATTR_REGWEN_200x394
MIO_PAD_ATTR_REGWEN_210x398
MIO_PAD_ATTR_REGWEN_220x39c
MIO_PAD_ATTR_REGWEN_230x3a0
MIO_PAD_ATTR_REGWEN_240x3a4
MIO_PAD_ATTR_REGWEN_250x3a8
MIO_PAD_ATTR_REGWEN_260x3ac
MIO_PAD_ATTR_REGWEN_270x3b0
MIO_PAD_ATTR_REGWEN_280x3b4
MIO_PAD_ATTR_REGWEN_290x3b8
MIO_PAD_ATTR_REGWEN_300x3bc
MIO_PAD_ATTR_REGWEN_310x3c0
MIO_PAD_ATTR_REGWEN_320x3c4
MIO_PAD_ATTR_REGWEN_330x3c8
MIO_PAD_ATTR_REGWEN_340x3cc
MIO_PAD_ATTR_REGWEN_350x3d0
MIO_PAD_ATTR_REGWEN_360x3d4
MIO_PAD_ATTR_REGWEN_370x3d8
MIO_PAD_ATTR_REGWEN_380x3dc
MIO_PAD_ATTR_REGWEN_390x3e0
MIO_PAD_ATTR_REGWEN_400x3e4
MIO_PAD_ATTR_REGWEN_410x3e8
MIO_PAD_ATTR_REGWEN_420x3ec
MIO_PAD_ATTR_REGWEN_430x3f0
MIO_PAD_ATTR_REGWEN_440x3f4
MIO_PAD_ATTR_REGWEN_450x3f8
MIO_PAD_ATTR_REGWEN_460x3fc

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENRegister write enable bit. If this is cleared to 0, the corresponding MIO_PAD_ATTR is not writable anymore.

MIO_PAD_ATTR

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes. The muxed pad that is used for TAP strap 0 has a different reset value, with pull_en set to 1.

  • Reset default: 0x0
  • Reset mask: 0xf300ff

Instances

NameOffset
MIO_PAD_ATTR_00x400
MIO_PAD_ATTR_10x404
MIO_PAD_ATTR_20x408
MIO_PAD_ATTR_30x40c
MIO_PAD_ATTR_40x410
MIO_PAD_ATTR_50x414
MIO_PAD_ATTR_60x418
MIO_PAD_ATTR_70x41c
MIO_PAD_ATTR_80x420
MIO_PAD_ATTR_90x424
MIO_PAD_ATTR_100x428
MIO_PAD_ATTR_110x42c
MIO_PAD_ATTR_120x430
MIO_PAD_ATTR_130x434
MIO_PAD_ATTR_140x438
MIO_PAD_ATTR_150x43c
MIO_PAD_ATTR_160x440
MIO_PAD_ATTR_170x444
MIO_PAD_ATTR_180x448
MIO_PAD_ATTR_190x44c
MIO_PAD_ATTR_200x450
MIO_PAD_ATTR_210x454
MIO_PAD_ATTR_220x458
MIO_PAD_ATTR_230x45c
MIO_PAD_ATTR_240x460
MIO_PAD_ATTR_250x464
MIO_PAD_ATTR_260x468
MIO_PAD_ATTR_270x46c
MIO_PAD_ATTR_280x470
MIO_PAD_ATTR_290x474
MIO_PAD_ATTR_300x478
MIO_PAD_ATTR_310x47c
MIO_PAD_ATTR_320x480
MIO_PAD_ATTR_330x484
MIO_PAD_ATTR_340x488
MIO_PAD_ATTR_350x48c
MIO_PAD_ATTR_360x490
MIO_PAD_ATTR_370x494
MIO_PAD_ATTR_380x498
MIO_PAD_ATTR_390x49c
MIO_PAD_ATTR_400x4a0
MIO_PAD_ATTR_410x4a4
MIO_PAD_ATTR_420x4a8
MIO_PAD_ATTR_430x4ac
MIO_PAD_ATTR_440x4b0
MIO_PAD_ATTR_450x4b4
MIO_PAD_ATTR_460x4b8

Fields

{"reg": [{"name": "invert", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "virtual_od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_select", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "keeper_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "schmitt_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "input_disable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 8}, {"name": "slew_rate", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "drive_strength", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
BitsTypeResetName
31:24Reserved
23:20rw0x0drive_strength
19:18Reserved
17:16rw0x0slew_rate
15:8Reserved
7rw0x0input_disable
6rw0x0od_en
5rw0x0schmitt_en
4rw0x0keeper_en
3rw0x0pull_select
2rw0x0pull_en
1rw0x0virtual_od_en
0rw0x0invert

MIO_PAD_ATTR . drive_strength

Drive strength (0x0: weakest, 0xf: strongest)

MIO_PAD_ATTR . slew_rate

Slew rate (0x0: slowest, 0x3: fastest).

MIO_PAD_ATTR . input_disable

Disable input drivers. Setting this to 1 for pads that are not used as input can reduce their leakage current.

MIO_PAD_ATTR . od_en

Enable open drain.

MIO_PAD_ATTR . schmitt_en

Enable the schmitt trigger.

MIO_PAD_ATTR . keeper_en

Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog trireg.

MIO_PAD_ATTR . pull_select

Pull select (0: pull-down, 1: pull-up).

ValueNameDescription
0x0pull_downSelect the pull-down resistor.
0x1pull_upSelect the pull-up resistor.

MIO_PAD_ATTR . pull_en

Enable pull-up or pull-down resistor.

MIO_PAD_ATTR . virtual_od_en

Enable virtual open drain.

MIO_PAD_ATTR . invert

Invert input and output levels.

DIO_PAD_ATTR_REGWEN

Register write enable for DIO PAD attributes.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
DIO_PAD_ATTR_REGWEN_00x4bc
DIO_PAD_ATTR_REGWEN_10x4c0
DIO_PAD_ATTR_REGWEN_20x4c4
DIO_PAD_ATTR_REGWEN_30x4c8
DIO_PAD_ATTR_REGWEN_40x4cc
DIO_PAD_ATTR_REGWEN_50x4d0
DIO_PAD_ATTR_REGWEN_60x4d4
DIO_PAD_ATTR_REGWEN_70x4d8
DIO_PAD_ATTR_REGWEN_80x4dc
DIO_PAD_ATTR_REGWEN_90x4e0
DIO_PAD_ATTR_REGWEN_100x4e4
DIO_PAD_ATTR_REGWEN_110x4e8
DIO_PAD_ATTR_REGWEN_120x4ec
DIO_PAD_ATTR_REGWEN_130x4f0
DIO_PAD_ATTR_REGWEN_140x4f4
DIO_PAD_ATTR_REGWEN_150x4f8

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENRegister write enable bit. If this is cleared to 0, the corresponding DIO_PAD_ATTR is not writable anymore.

DIO_PAD_ATTR

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

  • Reset default: 0x0
  • Reset mask: 0xf300ff

Instances

NameOffset
DIO_PAD_ATTR_00x4fc
DIO_PAD_ATTR_10x500
DIO_PAD_ATTR_20x504
DIO_PAD_ATTR_30x508
DIO_PAD_ATTR_40x50c
DIO_PAD_ATTR_50x510
DIO_PAD_ATTR_60x514
DIO_PAD_ATTR_70x518
DIO_PAD_ATTR_80x51c
DIO_PAD_ATTR_90x520
DIO_PAD_ATTR_100x524
DIO_PAD_ATTR_110x528
DIO_PAD_ATTR_120x52c
DIO_PAD_ATTR_130x530
DIO_PAD_ATTR_140x534
DIO_PAD_ATTR_150x538

Fields

{"reg": [{"name": "invert", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "virtual_od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "pull_select", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "keeper_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "schmitt_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "od_en", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "input_disable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 8}, {"name": "slew_rate", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 2}, {"name": "drive_strength", "bits": 4, "attr": ["rw"], "rotate": -90}, {"bits": 8}], "config": {"lanes": 1, "fontsize": 10, "vspace": 160}}
BitsTypeResetName
31:24Reserved
23:20rw0x0drive_strength
19:18Reserved
17:16rw0x0slew_rate
15:8Reserved
7rw0x0input_disable
6rw0x0od_en
5rw0x0schmitt_en
4rw0x0keeper_en
3rw0x0pull_select
2rw0x0pull_en
1rw0x0virtual_od_en
0rw0x0invert

DIO_PAD_ATTR . drive_strength

Drive strength (0x0: weakest, 0xf: strongest)

DIO_PAD_ATTR . slew_rate

Slew rate (0x0: slowest, 0x3: fastest).

DIO_PAD_ATTR . input_disable

Disable input drivers. Setting this to 1 for pads that are not used as input can reduce their leakage current.

DIO_PAD_ATTR . od_en

Enable open drain.

DIO_PAD_ATTR . schmitt_en

Enable the schmitt trigger.

DIO_PAD_ATTR . keeper_en

Enable keeper termination. This weakly drives the previous pad output value when output is disabled, similar to a verilog trireg.

DIO_PAD_ATTR . pull_select

Pull select (0: pull-down, 1: pull-up).

ValueNameDescription
0x0pull_downSelect the pull-down resistor.
0x1pull_upSelect the pull-up resistor.

DIO_PAD_ATTR . pull_en

Enable pull-up or pull-down resistor.

DIO_PAD_ATTR . virtual_od_en

Enable virtual open drain.

DIO_PAD_ATTR . invert

Invert input and output levels.

MIO_PAD_SLEEP_STATUS_0

Register indicating whether the corresponding pad is in sleep mode.

  • Offset: 0x53c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_8", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_9", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_10", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_11", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_12", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_13", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_14", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_15", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_16", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_17", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_18", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_19", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_20", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_21", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_22", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_23", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_24", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_25", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_26", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_27", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_28", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_29", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_30", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_31", "bits": 1, "attr": ["rw0c"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31rw0c0x0EN_31This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
30rw0c0x0EN_30This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
29rw0c0x0EN_29This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
28rw0c0x0EN_28This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
27rw0c0x0EN_27This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
26rw0c0x0EN_26This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
25rw0c0x0EN_25This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
24rw0c0x0EN_24This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
23rw0c0x0EN_23This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
22rw0c0x0EN_22This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
21rw0c0x0EN_21This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
20rw0c0x0EN_20This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
19rw0c0x0EN_19This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
18rw0c0x0EN_18This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
17rw0c0x0EN_17This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
16rw0c0x0EN_16This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
15rw0c0x0EN_15This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
14rw0c0x0EN_14This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
13rw0c0x0EN_13This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
12rw0c0x0EN_12This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
11rw0c0x0EN_11This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
10rw0c0x0EN_10This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
9rw0c0x0EN_9This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
8rw0c0x0EN_8This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
7rw0c0x0EN_7This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
6rw0c0x0EN_6This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
5rw0c0x0EN_5This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
4rw0c0x0EN_4This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
3rw0c0x0EN_3This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
2rw0c0x0EN_2This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
1rw0c0x0EN_1This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
0rw0c0x0EN_0This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

MIO_PAD_SLEEP_STATUS_1

Register indicating whether the corresponding pad is in sleep mode.

  • Offset: 0x540
  • Reset default: 0x0
  • Reset mask: 0x7fff

Fields

{"reg": [{"name": "EN_32", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_33", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_34", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_35", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_36", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_37", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_38", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_39", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_40", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_41", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_42", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_43", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_44", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_45", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_46", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 17}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:15Reserved
14rw0c0x0EN_46For MIO_PAD1
13rw0c0x0EN_45For MIO_PAD1
12rw0c0x0EN_44For MIO_PAD1
11rw0c0x0EN_43For MIO_PAD1
10rw0c0x0EN_42For MIO_PAD1
9rw0c0x0EN_41For MIO_PAD1
8rw0c0x0EN_40For MIO_PAD1
7rw0c0x0EN_39For MIO_PAD1
6rw0c0x0EN_38For MIO_PAD1
5rw0c0x0EN_37For MIO_PAD1
4rw0c0x0EN_36For MIO_PAD1
3rw0c0x0EN_35For MIO_PAD1
2rw0c0x0EN_34For MIO_PAD1
1rw0c0x0EN_33For MIO_PAD1
0rw0c0x0EN_32For MIO_PAD1

MIO_PAD_SLEEP_REGWEN

Register write enable for MIO sleep value configuration.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
MIO_PAD_SLEEP_REGWEN_00x544
MIO_PAD_SLEEP_REGWEN_10x548
MIO_PAD_SLEEP_REGWEN_20x54c
MIO_PAD_SLEEP_REGWEN_30x550
MIO_PAD_SLEEP_REGWEN_40x554
MIO_PAD_SLEEP_REGWEN_50x558
MIO_PAD_SLEEP_REGWEN_60x55c
MIO_PAD_SLEEP_REGWEN_70x560
MIO_PAD_SLEEP_REGWEN_80x564
MIO_PAD_SLEEP_REGWEN_90x568
MIO_PAD_SLEEP_REGWEN_100x56c
MIO_PAD_SLEEP_REGWEN_110x570
MIO_PAD_SLEEP_REGWEN_120x574
MIO_PAD_SLEEP_REGWEN_130x578
MIO_PAD_SLEEP_REGWEN_140x57c
MIO_PAD_SLEEP_REGWEN_150x580
MIO_PAD_SLEEP_REGWEN_160x584
MIO_PAD_SLEEP_REGWEN_170x588
MIO_PAD_SLEEP_REGWEN_180x58c
MIO_PAD_SLEEP_REGWEN_190x590
MIO_PAD_SLEEP_REGWEN_200x594
MIO_PAD_SLEEP_REGWEN_210x598
MIO_PAD_SLEEP_REGWEN_220x59c
MIO_PAD_SLEEP_REGWEN_230x5a0
MIO_PAD_SLEEP_REGWEN_240x5a4
MIO_PAD_SLEEP_REGWEN_250x5a8
MIO_PAD_SLEEP_REGWEN_260x5ac
MIO_PAD_SLEEP_REGWEN_270x5b0
MIO_PAD_SLEEP_REGWEN_280x5b4
MIO_PAD_SLEEP_REGWEN_290x5b8
MIO_PAD_SLEEP_REGWEN_300x5bc
MIO_PAD_SLEEP_REGWEN_310x5c0
MIO_PAD_SLEEP_REGWEN_320x5c4
MIO_PAD_SLEEP_REGWEN_330x5c8
MIO_PAD_SLEEP_REGWEN_340x5cc
MIO_PAD_SLEEP_REGWEN_350x5d0
MIO_PAD_SLEEP_REGWEN_360x5d4
MIO_PAD_SLEEP_REGWEN_370x5d8
MIO_PAD_SLEEP_REGWEN_380x5dc
MIO_PAD_SLEEP_REGWEN_390x5e0
MIO_PAD_SLEEP_REGWEN_400x5e4
MIO_PAD_SLEEP_REGWEN_410x5e8
MIO_PAD_SLEEP_REGWEN_420x5ec
MIO_PAD_SLEEP_REGWEN_430x5f0
MIO_PAD_SLEEP_REGWEN_440x5f4
MIO_PAD_SLEEP_REGWEN_450x5f8
MIO_PAD_SLEEP_REGWEN_460x5fc

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENRegister write enable bit. If this is cleared to 0, the corresponding MIO_PAD_SLEEP_MODE is not writable anymore.

MIO_PAD_SLEEP_EN

Enables the sleep mode of the corresponding muxed pad.

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
MIO_PAD_SLEEP_EN_00x600
MIO_PAD_SLEEP_EN_10x604
MIO_PAD_SLEEP_EN_20x608
MIO_PAD_SLEEP_EN_30x60c
MIO_PAD_SLEEP_EN_40x610
MIO_PAD_SLEEP_EN_50x614
MIO_PAD_SLEEP_EN_60x618
MIO_PAD_SLEEP_EN_70x61c
MIO_PAD_SLEEP_EN_80x620
MIO_PAD_SLEEP_EN_90x624
MIO_PAD_SLEEP_EN_100x628
MIO_PAD_SLEEP_EN_110x62c
MIO_PAD_SLEEP_EN_120x630
MIO_PAD_SLEEP_EN_130x634
MIO_PAD_SLEEP_EN_140x638
MIO_PAD_SLEEP_EN_150x63c
MIO_PAD_SLEEP_EN_160x640
MIO_PAD_SLEEP_EN_170x644
MIO_PAD_SLEEP_EN_180x648
MIO_PAD_SLEEP_EN_190x64c
MIO_PAD_SLEEP_EN_200x650
MIO_PAD_SLEEP_EN_210x654
MIO_PAD_SLEEP_EN_220x658
MIO_PAD_SLEEP_EN_230x65c
MIO_PAD_SLEEP_EN_240x660
MIO_PAD_SLEEP_EN_250x664
MIO_PAD_SLEEP_EN_260x668
MIO_PAD_SLEEP_EN_270x66c
MIO_PAD_SLEEP_EN_280x670
MIO_PAD_SLEEP_EN_290x674
MIO_PAD_SLEEP_EN_300x678
MIO_PAD_SLEEP_EN_310x67c
MIO_PAD_SLEEP_EN_320x680
MIO_PAD_SLEEP_EN_330x684
MIO_PAD_SLEEP_EN_340x688
MIO_PAD_SLEEP_EN_350x68c
MIO_PAD_SLEEP_EN_360x690
MIO_PAD_SLEEP_EN_370x694
MIO_PAD_SLEEP_EN_380x698
MIO_PAD_SLEEP_EN_390x69c
MIO_PAD_SLEEP_EN_400x6a0
MIO_PAD_SLEEP_EN_410x6a4
MIO_PAD_SLEEP_EN_420x6a8
MIO_PAD_SLEEP_EN_430x6ac
MIO_PAD_SLEEP_EN_440x6b0
MIO_PAD_SLEEP_EN_450x6b4
MIO_PAD_SLEEP_EN_460x6b8

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:1Reserved
0rw0x0EN

MIO_PAD_SLEEP_EN . EN

Deep sleep mode enable. If this bit is set to 1 the corresponding pad will enable the sleep behavior specified in MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit in MIO_PAD_SLEEP_STATUS will be set to 1. The pad remains in deep sleep mode until the corresponding bit in MIO_PAD_SLEEP_STATUS is cleared by SW. Note that if an always on peripheral is connected to a specific MIO pad, the corresponding MIO_PAD_SLEEP_EN bit should be set to 0.

MIO_PAD_SLEEP_MODE

Defines sleep behavior of the corresponding muxed pad.

  • Reset default: 0x2
  • Reset mask: 0x3

Instances

NameOffset
MIO_PAD_SLEEP_MODE_00x6bc
MIO_PAD_SLEEP_MODE_10x6c0
MIO_PAD_SLEEP_MODE_20x6c4
MIO_PAD_SLEEP_MODE_30x6c8
MIO_PAD_SLEEP_MODE_40x6cc
MIO_PAD_SLEEP_MODE_50x6d0
MIO_PAD_SLEEP_MODE_60x6d4
MIO_PAD_SLEEP_MODE_70x6d8
MIO_PAD_SLEEP_MODE_80x6dc
MIO_PAD_SLEEP_MODE_90x6e0
MIO_PAD_SLEEP_MODE_100x6e4
MIO_PAD_SLEEP_MODE_110x6e8
MIO_PAD_SLEEP_MODE_120x6ec
MIO_PAD_SLEEP_MODE_130x6f0
MIO_PAD_SLEEP_MODE_140x6f4
MIO_PAD_SLEEP_MODE_150x6f8
MIO_PAD_SLEEP_MODE_160x6fc
MIO_PAD_SLEEP_MODE_170x700
MIO_PAD_SLEEP_MODE_180x704
MIO_PAD_SLEEP_MODE_190x708
MIO_PAD_SLEEP_MODE_200x70c
MIO_PAD_SLEEP_MODE_210x710
MIO_PAD_SLEEP_MODE_220x714
MIO_PAD_SLEEP_MODE_230x718
MIO_PAD_SLEEP_MODE_240x71c
MIO_PAD_SLEEP_MODE_250x720
MIO_PAD_SLEEP_MODE_260x724
MIO_PAD_SLEEP_MODE_270x728
MIO_PAD_SLEEP_MODE_280x72c
MIO_PAD_SLEEP_MODE_290x730
MIO_PAD_SLEEP_MODE_300x734
MIO_PAD_SLEEP_MODE_310x738
MIO_PAD_SLEEP_MODE_320x73c
MIO_PAD_SLEEP_MODE_330x740
MIO_PAD_SLEEP_MODE_340x744
MIO_PAD_SLEEP_MODE_350x748
MIO_PAD_SLEEP_MODE_360x74c
MIO_PAD_SLEEP_MODE_370x750
MIO_PAD_SLEEP_MODE_380x754
MIO_PAD_SLEEP_MODE_390x758
MIO_PAD_SLEEP_MODE_400x75c
MIO_PAD_SLEEP_MODE_410x760
MIO_PAD_SLEEP_MODE_420x764
MIO_PAD_SLEEP_MODE_430x768
MIO_PAD_SLEEP_MODE_440x76c
MIO_PAD_SLEEP_MODE_450x770
MIO_PAD_SLEEP_MODE_460x774

Fields

{"reg": [{"name": "OUT", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:2Reserved
1:0rw0x2OUT

MIO_PAD_SLEEP_MODE . OUT

Value to drive in deep sleep.

ValueNameDescription
0x0Tie-LowThe pad is driven actively to zero in deep sleep mode.
0x1Tie-HighThe pad is driven actively to one in deep sleep mode.
0x2High-ZThe pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in !!MIO_PAD_ATTR.
0x3KeepKeep last driven value (including high-Z).

DIO_PAD_SLEEP_STATUS

Register indicating whether the corresponding pad is in sleep mode.

  • Offset: 0x778
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_8", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_9", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_10", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_11", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_12", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_13", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_14", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "EN_15", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 16}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:16Reserved
15rw0c0x0EN_15This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
14rw0c0x0EN_14This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
13rw0c0x0EN_13This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
12rw0c0x0EN_12This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
11rw0c0x0EN_11This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
10rw0c0x0EN_10This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
9rw0c0x0EN_9This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
8rw0c0x0EN_8This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
7rw0c0x0EN_7This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
6rw0c0x0EN_6This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
5rw0c0x0EN_5This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
4rw0c0x0EN_4This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
3rw0c0x0EN_3This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
2rw0c0x0EN_2This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
1rw0c0x0EN_1This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.
0rw0c0x0EN_0This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (DIO_PAD_SLEEP_MODE) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

DIO_PAD_SLEEP_REGWEN

Register write enable for DIO sleep value configuration.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
DIO_PAD_SLEEP_REGWEN_00x77c
DIO_PAD_SLEEP_REGWEN_10x780
DIO_PAD_SLEEP_REGWEN_20x784
DIO_PAD_SLEEP_REGWEN_30x788
DIO_PAD_SLEEP_REGWEN_40x78c
DIO_PAD_SLEEP_REGWEN_50x790
DIO_PAD_SLEEP_REGWEN_60x794
DIO_PAD_SLEEP_REGWEN_70x798
DIO_PAD_SLEEP_REGWEN_80x79c
DIO_PAD_SLEEP_REGWEN_90x7a0
DIO_PAD_SLEEP_REGWEN_100x7a4
DIO_PAD_SLEEP_REGWEN_110x7a8
DIO_PAD_SLEEP_REGWEN_120x7ac
DIO_PAD_SLEEP_REGWEN_130x7b0
DIO_PAD_SLEEP_REGWEN_140x7b4
DIO_PAD_SLEEP_REGWEN_150x7b8

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENRegister write enable bit. If this is cleared to 0, the corresponding DIO_PAD_SLEEP_MODE is not writable anymore.

DIO_PAD_SLEEP_EN

Enables the sleep mode of the corresponding dedicated pad.

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
DIO_PAD_SLEEP_EN_00x7bc
DIO_PAD_SLEEP_EN_10x7c0
DIO_PAD_SLEEP_EN_20x7c4
DIO_PAD_SLEEP_EN_30x7c8
DIO_PAD_SLEEP_EN_40x7cc
DIO_PAD_SLEEP_EN_50x7d0
DIO_PAD_SLEEP_EN_60x7d4
DIO_PAD_SLEEP_EN_70x7d8
DIO_PAD_SLEEP_EN_80x7dc
DIO_PAD_SLEEP_EN_90x7e0
DIO_PAD_SLEEP_EN_100x7e4
DIO_PAD_SLEEP_EN_110x7e8
DIO_PAD_SLEEP_EN_120x7ec
DIO_PAD_SLEEP_EN_130x7f0
DIO_PAD_SLEEP_EN_140x7f4
DIO_PAD_SLEEP_EN_150x7f8

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:1Reserved
0rw0x0EN

DIO_PAD_SLEEP_EN . EN

Deep sleep mode enable. If this bit is set to 1 the corresponding pad will enable the sleep behavior specified in DIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit in DIO_PAD_SLEEP_STATUS will be set to 1. The pad remains in deep sleep mode until the corresponding bit in DIO_PAD_SLEEP_STATUS is cleared by SW. Note that if an always on peripheral is connected to a specific DIO pad, the corresponding DIO_PAD_SLEEP_EN bit should be set to 0.

DIO_PAD_SLEEP_MODE

Defines sleep behavior of the corresponding dedicated pad.

  • Reset default: 0x2
  • Reset mask: 0x3

Instances

NameOffset
DIO_PAD_SLEEP_MODE_00x7fc
DIO_PAD_SLEEP_MODE_10x800
DIO_PAD_SLEEP_MODE_20x804
DIO_PAD_SLEEP_MODE_30x808
DIO_PAD_SLEEP_MODE_40x80c
DIO_PAD_SLEEP_MODE_50x810
DIO_PAD_SLEEP_MODE_60x814
DIO_PAD_SLEEP_MODE_70x818
DIO_PAD_SLEEP_MODE_80x81c
DIO_PAD_SLEEP_MODE_90x820
DIO_PAD_SLEEP_MODE_100x824
DIO_PAD_SLEEP_MODE_110x828
DIO_PAD_SLEEP_MODE_120x82c
DIO_PAD_SLEEP_MODE_130x830
DIO_PAD_SLEEP_MODE_140x834
DIO_PAD_SLEEP_MODE_150x838

Fields

{"reg": [{"name": "OUT", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:2Reserved
1:0rw0x2OUT

DIO_PAD_SLEEP_MODE . OUT

Value to drive in deep sleep.

ValueNameDescription
0x0Tie-LowThe pad is driven actively to zero in deep sleep mode.
0x1Tie-HighThe pad is driven actively to one in deep sleep mode.
0x2High-ZThe pad is left undriven in deep sleep mode. Note that the actual driving behavior during deep sleep will then depend on the pull-up/-down configuration of in !!DIO_PAD_ATTR.
0x3KeepKeep last driven value (including high-Z).

WKUP_DETECTOR_REGWEN

Register write enable for wakeup detectors.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
WKUP_DETECTOR_REGWEN_00x83c
WKUP_DETECTOR_REGWEN_10x840
WKUP_DETECTOR_REGWEN_20x844
WKUP_DETECTOR_REGWEN_30x848
WKUP_DETECTOR_REGWEN_40x84c
WKUP_DETECTOR_REGWEN_50x850
WKUP_DETECTOR_REGWEN_60x854
WKUP_DETECTOR_REGWEN_70x858

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENRegister write enable bit. If this is cleared to 0, the corresponding WKUP_DETECTOR configuration is not writable anymore.

WKUP_DETECTOR_EN

Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
WKUP_DETECTOR_EN_00x85c
WKUP_DETECTOR_EN_10x860
WKUP_DETECTOR_EN_20x864
WKUP_DETECTOR_EN_30x868
WKUP_DETECTOR_EN_40x86c
WKUP_DETECTOR_EN_50x870
WKUP_DETECTOR_EN_60x874
WKUP_DETECTOR_EN_70x878

Fields

{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0x0ENSetting this bit activates the corresponding wakeup detector. The behavior is as specified in WKUP_DETECTOR, WKUP_DETECTOR_CNT_TH and WKUP_DETECTOR_PADSEL.

WKUP_DETECTOR

Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

Note that the wkup detector should be disabled by setting WKUP_DETECTOR_EN_0 before changing the detection mode. The reason for that is that the pulse width counter is NOT cleared upon a mode change while the detector is enabled.

  • Reset default: 0x0
  • Reset mask: 0x1f

Instances

NameOffset
WKUP_DETECTOR_00x87c
WKUP_DETECTOR_10x880
WKUP_DETECTOR_20x884
WKUP_DETECTOR_30x888
WKUP_DETECTOR_40x88c
WKUP_DETECTOR_50x890
WKUP_DETECTOR_60x894
WKUP_DETECTOR_70x898

Fields

{"reg": [{"name": "MODE", "bits": 3, "attr": ["rw"], "rotate": 0}, {"name": "FILTER", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "MIODIO", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 27}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:5Reserved
4rw0x0MIODIO
3rw0x0FILTER
2:0rw0x0MODE

WKUP_DETECTOR . MIODIO

0: select index WKUP_DETECTOR_PADSEL from MIO pads, 1: select index WKUP_DETECTOR_PADSEL from DIO pads.

WKUP_DETECTOR . FILTER

0: signal filter disabled, 1: signal filter enabled. the signal must be stable for 4 always-on clock cycles before the value is being forwarded. can be used for debouncing.

WKUP_DETECTOR . MODE

Wakeup detection mode. Out of range values default to Posedge.

ValueNameDescription
0x0PosedgeTrigger a wakeup request when observing a positive edge.
0x1NegedgeTrigger a wakeup request when observing a negative edge.
0x2EdgeTrigger a wakeup request when observing an edge in any direction.
0x3TimedHighTrigger a wakeup request when pin is driven HIGH for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.
0x4TimedLowTrigger a wakeup request when pin is driven LOW for a certain amount of always-on clock cycles as configured in !!WKUP_DETECTOR_CNT_TH.

Other values are reserved.

WKUP_DETECTOR_CNT_TH

Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

  • Reset default: 0x0
  • Reset mask: 0xff

Instances

NameOffset
WKUP_DETECTOR_CNT_TH_00x89c
WKUP_DETECTOR_CNT_TH_10x8a0
WKUP_DETECTOR_CNT_TH_20x8a4
WKUP_DETECTOR_CNT_TH_30x8a8
WKUP_DETECTOR_CNT_TH_40x8ac
WKUP_DETECTOR_CNT_TH_50x8b0
WKUP_DETECTOR_CNT_TH_60x8b4
WKUP_DETECTOR_CNT_TH_70x8b8

Fields

{"reg": [{"name": "TH", "bits": 8, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:8Reserved
7:0rw0x0THCounter threshold for TimedLow and TimedHigh wakeup detector modes (see WKUP_DETECTOR). The threshold is in terms of always-on clock cycles.

WKUP_DETECTOR_PADSEL

Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.

  • Reset default: 0x0
  • Reset mask: 0x3f

Instances

NameOffset
WKUP_DETECTOR_PADSEL_00x8bc
WKUP_DETECTOR_PADSEL_10x8c0
WKUP_DETECTOR_PADSEL_20x8c4
WKUP_DETECTOR_PADSEL_30x8c8
WKUP_DETECTOR_PADSEL_40x8cc
WKUP_DETECTOR_PADSEL_50x8d0
WKUP_DETECTOR_PADSEL_60x8d4
WKUP_DETECTOR_PADSEL_70x8d8

Fields

{"reg": [{"name": "SEL", "bits": 6, "attr": ["rw"], "rotate": 0}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:6Reserved
5:0rw0x0SEL

WKUP_DETECTOR_PADSEL . SEL

Selects a specific MIO or DIO pad (depending on WKUP_DETECTOR configuration). In case of MIO, the pad select index is the same as used for MIO_PERIPH_INSEL, meaning that index 0 and 1 just select constants 0 and 1, and the MIO pads live at indices >= 2. In case of DIO pads, the pad select index corresponds 1:1 to the DIO pad to be selected.

WKUP_CAUSE

Cause registers for wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

  • Offset: 0x8dc
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

{"reg": [{"name": "CAUSE_0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_1", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_2", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_3", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_4", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_5", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_6", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"name": "CAUSE_7", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
BitsTypeResetNameDescription
31:8Reserved
7rw0c0x0CAUSE_7Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
6rw0c0x0CAUSE_6Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
5rw0c0x0CAUSE_5Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
4rw0c0x0CAUSE_4Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
3rw0c0x0CAUSE_3Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
2rw0c0x0CAUSE_2Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
1rw0c0x0CAUSE_1Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.
0rw0c0x0CAUSE_0Set to 1 if the corresponding detector has detected a wakeup pattern. Write 0 to clear.