Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module sensor_ctrl has the following hardware interfaces defined

Primary Clock: clk_i
Other Clocks: clk_aon_i
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Security Countermeasures: none

Peripheral Pins for Chip IO

Pin name	Direction	Description
ast_debug_out[8:0]	output	ast debug outputs to pinmux

Inter-Module Signals

Port Name	Package::Struct	Type	Act	Width
ast_alert	ast_pkg::ast_alert	req_rsp	rsp	1
ast_status	ast_pkg::ast_status	uni	rcv	1
ast_init_done	prim_mubi_pkg::mubi4	uni	rcv	1
ast2pinmux	logic	uni	rcv	9
wkup_req	logic	uni	req	1
tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts

Interrupt Name	Type	Description
io_status_change	Event	io power status has changed
init_status_change	Event	ast init status has changed

Security Alerts

Alert Name	Description
recov_alert	recoverable sensor_ctrl alerts
fatal_alert	fatal sensor_ctrl alerts

Registers

Summary

Name	Offset	Length	Description
sensor_ctrl.`INTR_STATE`	0x0	4	Interrupt State Register
sensor_ctrl.`INTR_ENABLE`	0x4	4	Interrupt Enable Register
sensor_ctrl.`INTR_TEST`	0x8	4	Interrupt Test Register
sensor_ctrl.`ALERT_TEST`	0xc	4	Alert Test Register
sensor_ctrl.`CFG_REGWEN`	0x10	4	Controls the configurability of !!FATAL_ALERT_EN register.
sensor_ctrl.`ALERT_TRIG`	0x14	4	Alert trigger test
sensor_ctrl.`FATAL_ALERT_EN`	0x18	4	Each bit marks a corresponding alert as fatal or recoverable.
sensor_ctrl.`RECOV_ALERT`	0x1c	4	Each bit represents a recoverable alert that has been triggered by AST.
sensor_ctrl.`FATAL_ALERT`	0x20	4	Each bit represents a fatal alert that has been triggered by AST.
sensor_ctrl.`STATUS`	0x24	4	Status readback for ast

INTR_STATE

Interrupt State Register

Offset: 0x0
Reset default: 0x0
Reset mask: 0x3

Fields

Bits	Type	Reset	Name	Description
31:2				Reserved
1	rw1c	0x0	init_status_change	ast init status has changed
0	rw1c	0x0	io_status_change	io power status has changed

INTR_ENABLE

Interrupt Enable Register

Offset: 0x4
Reset default: 0x0
Reset mask: 0x3

Fields

Bits	Type	Reset	Name	Description
31:2				Reserved
1	rw	0x0	init_status_change	Enable interrupt when `INTR_STATE.init_status_change` is set.
0	rw	0x0	io_status_change	Enable interrupt when `INTR_STATE.io_status_change` is set.

INTR_TEST

Interrupt Test Register

Offset: 0x8
Reset default: 0x0
Reset mask: 0x3

Fields

Bits	Type	Reset	Name	Description
31:2				Reserved
1	wo	0x0	init_status_change	Write 1 to force `INTR_STATE.init_status_change` to 1.
0	wo	0x0	io_status_change	Write 1 to force `INTR_STATE.io_status_change` to 1.

ALERT_TEST

Alert Test Register

Offset: 0xc
Reset default: 0x0
Reset mask: 0x3

Fields

Bits	Type	Reset	Name	Description
31:2				Reserved
1	wo	0x0	fatal_alert	Write 1 to trigger one alert event of this kind.
0	wo	0x0	recov_alert	Write 1 to trigger one alert event of this kind.

CFG_REGWEN

Controls the configurability of FATAL_ALERT_EN register.

Offset: 0x10
Reset default: 0x1
Reset mask: 0x1

Fields

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw0c	0x1	EN	Configuration enable.

ALERT_TRIG

Alert trigger test

Offset: 0x14
Reset default: 0x0
Reset mask: 0x7ff

Fields

Bits	Type	Reset	Name	Description
31:11				Reserved
10	rw	0x0	VAL_10	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
9	rw	0x0	VAL_9	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
8	rw	0x0	VAL_8	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
7	rw	0x0	VAL_7	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
6	rw	0x0	VAL_6	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
5	rw	0x0	VAL_5	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
4	rw	0x0	VAL_4	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
3	rw	0x0	VAL_3	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
2	rw	0x0	VAL_2	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
1	rw	0x0	VAL_1	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`
0	rw	0x0	VAL_0	Alert trigger for testing 0 No alerts triggered 1 Continuously trigger alert until disabled For bit mapping, please see `ALERT_TEST`

FATAL_ALERT_EN

Each bit marks a corresponding alert as fatal or recoverable.

Offset: 0x18
Reset default: 0x0
Reset mask: 0x7ff
Register enable: CFG_REGWEN

Fields

Bits	Type	Reset	Name	Description
31:11				Reserved
10	rw	0x0	VAL_10	1 - An alert event is fatal. 0 - An alert event is recoverable.
9	rw	0x0	VAL_9	1 - An alert event is fatal. 0 - An alert event is recoverable.
8	rw	0x0	VAL_8	1 - An alert event is fatal. 0 - An alert event is recoverable.
7	rw	0x0	VAL_7	1 - An alert event is fatal. 0 - An alert event is recoverable.
6	rw	0x0	VAL_6	1 - An alert event is fatal. 0 - An alert event is recoverable.
5	rw	0x0	VAL_5	1 - An alert event is fatal. 0 - An alert event is recoverable.
4	rw	0x0	VAL_4	1 - An alert event is fatal. 0 - An alert event is recoverable.
3	rw	0x0	VAL_3	1 - An alert event is fatal. 0 - An alert event is recoverable.
2	rw	0x0	VAL_2	1 - An alert event is fatal. 0 - An alert event is recoverable.
1	rw	0x0	VAL_1	1 - An alert event is fatal. 0 - An alert event is recoverable.
0	rw	0x0	VAL_0	1 - An alert event is fatal. 0 - An alert event is recoverable.

RECOV_ALERT

Each bit represents a recoverable alert that has been triggered by AST. Since these are recoverable alerts, they can be cleared by software.

Offset: 0x1c
Reset default: 0x0
Reset mask: 0x7ff

Fields

Bits	Type	Reset	Name	Description
31:11				Reserved
10	rw1c	0x0	VAL_10	1 - An alert event has been set 0 - No alert event has been set
9	rw1c	0x0	VAL_9	1 - An alert event has been set 0 - No alert event has been set
8	rw1c	0x0	VAL_8	1 - An alert event has been set 0 - No alert event has been set
7	rw1c	0x0	VAL_7	1 - An alert event has been set 0 - No alert event has been set
6	rw1c	0x0	VAL_6	1 - An alert event has been set 0 - No alert event has been set
5	rw1c	0x0	VAL_5	1 - An alert event has been set 0 - No alert event has been set
4	rw1c	0x0	VAL_4	1 - An alert event has been set 0 - No alert event has been set
3	rw1c	0x0	VAL_3	1 - An alert event has been set 0 - No alert event has been set
2	rw1c	0x0	VAL_2	1 - An alert event has been set 0 - No alert event has been set
1	rw1c	0x0	VAL_1	1 - An alert event has been set 0 - No alert event has been set
0	rw1c	0x0	VAL_0	1 - An alert event has been set 0 - No alert event has been set

FATAL_ALERT

Each bit represents a fatal alert that has been triggered by AST. Since these registers represent fatal alerts, they cannot be cleared.

The lower bits are used for ast alert events. The upper bits are used for local events.

Offset: 0x20
Reset default: 0x0
Reset mask: 0xfff

Fields

Bits	Type	Reset	Name	Description
31:12				Reserved
11	ro	0x0	VAL_11	1 - An alert event has been set 0 - No alert event has been set
10	ro	0x0	VAL_10	1 - An alert event has been set 0 - No alert event has been set
9	ro	0x0	VAL_9	1 - An alert event has been set 0 - No alert event has been set
8	ro	0x0	VAL_8	1 - An alert event has been set 0 - No alert event has been set
7	ro	0x0	VAL_7	1 - An alert event has been set 0 - No alert event has been set
6	ro	0x0	VAL_6	1 - An alert event has been set 0 - No alert event has been set
5	ro	0x0	VAL_5	1 - An alert event has been set 0 - No alert event has been set
4	ro	0x0	VAL_4	1 - An alert event has been set 0 - No alert event has been set
3	ro	0x0	VAL_3	1 - An alert event has been set 0 - No alert event has been set
2	ro	0x0	VAL_2	1 - An alert event has been set 0 - No alert event has been set
1	ro	0x0	VAL_1	1 - An alert event has been set 0 - No alert event has been set
0	ro	0x0	VAL_0	1 - An alert event has been set 0 - No alert event has been set

STATUS

Status readback for ast

Offset: 0x24
Reset default: 0x0
Reset mask: 0x7

Fields

Bits	Type	Reset	Name	Description
31:3				Reserved
2:1	ro	0x0	io_pok	IO power is ready
0	ro	0x0	ast_init_done	AST has finished initializing