Testplan

Testpoints

Stage V1 Testpoints

smoke

Test: rstmgr_smoke

Smoke test accessing a major datapath within the rstmgr.

Checks the behavior of rstmgr when receiving various reset requests.

Stimulus:

  • Send a scan reset.
  • Send a low power entry reset.
  • Send a peripheral reset request.
  • Send a debug reset.
  • Configure a software request for peripheral reset.
  • Set alert and cpu dump inputs to random values.

Checks:

  • Checks the reset_info matches expected values.
  • Checks the alert_info CSR correctly captures the input info.
  • Checks the cpu_info CSR correctly captures the input info.
  • Checks the output reset pins corresponding to sw resettable units match sw_rst_ctrl_n CSR.

csr_hw_reset

Test: rstmgr_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_rw

Test: rstmgr_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_bit_bash

Test: rstmgr_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_aliasing

Test: rstmgr_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.

csr_mem_rw_with_rand_reset

Test: rstmgr_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.

regwen_csr_and_corresponding_lockable_csr

Tests:

  • rstmgr_csr_rw
  • rstmgr_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

  • Randomly access all CSRs
  • Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

  • If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
  • If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

Stage V2 Testpoints

reset_stretcher

Test: rstmgr_por_stretcher

Test the POR reset signal must be stable for multiple cycles.

The POR reset signal must remain active for at least 32 consecutive cycles before going inactive for the rest of the reset tree to go inactive.

Stimulus:

  • Activate POR, and de-activate it at a random width less than 32 cycles between de-activations for N de-activations.

Checks:

  • With SVA check the output reset is only set if the input reset has had at least 32 cycles of steady input reset active.

sw_rst

Test: rstmgr_sw_rst

Test the sw_rst functionality.

The sw_rst_regwen and sw_rst_ctrl_n CSRs control the specific reset outputs to peripherals in the following sequence:

  • Test all sw_rst_ctrl_n bits when sw_rst_regwen is all 1’s.
  • Clear each sw_rst_regwen bit to verify the corresponding resets are masked.

Stimulus:

  • Write sw_rst_ctrl_n CSR with random values when regwen is all 1’s.
  • Clear each sw_rst_regwen bit and write sw_rst_ctrl_n CSR with all 0’s.
  • After each regwen bit check set sw_rst_ctrl_n to all 1’s.

Checks:

  • Check that the zero bits in sw_rst_ctrl_n enabled by sw_rst_regwen cause the respective resets to become active.
  • Check that the zero bits in sw_rst_ctrl_n disabled by sw_rst_regwen have no effect on resets.
  • Check the reset_info, cpu_info, and alert_info CSRs are not modified.

sw_rst_reset_race

Test: rstmgr_sw_rst_reset_race

Test sw_rst and reset close in time.

Sends sw_rst and regular resets in close temporal proximity.

Stimulus:

  • Write sw_rst_ctrl_n CSR with random values when regwen is all 1’s.
  • Send a hardware reset.
  • Release resets.

Checks:

  • Check the reset_info CSR.
  • Reset behavior is checked by SVA.

reset_info

Test: rstmgr_reset

Test the reporting of reset reason.

Stimulus:

  • Generate the different resets recorded in reset_info CSR.
  • Randomly clear reset_info (it is rw1c).

Checks:

  • The resulting setting of reset_info is as expected.
  • Each bit was set at least once.
  • Each bit was cleared at least once.

cpu_info

Test: rstmgr_reset

Test the cpu_info recording.

The cpu_info CSR register(s) can capture the contents of the cpu_dump_i input when resets happen and it is enabled.

Stimulus:

  • Regularly modify the cpu_dump_i input.
  • With cpu_regwen on, randomly set cpu_info_ctrl.en to control whether the dump should be captured.
  • Generate reset(s) as in smoke testpoint.

Checks:

  • Verify the cpu_info is only captured when enabled.
  • Verify the cpu_info contents at each cpu_info_ctrl.index matches the expected value.

alert_info

Test: rstmgr_reset

Test the alert_info recording.

The alert_info CSR register(s) can capture the contents of the alert_dump_i input when resets happen and it is enabled.

Stimulus:

  • Regularly modify the alert_dump_i input.
  • With alert_regwen on, randomly set alert_info_ctrl.en to control whether the dump should be captured.
  • Generate reset(s) as in smoke testpoint.

Checks:

  • Verify the alert_info is only captured when enabled.
  • Verify the alert_info contents at each alert_info_ctrl.index matches the expected value.

reset_info_capture

Test: rstmgr_reset

Test the capture blocking effect of rst_cpu_n input.

After an AON reset reset capture is blocked until the input rst_cpu_n goes inactive.

Stimulus:

  • Wait for a random number of resets before setting rst_cpu_n inactive.

Checks:

  • Non-AON resets prior to this event don’t capture.

stress_all

Test: rstmgr_stress_all

This runs random tests sequentially.

Stress with the following sequences:

  • rstmgr_reset_vseq
  • rstmgr_smoke_vseq
  • rstmgr_sw_rst_vseq

alert_test

Test: rstmgr_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.

tl_d_oob_addr_access

Test: rstmgr_tl_errors

Access out of bounds address and verify correctness of response / behavior

tl_d_illegal_access

Test: rstmgr_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn’t support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
    • write with instr_type = True

tl_d_outstanding_access

Tests:

  • rstmgr_csr_hw_reset
  • rstmgr_csr_rw
  • rstmgr_csr_aliasing
  • rstmgr_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

tl_d_partial_access

Tests:

  • rstmgr_csr_hw_reset
  • rstmgr_csr_rw
  • rstmgr_csr_aliasing
  • rstmgr_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

tl_intg_err

Tests:

  • rstmgr_tl_intg_err
  • rstmgr_sec_cm

Verify that the data integrity check violation generates an alert.

  • Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
  • Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

prim_count_check

Test: rstmgr_sec_cm

Verify that violating prim_count counter properties generate a fatal alert.

Stimulus:

  • At the falling edge (non-active edge), force the counter to a different value than expected.
  • Randomly force the counter back to a normal value to ensure the error is latched and won’t go away until reset.
  • Within the next few cycles, the violation of hardened counter property should generate a fatal alert.
  • Repeat for ALL prim_count instances in the DUT.

Checks:

  • Check that fatal alert is triggered.
  • Check that err_code/fault_status is updated correctly and preserved until reset.
  • Verify any operations that follow fail (as applicable).

prim_fsm_check

Test: rstmgr_sec_cm

Verify that entering to an undefined state generates a fatal alert.

Stimulus:

  • Backdoor force the FSM to any of the undefined values.
  • Randomly force the FSM back to a defined state to ensure the error is latched and won’t go away until reset.
  • Within the next few cycles, the FSM landing in an invalid state should trigger a fatal alert.
  • Repeat for ALL prim_fsm instances in the DUT.

Checks:

  • Check that fatal alert is triggered.
  • Check that err_code/fault_status is updated correctly and preserved until reset.
  • Verify any operations that follow fail (as applicable).

sec_cm_bus_integrity

Test: rstmgr_tl_intg_err

Verify the countermeasure(s) BUS.INTEGRITY. This entry is covered by tl_access_test.

sec_cm_scan_intersig_mubi

Test: rstmgr_sec_cm_scan_intersig_mubi

Verify the countermeasure(s) SCAN.INTERSIG.MUBI.

Stimulus: Same as smoke test but drive scanmode_i with a constant invalid value during the test.

Check: If dut accepts any of invalid values, test will fail by turning dut to scanmode.

sec_cm_leaf_rst_bkgn_chk

Test: rstmgr_leaf_rst_cnsty

Verify the countermeasure(s) LEAF.RST.BKGN_CHK.

** Stimulus**: Execute a series of reset event - lowpower, hwreq, and sw reset -. And at the beginning of these events, create reset consistency error to one of 25 leaf modules. (exclude u_daon_por_io_div4 and u_daon_por_io_div4_shadowed, see #11858, #12729 for details) Do the same test for all 25 modules.

Check: Upon asserting each reset consistency error, check alert_fatal_cnsty_fault is asserted.

sec_cm_leaf_rst_shadow

Test: rstmgr_leaf_rst_shadow_attack

Verify the countermeasure(s) LEAF.RST.SHADOW. After power up, create glitch to a shadow leaf reset module. Check if normal leaf reset module is not triggerred. Do over all {shadow, normal} leaf reset module pairs

sec_cm_leaf_fsm_sparse

Test: rstmgr_sec_cm

Verify the countermeasure(s) LEAF.FSM.SPARSE.

Force leaf rst check state to illegal value. This is triggered by common cm primitives

sec_cm_sw_rst_config_regwen

Test: rstmgr_csr_rw

Verify the countermeasure(s) SW_RST.CONFIG.REGWEN.

RSTMGR.SW_RST_CTRL_N. This is covered by auto csr test.

sec_cm_dump_ctrl_config_regwen

Test: rstmgr_csr_rw

Verify the countermeasure(s) DUMP_CTRL.CONFIG.REGWEN.

RSTMGR.ALERT_INFO_CTRL and RSTMGR.CPU_INFO_CTRL This is covered by auto csr test.

Stage V3 Testpoints

stress_all_with_rand_reset

Test: rstmgr_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

alert_info_access_cg

Collects coverage on the reads of alert_info.

This captures alert_info_ctrl.index CSR to verify all fields of alert_info have been read.

alert_info_capture_cg

Collects coverage on reset type and enable when reset occurs.

Uses reset_cp that records the reset encoded as in reset_info CSR, and ctrl_en_cp capturing alert_info_ctrl.en CSR, and creates the per-reset_cp bit cross.

cpu_info_access_cg

Collects coverage on the reads of cpu_info.

This captures cpu_info_ctrl.index CSR to verify all fields of cpu_info have been read.

cpu_info_capture_cg

Collects coverage on the reset and enable when reset occurs.

Uses reset_cp that records the reset encoded as in reset_info CSR, and ctrl_en_cp capturing cpu_info_ctrl.en CSR, and creates the per-reset_cp bit cross.

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

  • When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
  • When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

reset_stretcher_cg

Collects coverage on the reset_stretcher functionality.

The stretcher counter is reset when por_n_i is not stable. Collect both the count at the point of instability, and the number of times the counter was reset.

sw_rst_cg

Collects coverage on the software reset functionality.

Each bit of the pair sw_rst_regwen and sw_rst_ctrl_n CSRs independently control if the corresponding output reset is activated. This collects one coverpoint for each, and their cross.

tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.