Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | rstmgr_smoke | Smoke test accessing a major datapath within the rstmgr. Checks the behavior of rstmgr when receiving various reset requests. Stimulus:
Checks:
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V1 | csr_hw_reset | rstmgr_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | rstmgr_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | rstmgr_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | rstmgr_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | rstmgr_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | rstmgr_csr_rw rstmgr_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | reset_stretcher | rstmgr_por_stretcher | Test the POR reset signal must be stable for multiple cycles. The POR reset signal must remain active for at least 32 consecutive cycles before going inactive for the rest of the reset tree to go inactive. Stimulus:
Checks:
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V2 | sw_rst | rstmgr_sw_rst | Test the sw_rst functionality. The
Stimulus:
Checks:
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V2 | sw_rst_reset_race | rstmgr_sw_rst_reset_race | Test sw_rst and reset close in time. Sends sw_rst and regular resets in close temporal proximity. Stimulus:
Checks:
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V2 | reset_info | rstmgr_reset | Test the reporting of reset reason. Stimulus:
Checks:
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V2 | cpu_info | rstmgr_reset | Test the cpu_info recording. The Stimulus:
Checks:
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V2 | alert_info | rstmgr_reset | Test the alert_info recording. The Stimulus:
Checks:
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V2 | reset_info_capture | rstmgr_reset | Test the capture blocking effect of rst_cpu_n input. After an AON reset reset capture is blocked until the input rst_cpu_n goes inactive. Stimulus:
Checks:
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V2 | stress_all | rstmgr_stress_all | This runs random tests sequentially. Stress with the following sequences:
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V2 | alert_test | rstmgr_alert_test | Verify common
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V2 | tl_d_oob_addr_access | rstmgr_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | rstmgr_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | rstmgr_csr_hw_reset rstmgr_csr_rw rstmgr_csr_aliasing rstmgr_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | rstmgr_csr_hw_reset rstmgr_csr_rw rstmgr_csr_aliasing rstmgr_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | rstmgr_tl_intg_err rstmgr_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | prim_count_check | rstmgr_sec_cm | Verify that violating prim_count counter properties generate a fatal alert. Stimulus:
Checks:
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V2S | prim_fsm_check | rstmgr_sec_cm | Verify that entering to an undefined state generates a fatal alert. Stimulus:
Checks:
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V2S | sec_cm_bus_integrity | rstmgr_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. This entry is covered by tl_access_test. |
V2S | sec_cm_scan_intersig_mubi | rstmgr_sec_cm_scan_intersig_mubi | Verify the countermeasure(s) SCAN.INTERSIG.MUBI. Stimulus: Same as smoke test but drive scanmode_i with a constant invalid value during the test. Check: If dut accepts any of invalid values, test will fail by turning dut to scanmode. |
V2S | sec_cm_leaf_rst_bkgn_chk | rstmgr_leaf_rst_cnsty | Verify the countermeasure(s) LEAF.RST.BKGN_CHK. ** Stimulus**: Execute a series of reset event - lowpower, hwreq, and sw reset -. And at the beginning of these events, create reset consistency error to one of 25 leaf modules. (exclude u_daon_por_io_div4 and u_daon_por_io_div4_shadowed, see #11858, #12729 for details) Do the same test for all 25 modules. Check: Upon asserting each reset consistency error, check alert_fatal_cnsty_fault is asserted. |
V2S | sec_cm_leaf_rst_shadow | rstmgr_leaf_rst_shadow_attack | Verify the countermeasure(s) LEAF.RST.SHADOW. After power up, create glitch to a shadow leaf reset module. Check if normal leaf reset module is not triggerred. Do over all {shadow, normal} leaf reset module pairs |
V2S | sec_cm_leaf_fsm_sparse | rstmgr_sec_cm | Verify the countermeasure(s) LEAF.FSM.SPARSE. Force leaf rst check state to illegal value. This is triggered by common cm primitives |
V2S | sec_cm_sw_rst_config_regwen | rstmgr_csr_rw | Verify the countermeasure(s) SW_RST.CONFIG.REGWEN. RSTMGR.SW_RST_CTRL_N. This is covered by auto csr test. |
V2S | sec_cm_dump_ctrl_config_regwen | rstmgr_csr_rw | Verify the countermeasure(s) DUMP_CTRL.CONFIG.REGWEN. RSTMGR.ALERT_INFO_CTRL and RSTMGR.CPU_INFO_CTRL This is covered by auto csr test. |
V3 | stress_all_with_rand_reset | rstmgr_stress_all_with_rand_reset | This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers. |
Covergroups
Name | Description |
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alert_info_access_cg | Collects coverage on the reads of alert_info. This captures |
alert_info_capture_cg | Collects coverage on reset type and enable when reset occurs. Uses |
cpu_info_access_cg | Collects coverage on the reads of cpu_info. This captures |
cpu_info_capture_cg | Collects coverage on the reset and enable when reset occurs. Uses |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
reset_stretcher_cg | Collects coverage on the reset_stretcher functionality. The stretcher counter is reset when por_n_i is not stable. Collect both the count at the point of instability, and the number of times the counter was reset. |
sw_rst_cg | Collects coverage on the software reset functionality. Each bit of the pair |
tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |