Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pwm has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: clk_core_i
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Interrupts: none

Peripheral Pins for Chip IO

Pin nameDirectionDescription
pwm[5:0]outputPulse output. Note that though this output is always enabled, there is a formal set of enable pins (pwm_en_o) which are required for top-level integration of comportable IPs.

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure IDDescription
PWM.BUS.INTEGRITYEnd-to-end bus integrity scheme.