Referring to the Comportable guideline for peripheral device functionality, the module pwm has the following hardware interfaces defined
- Primary Clock:
clk_i
- Other Clocks:
clk_core_i
- Bus Device Interfaces (TL-UL):
tl
- Bus Host Interfaces (TL-UL): none
- Interrupts: none
| Pin name | Direction | Description |
|---|
| pwm[5:0] | output | Pulse output. Note that though this output is always enabled, there is a formal set of enable pins (pwm_en_o) which are required for top-level integration of comportable IPs. |
| Port Name | Package::Struct | Type | Act | Width | Description |
|---|
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Alert Name | Description |
|---|
| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
| Countermeasure ID | Description |
|---|
| PWM.BUS.INTEGRITY | End-to-end bus integrity scheme. |