Registers

Summary

NameOffsetLengthDescription
pwm.ALERT_TEST0x04Alert Test Register
pwm.REGWEN0x44Register write enable for all control registers
pwm.CFG0x84Configuration register
pwm.PWM_EN0xc4Enable PWM operation for each channel
pwm.INVERT0x104Invert the PWM output for each channel
pwm.PWM_PARAM_00x144Basic PWM Channel Parameters
pwm.PWM_PARAM_10x184Basic PWM Channel Parameters
pwm.PWM_PARAM_20x1c4Basic PWM Channel Parameters
pwm.PWM_PARAM_30x204Basic PWM Channel Parameters
pwm.PWM_PARAM_40x244Basic PWM Channel Parameters
pwm.PWM_PARAM_50x284Basic PWM Channel Parameters
pwm.DUTY_CYCLE_00x2c4Controls the duty_cycle of each channel.
pwm.DUTY_CYCLE_10x304Controls the duty_cycle of each channel.
pwm.DUTY_CYCLE_20x344Controls the duty_cycle of each channel.
pwm.DUTY_CYCLE_30x384Controls the duty_cycle of each channel.
pwm.DUTY_CYCLE_40x3c4Controls the duty_cycle of each channel.
pwm.DUTY_CYCLE_50x404Controls the duty_cycle of each channel.
pwm.BLINK_PARAM_00x444Hardware controlled blink/heartbeat parameters.
pwm.BLINK_PARAM_10x484Hardware controlled blink/heartbeat parameters.
pwm.BLINK_PARAM_20x4c4Hardware controlled blink/heartbeat parameters.
pwm.BLINK_PARAM_30x504Hardware controlled blink/heartbeat parameters.
pwm.BLINK_PARAM_40x544Hardware controlled blink/heartbeat parameters.
pwm.BLINK_PARAM_50x584Hardware controlled blink/heartbeat parameters.

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

{"reg": [{"name": "fatal_fault", "bits": 1, "attr": ["wo"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 130}}
BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

REGWEN

Register write enable for all control registers

  • Offset: 0x4
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

{"reg": [{"name": "REGWEN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1REGWENWhen true, all writable registers can be modified. When false, they become read-only. Defaults true, write zero to clear. This can be cleared after initial configuration at boot in order to lock in the listed register settings.

CFG

Configuration register

  • Offset: 0x8
  • Reset default: 0x38008000
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

{"reg": [{"name": "CLK_DIV", "bits": 27, "attr": ["rw"], "rotate": 0}, {"name": "DC_RESN", "bits": 4, "attr": ["rw"], "rotate": -90}, {"name": "CNTR_EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}}
BitsTypeResetName
31rw0x0CNTR_EN
30:27rw0x7DC_RESN
26:0rw0x8000CLK_DIV

CFG . CNTR_EN

Assert this bit to enable the PWM phase counter. Clearing this bit disables and resets the phase counter.

CFG . DC_RESN

Phase Resolution (logarithmic). All duty-cycle and phase shift registers represent fractional PWM cycles, expressed in units of 2^16 PWM cycles. Each PWM cycle is divided into 2^(DC_RESN+1) time slices, and thus only the (DC_RESN+1) most significant bits of each phase or duty cycle register are relevant.

CFG . CLK_DIV

Sets the period of each PWM beat to be (CLK_DIV+1) input clock periods. Since PWM pulses are generated once every 2^(DC_RESN+1) beats, the period between output pulses is 2^(DC_RESN+1)*(CLK_DIV+1) times longer than the input clock period.

PWM_EN

Enable PWM operation for each channel

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x3f
  • Register enable: REGWEN

Fields

{"reg": [{"name": "EN_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "EN_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetNameDescription
31:6Reserved
5rw0x0EN_5Write 1 to this bit to enable PWM pulses on the corresponding channel.
4rw0x0EN_4Write 1 to this bit to enable PWM pulses on the corresponding channel.
3rw0x0EN_3Write 1 to this bit to enable PWM pulses on the corresponding channel.
2rw0x0EN_2Write 1 to this bit to enable PWM pulses on the corresponding channel.
1rw0x0EN_1Write 1 to this bit to enable PWM pulses on the corresponding channel.
0rw0x0EN_0Write 1 to this bit to enable PWM pulses on the corresponding channel.

INVERT

Invert the PWM output for each channel

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0x3f
  • Register enable: REGWEN

Fields

{"reg": [{"name": "INVERT_0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "INVERT_1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "INVERT_2", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "INVERT_3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "INVERT_4", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "INVERT_5", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
BitsTypeResetNameDescription
31:6Reserved
5rw0x0INVERT_5Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
4rw0x0INVERT_4Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
3rw0x0INVERT_3Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
2rw0x0INVERT_2Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
1rw0x0INVERT_1Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
0rw0x0INVERT_0Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

PWM_PARAM

Basic PWM Channel Parameters

  • Reset default: 0x0
  • Reset mask: 0xc000ffff

Instances

NameOffset
PWM_PARAM_00x14
PWM_PARAM_10x18
PWM_PARAM_20x1c
PWM_PARAM_30x20
PWM_PARAM_40x24
PWM_PARAM_50x28

Fields

{"reg": [{"name": "PHASE_DELAY", "bits": 16, "attr": ["rw"], "rotate": 0}, {"bits": 14}, {"name": "HTBT_EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "BLINK_EN", "bits": 1, "attr": ["rw"], "rotate": -90}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}}
BitsTypeResetName
31rw0x0BLINK_EN
30rw0x0HTBT_EN
29:16Reserved
15:0rw0x0PHASE_DELAY

Enables blink (or heartbeat). If cleared, the output duty cycle will remain constant at DUTY_CYCLE.A. Enabling this bit causes the PWM duty cycle to fluctuate between DUTY_CYCLE.A and DUTY_CYCLE.B

PWM_PARAM . HTBT_EN

Modulates blink behavior to create a heartbeat effect. When HTBT_EN is set, the duty cycle increases (or decreases) linearly from DUTY_CYCLE.A to DUTY_CYCLE.B and back, in steps of (BLINK_PARAM.Y+1), with an increment (decrement) once every (BLINK_PARAM.X+1) PWM cycles. When HTBT_EN is cleared, the standard blink behavior applies, meaning that the output duty cycle alternates between DUTY_CYCLE.A for (BLINK_PARAM.X+1) pulses and DUTY_CYCLE.B for (BLINK_PARAM.Y+1) pulses.

PWM_PARAM . PHASE_DELAY

Phase delay of the PWM rising edge, in units of 2^(-16) PWM cycles

DUTY_CYCLE

Controls the duty_cycle of each channel.

  • Reset default: 0x7fff7fff
  • Reset mask: 0xffffffff

Instances

NameOffset
DUTY_CYCLE_00x2c
DUTY_CYCLE_10x30
DUTY_CYCLE_20x34
DUTY_CYCLE_30x38
DUTY_CYCLE_40x3c
DUTY_CYCLE_50x40

Fields

{"reg": [{"name": "A", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "B", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:16rw0x7fffB
15:0rw0x7fffA

DUTY_CYCLE . B

The target duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting only applies when blinking, and determines the target duty cycle.

DUTY_CYCLE . A

The initial duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting applies continuously when not blinking and determines the initial duty cycle when blinking.

Hardware controlled blink/heartbeat parameters.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
BLINK_PARAM_00x44
BLINK_PARAM_10x48
BLINK_PARAM_20x4c
BLINK_PARAM_30x50
BLINK_PARAM_40x54
BLINK_PARAM_50x58

Fields

{"reg": [{"name": "X", "bits": 16, "attr": ["rw"], "rotate": 0}, {"name": "Y", "bits": 16, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}}
BitsTypeResetName
31:16rw0x0Y
15:0rw0x0X

This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle B for (Y+1) pulse cycles before returning to duty cycle A. If heartbeat is enabled the duty cycle will increase (or decrease) by (Y+1) units every time it is incremented (or decremented)

This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle A for (X+1) pulses before switching to duty cycle B. If heartbeat is enabled the duty-cycle will start at the duty cycle A, but will be incremented (or decremented) every (X+1) cycles. In heartbeat mode is enabled, the size of each step is controlled by BLINK_PARAM.Y.