Hardware Interfaces

Parameters

The following table lists the instantiation parameters of rstmgr.

ParameterDefaultDescription
SecCheck1Enables reset consistency checks on the leaf reset. Each check contains a small FSM.
SecMaxSyncDelay2The default synchronization delay assumptions used in reset consistency checks. If a design uses a sync cell with more stages of delay, that value should be supplied.

Signals

Referring to the Comportable guideline for peripheral device functionality, the module rstmgr has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: clk_aon_i, clk_io_div4_i, clk_main_i, clk_io_i, clk_io_div2_i, clk_usb_i, clk_por_i
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none
  • Interrupts: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
por_nlogicunircv2Root power on reset signals from ast. There is one root reset signal for each core power domain.
pwrpwr_rstreq_rsprsp1Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert.
resetsrstmgr_pkg::rstmgr_outunireq1Leaf resets fed to the system.
rst_enrstmgr_pkg::rstmgr_rst_enunireq1Low-power-group outputs used by alert handler.
alert_dumpalert_pkg::alert_crashdumpunircv1Alert handler crash dump information.
cpu_dumprv_core_ibex_pkg::cpu_crash_dumpunircv1Main processing element crash dump information.
sw_rst_reqprim_mubi_pkg::mubi4unireq1Software requested system reset to pwrmgr.
tltlul_pkg::tlreq_rsprsp1

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal structural fault is detected. Structural faults include errors such as sparse fsm errors and tlul integrity errors.
fatal_cnsty_faultThis fatal alert is triggered when a reset consistency fault is detected. It is separated from the category above for clearer error collection and debug.

Security Countermeasures

Countermeasure IDDescription
RSTMGR.BUS.INTEGRITYEnd-to-end bus integrity scheme.
RSTMGR.SCAN.INTERSIG.MUBIscan control signals are multibit
RSTMGR.LEAF.RST.BKGN_CHKBackground consistency checks for each leaf reset.
RSTMGR.LEAF.RST.SHADOWLeaf resets to blocks containing shadow registers are shadowed
RSTMGR.LEAF.FSM.SPARSESparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets
RSTMGR.SW_RST.CONFIG.REGWENSoftware reset controls are protected by regwen
RSTMGR.DUMP_CTRL.CONFIG.REGWENCrash dump controls are protected by regwen