OpenTitan Documentation

GPIO smoke test that exercises gpio pins as inputs or outputs, and performs data integrity checks by triggering scoreboard checks by reading data_in register. This test repeats following steps are random no. of times:

• Configures all gpio pins as inputs, drives random value on cio_gpio_i signal and reads data_in register after random delay
• Configures all gpio pins as outputs, programs direct_out and direct_oe registers to random values and reads data_in register after random delay

Verify the reset values as indicated in the RAL specification.

• Write all CSRs with a random value.
• Apply reset to the DUT as well as the RAL model.
• Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify accessibility of CSRs as indicated in the RAL specification.

• Loop through each CSR to write it with a random value.
• Read the CSR back and check for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within individual bits of a CSR.

• Walk a 1 through each CSR by flipping 1 bit at a time.
• Read the CSR back and check for correctness while adhering to its access policies.
• This verify that writing a specific bit within the CSR did not affect any of the other bits.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify no aliasing within the CSR address space.

• Loop through each CSR to write it with a random value
• Shuffle and read ALL CSRs back.
• All CSRs except for the one that was written in this iteration should read back the previous value.
• The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.
• Shuffle the list of CSRs first to remove the effect of ordering.

Verify random reset during CSR/memory access.

• Run csr_rw sequence to randomly access CSRs
• If memory exists, run mem_partial_access in parallel with csr_rw
• Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
• It is mandatory to run this test for all available interfaces the CSRs are accessible from.

Verify regwen CSR and its corresponding lockable CSRs.

• Randomly access all CSRs
• Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

• If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
• If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

GPIO test that programs DIRECT_OUT, DIRECT_OE, MASKED_OUT_LOWER, MASKED_OE_LOWER, MASKED_OUT_UPPER and MASKED_OE_UPPER registers and checks their effect on GPIO pins as well as DATA_IN register value. Every random iteration in this test would either:

• Program one or more of \*OUT\* and \*OE\* registers, or
• Drive new random value on GPIO pins

GPIO test that exercises functionality of DATA_OUT and DATA_OE internal registers, and DATA_IN register by programming any of \*OUT\ and \*OE\* registers, respectively. Every random iteration in this test would perform one out of following operations:

• Drive new random value on GPIO pins
• Write random value to any one of \*OUT\*, \*OE\* or DATA_IN registers
• Read any one of \*OUT\*, \*OE\* or DATA_IN registers

GPIO test which programs one or multiple interrupt registers to check GPIO interrupt functionality Every random iteration in this test would do either of following steps, and then read INTR_STATE register value:

• Drive new random value on GPIO pins (and thereby generate random interrupt event)
• Write random value to one or more interrupt registers that include INTR_ENABLE, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_LVL_LOW, INTR_CTRL_EN_LVL_HIGH and INTR_STATE

GPIO test that randomly generates and clears multiple GPIO interrupts for each random programming of interrupt registers, and performs checks by reading DATA_IN and INTR_STATE registers. Each random iteration of this test performs following operations:

1. Programs one more interrupt registers to random values
2. Following two operations are performed in parallel:
   • Drive random value on GPIO pins multiple times, every time at a random time intervals (random number of clock cycles)
   • Randomize random time interval (random number of clock cycles) and read either DATA_IN or INTR_STATE register value at randomized time interval After every read, optionally perform random interrupt clearing operation by writing to INTR_STATE register

GPIO test that exercise GPIO noise filter functionaliy along with random interrupt programming and randomly toggling each GPIO pin value, independently of other GPIO pins. Each random iteration performs following operations:

1. programs random values in one or more interrupt registers
2. optionally, programs new random value in CTRL_EN_INPUT_FILTER register
3. performs following operations in parallel:
   • drives each GPIO pin independently such that each pin has stable value for random number of clock cycles within the range [1:FILTER_CYCLES], and also predicts updates in values of DATA_IN and INTR_STATE registers
   • multiple registers reads, each for either DATA_IN or INTR_STATE

GPIO test that stresses noise filter functionality by driving each GPIO pin such independently of other pins, and driving could be either synchronous to clock or asynchronous. Each iteration in test does following:

1. Programs one or more interrupt registers with random values
2. Programs noise filter register with random value
3. Drives each GPIO pin with the mix of both synchronous and asynchronous driving, and each pin is driven independently of others

GPIO test that performs back-to-back register writes and back-to-back register reads on randomly selected GPIO registers. Each iteration in this test performs one out of following operations:

• Drive new random value on GPIO pins
• Perform multiple random writes on randomly selected GPIO registers
• Perform multiple random reads on randomly selected GPIO registers

GPIO full random test that performs any of following in each iteration:

• Drive new random value on GPIO pins such that GPIO inputs and GPIO outputs shall not result in unknown value on any pin
• Write to one or more of DIRECT_OUT, DIRECT_OE, MASKED_OUT_UPPER, MASKED_OE_UPPER, MASKED_OE_LOWER and MASKED_OE_LOWER registers such that GPIO inputs and GPIO outputs shall not result in unknown value on any pin
• Write to one or more of GPIO interrupt registers that include INTR_ENABLE, INTR_CTRL_EN_FALLING, INTR_CTRL_EN_RISING, INTR_CTRL_EN_LVL_HIGH, INTR_CTRL_EN_LVL_LOW and INTR_STATE
• Write to other GPIO registers DATA_IN, INTR_TEST, CTRL_EN_INPUT_FILTER
• Read any one of the GPIO registers
• Apply hard reset

Stress_all test is a random mix of all the test above except csr tests, gpio full random, intr_test and other gpio test that disabled scoreboard

Verify common alert_test CSR that allows SW to mock-inject alert requests.

• Enable a random set of alert requests by writing random value to alert_test CSR.
• Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
• During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
• Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
• Repeat the above steps a bunch of times.

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

• Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
• Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
• Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
• Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
• Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
• Repeat the above steps a bunch of times.

Access out of bounds address and verify correctness of response / behavior

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

• TL-UL protocol error cases
  • invalid opcode
  • some mask bits not set when opcode is PutFullData
  • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
  • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
  • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
  • size is greater than 2
• OpenTitan defined error cases
  • access unmapped address, expect d_error = 1 when devmode_i == 1
  • write a CSR with unaligned address, e.g. a_address[1:0] != 0
  • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
  • write a memory with a_mask != '1 when it doesn't support partial accesses
  • read a WO (write-only) memory
  • write a RO (read-only) memory
  • write with instr_type = True

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Verify that the data integrity check violation generates an alert.

• Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
• Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

Verify the countermeasure(s) BUS.INTEGRITY.

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Cover each lockable reg field with these 2 cases:

• When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
• When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

Cover the following error cases on TL-UL bus:

• TL-UL protocol error cases.
• OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.