Registers

The flash protocol controller maintains two separate access windows for the FIFO. It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read).

Summary of the core interface’s registers

NameOffsetLengthDescription
flash_ctrl.INTR_STATE0x04Interrupt State Register
flash_ctrl.INTR_ENABLE0x44Interrupt Enable Register
flash_ctrl.INTR_TEST0x84Interrupt Test Register
flash_ctrl.ALERT_TEST0xc4Alert Test Register
flash_ctrl.DIS0x104Disable flash functionality
flash_ctrl.EXEC0x144Controls whether flash can be used for code execution fetches
flash_ctrl.INIT0x184Controller init register
flash_ctrl.CTRL_REGWEN0x1c4Controls the configurability of the !!CONTROL register.
flash_ctrl.CONTROL0x204Control register
flash_ctrl.ADDR0x244Address for flash operation
flash_ctrl.PROG_TYPE_EN0x284Enable different program types
flash_ctrl.ERASE_SUSPEND0x2c4Suspend erase
flash_ctrl.REGION_CFG_REGWEN_00x304Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_10x344Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_20x384Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_30x3c4Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_40x404Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_50x444Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_60x484Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_70x4c4Memory region registers configuration enable.
flash_ctrl.MP_REGION_CFG_00x504Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_10x544Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_20x584Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_30x5c4Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_40x604Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_50x644Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_60x684Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_70x6c4Memory property configuration for data partition
flash_ctrl.MP_REGION_00x704Memory base and size configuration for data partition
flash_ctrl.MP_REGION_10x744Memory base and size configuration for data partition
flash_ctrl.MP_REGION_20x784Memory base and size configuration for data partition
flash_ctrl.MP_REGION_30x7c4Memory base and size configuration for data partition
flash_ctrl.MP_REGION_40x804Memory base and size configuration for data partition
flash_ctrl.MP_REGION_50x844Memory base and size configuration for data partition
flash_ctrl.MP_REGION_60x884Memory base and size configuration for data partition
flash_ctrl.MP_REGION_70x8c4Memory base and size configuration for data partition
flash_ctrl.DEFAULT_REGION0x904Default region properties
flash_ctrl.BANK0_INFO0_REGWEN_00x944Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_10x984Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_20x9c4Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_30xa04Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_40xa44Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_50xa84Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_60xac4Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_70xb04Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_80xb44Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_90xb84Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_PAGE_CFG_00xbc4Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_10xc04Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_20xc44Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_30xc84Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_40xcc4Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_50xd04Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_60xd44Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_70xd84Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_80xdc4Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO0_PAGE_CFG_90xe04Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO1_REGWEN0xe44Memory region registers configuration enable.
flash_ctrl.BANK0_INFO1_PAGE_CFG0xe84Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO2_REGWEN_00xec4Memory region registers configuration enable.
flash_ctrl.BANK0_INFO2_REGWEN_10xf04Memory region registers configuration enable.
flash_ctrl.BANK0_INFO2_PAGE_CFG_00xf44Memory property configuration for info partition in bank0,
flash_ctrl.BANK0_INFO2_PAGE_CFG_10xf84Memory property configuration for info partition in bank0,
flash_ctrl.BANK1_INFO0_REGWEN_00xfc4Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_10x1004Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_20x1044Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_30x1084Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_40x10c4Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_50x1104Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_60x1144Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_70x1184Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_80x11c4Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_90x1204Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_PAGE_CFG_00x1244Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_10x1284Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_20x12c4Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_30x1304Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_40x1344Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_50x1384Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_60x13c4Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_70x1404Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_80x1444Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO0_PAGE_CFG_90x1484Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO1_REGWEN0x14c4Memory region registers configuration enable.
flash_ctrl.BANK1_INFO1_PAGE_CFG0x1504Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO2_REGWEN_00x1544Memory region registers configuration enable.
flash_ctrl.BANK1_INFO2_REGWEN_10x1584Memory region registers configuration enable.
flash_ctrl.BANK1_INFO2_PAGE_CFG_00x15c4Memory property configuration for info partition in bank1,
flash_ctrl.BANK1_INFO2_PAGE_CFG_10x1604Memory property configuration for info partition in bank1,
flash_ctrl.HW_INFO_CFG_OVERRIDE0x1644HW interface info configuration rule overrides
flash_ctrl.BANK_CFG_REGWEN0x1684Bank configuration registers configuration enable.
flash_ctrl.MP_BANK_CFG_SHADOWED0x16c4Memory properties bank configuration
flash_ctrl.OP_STATUS0x1704Flash Operation Status
flash_ctrl.STATUS0x1744Flash Controller Status
flash_ctrl.DEBUG_STATE0x1784Current flash fsm state
flash_ctrl.ERR_CODE0x17c4Flash error code register.
flash_ctrl.STD_FAULT_STATUS0x1804This register tabulates standard fault status of the flash.
flash_ctrl.FAULT_STATUS0x1844This register tabulates customized fault status of the flash.
flash_ctrl.ERR_ADDR0x1884Synchronous error address
flash_ctrl.ECC_SINGLE_ERR_CNT0x18c4Total number of single bit ECC error count
flash_ctrl.ECC_SINGLE_ERR_ADDR_00x1904Latest address of ECC single err
flash_ctrl.ECC_SINGLE_ERR_ADDR_10x1944Latest address of ECC single err
flash_ctrl.PHY_ALERT_CFG0x1984Phy alert configuration
flash_ctrl.PHY_STATUS0x19c4Flash Phy Status
flash_ctrl.Scratch0x1a04Flash Controller Scratch
flash_ctrl.FIFO_LVL0x1a44Programmable depth where FIFOs should generate interrupts
flash_ctrl.FIFO_RST0x1a84Reset for flash controller FIFOs
flash_ctrl.CURR_FIFO_LVL0x1ac4Current program and read fifo depth
flash_ctrl.prog_fifo0x1b04Flash program FIFO.
flash_ctrl.rd_fifo0x1b44Flash read FIFO.

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x3
  • Reset mask: 0x3f

Fields

BitsTypeResetNameDescription
31:6Reserved
5rw1c0x0corr_errCorrectable error encountered
4rw1c0x0op_doneOperation complete
3ro0x0rd_lvlRead FIFO filled to level
2ro0x0rd_fullRead FIFO full
1ro0x1prog_lvlProgram FIFO drained to level
0ro0x1prog_emptyProgram FIFO empty

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x3f

Fields

BitsTypeResetNameDescription
31:6Reserved
5rw0x0corr_errEnable interrupt when INTR_STATE.corr_err is set.
4rw0x0op_doneEnable interrupt when INTR_STATE.op_done is set.
3rw0x0rd_lvlEnable interrupt when INTR_STATE.rd_lvl is set.
2rw0x0rd_fullEnable interrupt when INTR_STATE.rd_full is set.
1rw0x0prog_lvlEnable interrupt when INTR_STATE.prog_lvl is set.
0rw0x0prog_emptyEnable interrupt when INTR_STATE.prog_empty is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x3f

Fields

BitsTypeResetNameDescription
31:6Reserved
5wo0x0corr_errWrite 1 to force INTR_STATE.corr_err to 1.
4wo0x0op_doneWrite 1 to force INTR_STATE.op_done to 1.
3wo0x0rd_lvlWrite 1 to force INTR_STATE.rd_lvl to 1.
2wo0x0rd_fullWrite 1 to force INTR_STATE.rd_full to 1.
1wo0x0prog_lvlWrite 1 to force INTR_STATE.prog_lvl to 1.
0wo0x0prog_emptyWrite 1 to force INTR_STATE.prog_empty to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

BitsTypeResetNameDescription
31:5Reserved
4wo0x0recov_prim_flash_alertWrite 1 to trigger one alert event of this kind.
3wo0x0fatal_prim_flash_alertWrite 1 to trigger one alert event of this kind.
2wo0x0fatal_errWrite 1 to trigger one alert event of this kind.
1wo0x0fatal_std_errWrite 1 to trigger one alert event of this kind.
0wo0x0recov_errWrite 1 to trigger one alert event of this kind.

DIS

Disable flash functionality

  • Offset: 0x10
  • Reset default: 0x9
  • Reset mask: 0xf

Fields

BitsTypeResetName
31:4Reserved
3:0rw1s0x9VAL

DIS . VAL

Disables flash functionality completely. This is a shortcut mechanism used by the software to completely kill flash in case of emergency.

Since this register is rw1s instead of rw, to disable, write the value kMuBi4True to the register to disable the flash.

EXEC

Controls whether flash can be used for code execution fetches

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0ENA value of 0xa26a38f7 allows flash to be used for code execution. Any other value prevents code execution.

INIT

Controller init register

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetName
31:1Reserved
0rw1s0x0VAL

INIT . VAL

Initializes the flash controller.

During the initialization process, the flash controller requests the address and data scramble keys and reads out the root seeds stored in flash before allowing other usage of the flash controller.

When the initialization sequence is complete, the flash read buffers are enabled and turned on.

CTRL_REGWEN

Controls the configurability of the CONTROL register.

This register ensures the contents of CONTROL cannot be changed by software once a flash operation has begun.

It unlocks whenever the existing flash operation completes, regardless of success or error.

  • Offset: 0x1c
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0ro0x1ENConfiguration enable. This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated. When the controller completes the flash operation, this bit is set back to 1 to allow software configuration of CONTROL

CONTROL

Control register

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0xfff07f1
  • Register enable: CTRL_REGWEN

Fields

BitsTypeResetName
31:28Reserved
27:16rw0x0NUM
15:11Reserved
10:9rw0x0INFO_SEL
8rw0x0PARTITION_SEL
7rw0x0ERASE_SEL
6rw0x0PROG_SEL
5:4rw0x0OP
3:1Reserved
0rw0x0START

CONTROL . NUM

One fewer than the number of bus words the flash operation should read or program. For example, to read 10 words, software should program this field with the value 9.

CONTROL . INFO_SEL

Informational partions can have multiple types.

This field selects the info type to be accessed.

CONTROL . PARTITION_SEL

When doing a read, program or page erase operation, selects either info or data partition for operation. When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller. When 1, select info partition - this is the portion of flash that is only accessible by the controller.

When doing a bank erase operation, selects info partition also for erase. When 0, bank erase only erases data partition. When 1, bank erase erases data partition and info partition.

CONTROL . ERASE_SEL

Flash erase operation type selection

ValueNameDescription
0x0Page EraseErase 1 page of flash
0x1Bank EraseErase 1 bank of flash

CONTROL . PROG_SEL

Flash program operation type selection

ValueNameDescription
0x0Normal programNormal program operation to the flash
0x1Program repairRepair program operation to the flash. Whether this is actually supported depends on the underlying flash memory.

CONTROL . OP

Flash operation selection

ValueNameDescription
0x0ReadFlash Read. Read desired number of flash words
0x1ProgFlash Program. Program desired number of flash words
0x2EraseFlash Erase Operation. See ERASE_SEL for details on erase operation

Other values are reserved.

CONTROL . START

Start flash transaction. This bit shall only be set at the same time or after the other fields of the CONTROL register and ADDR have been programmed.

ADDR

Address for flash operation

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xfffff
  • Register enable: CTRL_REGWEN

Fields

BitsTypeResetName
31:20Reserved
19:0rw0x0START

ADDR . START

Start address of a flash transaction. This is a byte address relative to the flash only. Ie, an address of 0 will access address 0 of the requested partition.

For read operations, the flash controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10.

Program operations behave similarly, the controller does not have read modified write support.

For page erases, the controller will truncate to the closest lower page aligned address. Similarly for bank erases, the controller will truncate to the closest lower bank aligned address.

PROG_TYPE_EN

Enable different program types

  • Offset: 0x28
  • Reset default: 0x3
  • Reset mask: 0x3
  • Register enable: CTRL_REGWEN

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0c0x1REPAIRRepair prog type available
0rw0c0x1NORMALNormal prog type available

ERASE_SUSPEND

Suspend erase

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0REQWhen 1, request erase suspend. If no erase ongoing, the request is immediately cleared by hardware If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled.

REGION_CFG_REGWEN

Memory region registers configuration enable.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
REGION_CFG_REGWEN_00x30
REGION_CFG_REGWEN_10x34
REGION_CFG_REGWEN_20x38
REGION_CFG_REGWEN_30x3c
REGION_CFG_REGWEN_40x40
REGION_CFG_REGWEN_50x44
REGION_CFG_REGWEN_60x48
REGION_CFG_REGWEN_70x4c

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1REGION

REGION_CFG_REGWEN . REGION

Region register write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0Region lockedRegion can no longer be configured until next reset
0x1Region enabledRegion can be configured

MP_REGION_CFG

Memory property configuration for data partition

  • Reset default: 0x9999999
  • Reset mask: 0xfffffff

Instances

NameOffset
MP_REGION_CFG_00x50
MP_REGION_CFG_10x54
MP_REGION_CFG_20x58
MP_REGION_CFG_30x5c
MP_REGION_CFG_40x60
MP_REGION_CFG_50x64
MP_REGION_CFG_60x68
MP_REGION_CFG_70x6c

Fields

BitsTypeResetNameDescription
31:28Reserved
27:24rw0x9HE_ENRegion is high endurance enabled.
23:20rw0x9ECC_ENRegion is integrity checked and reliability ECC enabled.
19:16rw0x9SCRAMBLE_ENRegion is scramble enabled.
15:12rw0x9ERASE_ENRegion can be erased
11:8rw0x9PROG_ENRegion can be programmed
7:4rw0x9RD_ENRegion can be read
3:0rw0x9ENRegion enabled, following fields apply. If region is disabled, it is not matched against any incoming transaction.

MP_REGION

Memory base and size configuration for data partition

  • Reset default: 0x0
  • Reset mask: 0x7ffff

Instances

NameOffset
MP_REGION_00x70
MP_REGION_10x74
MP_REGION_20x78
MP_REGION_30x7c
MP_REGION_40x80
MP_REGION_50x84
MP_REGION_60x88
MP_REGION_70x8c

Fields

BitsTypeResetNameDescription
31:19Reserved
18:9rw0x0SIZERegion size in number of pages. For example, if base is 0 and size is 1, then the region is defined by page 0. If base is 0 and size is 2, then the region is defined by pages 0 and 1.
8:0rw0x0BASERegion base page. Note the granularity is page, not byte or word

DEFAULT_REGION

Default region properties

  • Offset: 0x90
  • Reset default: 0x999999
  • Reset mask: 0xffffff

Fields

BitsTypeResetNameDescription
31:24Reserved
23:20rw0x9HE_ENRegion is high endurance enabled.
19:16rw0x9ECC_ENRegion is ECC enabled (both integrity and reliability ECC).
15:12rw0x9SCRAMBLE_ENRegion is scramble enabled.
11:8rw0x9ERASE_ENRegion can be erased
7:4rw0x9PROG_ENRegion can be programmed
3:0rw0x9RD_ENRegion can be read

BANK0_INFO0_REGWEN

Memory region registers configuration enable.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
BANK0_INFO0_REGWEN_00x94
BANK0_INFO0_REGWEN_10x98
BANK0_INFO0_REGWEN_20x9c
BANK0_INFO0_REGWEN_30xa0
BANK0_INFO0_REGWEN_40xa4
BANK0_INFO0_REGWEN_50xa8
BANK0_INFO0_REGWEN_60xac
BANK0_INFO0_REGWEN_70xb0
BANK0_INFO0_REGWEN_80xb4
BANK0_INFO0_REGWEN_90xb8

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1REGION

BANK0_INFO0_REGWEN . REGION

Info0 page write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0Page lockedRegion can no longer be configured until next reset
0x1Page enabledRegion can be configured

BANK0_INFO0_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

  • Reset default: 0x9999999
  • Reset mask: 0xfffffff

Instances

NameOffset
BANK0_INFO0_PAGE_CFG_00xbc
BANK0_INFO0_PAGE_CFG_10xc0
BANK0_INFO0_PAGE_CFG_20xc4
BANK0_INFO0_PAGE_CFG_30xc8
BANK0_INFO0_PAGE_CFG_40xcc
BANK0_INFO0_PAGE_CFG_50xd0
BANK0_INFO0_PAGE_CFG_60xd4
BANK0_INFO0_PAGE_CFG_70xd8
BANK0_INFO0_PAGE_CFG_80xdc
BANK0_INFO0_PAGE_CFG_90xe0

Fields

BitsTypeResetNameDescription
31:28Reserved
27:24rw0x9HE_ENRegion is high endurance enabled.
23:20rw0x9ECC_ENRegion is ECC enabled (both integrity and reliability ECC).
19:16rw0x9SCRAMBLE_ENRegion is scramble enabled.
15:12rw0x9ERASE_ENRegion can be erased
11:8rw0x9PROG_ENRegion can be programmed
7:4rw0x9RD_ENRegion can be read
3:0rw0x9ENRegion enabled, following fields apply

BANK0_INFO1_REGWEN

Memory region registers configuration enable.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
BANK0_INFO1_REGWEN0xe4

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1REGION

BANK0_INFO1_REGWEN . REGION

Info1 page write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0Page lockedRegion can no longer be configured until next reset
0x1Page enabledRegion can be configured

BANK0_INFO1_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

  • Reset default: 0x9999999
  • Reset mask: 0xfffffff

Instances

NameOffset
BANK0_INFO1_PAGE_CFG0xe8

Fields

BitsTypeResetNameDescription
31:28Reserved
27:24rw0x9HE_ENRegion is high endurance enabled.
23:20rw0x9ECC_ENRegion is ECC enabled (both integrity and reliability ECC).
19:16rw0x9SCRAMBLE_ENRegion is scramble enabled.
15:12rw0x9ERASE_ENRegion can be erased
11:8rw0x9PROG_ENRegion can be programmed
7:4rw0x9RD_ENRegion can be read
3:0rw0x9ENRegion enabled, following fields apply

BANK0_INFO2_REGWEN

Memory region registers configuration enable.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
BANK0_INFO2_REGWEN_00xec
BANK0_INFO2_REGWEN_10xf0

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1REGION

BANK0_INFO2_REGWEN . REGION

Info2 page write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0Page lockedRegion can no longer be configured until next reset
0x1Page enabledRegion can be configured

BANK0_INFO2_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

  • Reset default: 0x9999999
  • Reset mask: 0xfffffff

Instances

NameOffset
BANK0_INFO2_PAGE_CFG_00xf4
BANK0_INFO2_PAGE_CFG_10xf8

Fields

BitsTypeResetNameDescription
31:28Reserved
27:24rw0x9HE_ENRegion is high endurance enabled.
23:20rw0x9ECC_ENRegion is ECC enabled (both integrity and reliability ECC).
19:16rw0x9SCRAMBLE_ENRegion is scramble enabled.
15:12rw0x9ERASE_ENRegion can be erased
11:8rw0x9PROG_ENRegion can be programmed
7:4rw0x9RD_ENRegion can be read
3:0rw0x9ENRegion enabled, following fields apply

BANK1_INFO0_REGWEN

Memory region registers configuration enable.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
BANK1_INFO0_REGWEN_00xfc
BANK1_INFO0_REGWEN_10x100
BANK1_INFO0_REGWEN_20x104
BANK1_INFO0_REGWEN_30x108
BANK1_INFO0_REGWEN_40x10c
BANK1_INFO0_REGWEN_50x110
BANK1_INFO0_REGWEN_60x114
BANK1_INFO0_REGWEN_70x118
BANK1_INFO0_REGWEN_80x11c
BANK1_INFO0_REGWEN_90x120

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1REGION

BANK1_INFO0_REGWEN . REGION

Info0 page write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0Page lockedRegion can no longer be configured until next reset
0x1Page enabledRegion can be configured

BANK1_INFO0_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

  • Reset default: 0x9999999
  • Reset mask: 0xfffffff

Instances

NameOffset
BANK1_INFO0_PAGE_CFG_00x124
BANK1_INFO0_PAGE_CFG_10x128
BANK1_INFO0_PAGE_CFG_20x12c
BANK1_INFO0_PAGE_CFG_30x130
BANK1_INFO0_PAGE_CFG_40x134
BANK1_INFO0_PAGE_CFG_50x138
BANK1_INFO0_PAGE_CFG_60x13c
BANK1_INFO0_PAGE_CFG_70x140
BANK1_INFO0_PAGE_CFG_80x144
BANK1_INFO0_PAGE_CFG_90x148

Fields

BitsTypeResetNameDescription
31:28Reserved
27:24rw0x9HE_ENRegion is high endurance enabled.
23:20rw0x9ECC_ENRegion is ECC enabled (both integrity and reliability ECC).
19:16rw0x9SCRAMBLE_ENRegion is scramble enabled.
15:12rw0x9ERASE_ENRegion can be erased
11:8rw0x9PROG_ENRegion can be programmed
7:4rw0x9RD_ENRegion can be read
3:0rw0x9ENRegion enabled, following fields apply

BANK1_INFO1_REGWEN

Memory region registers configuration enable.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
BANK1_INFO1_REGWEN0x14c

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1REGION

BANK1_INFO1_REGWEN . REGION

Info1 page write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0Page lockedRegion can no longer be configured until next reset
0x1Page enabledRegion can be configured

BANK1_INFO1_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

  • Reset default: 0x9999999
  • Reset mask: 0xfffffff

Instances

NameOffset
BANK1_INFO1_PAGE_CFG0x150

Fields

BitsTypeResetNameDescription
31:28Reserved
27:24rw0x9HE_ENRegion is high endurance enabled.
23:20rw0x9ECC_ENRegion is ECC enabled (both integrity and reliability ECC).
19:16rw0x9SCRAMBLE_ENRegion is scramble enabled.
15:12rw0x9ERASE_ENRegion can be erased
11:8rw0x9PROG_ENRegion can be programmed
7:4rw0x9RD_ENRegion can be read
3:0rw0x9ENRegion enabled, following fields apply

BANK1_INFO2_REGWEN

Memory region registers configuration enable.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
BANK1_INFO2_REGWEN_00x154
BANK1_INFO2_REGWEN_10x158

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1REGION

BANK1_INFO2_REGWEN . REGION

Info2 page write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0Page lockedRegion can no longer be configured until next reset
0x1Page enabledRegion can be configured

BANK1_INFO2_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

  • Reset default: 0x9999999
  • Reset mask: 0xfffffff

Instances

NameOffset
BANK1_INFO2_PAGE_CFG_00x15c
BANK1_INFO2_PAGE_CFG_10x160

Fields

BitsTypeResetNameDescription
31:28Reserved
27:24rw0x9HE_ENRegion is high endurance enabled.
23:20rw0x9ECC_ENRegion is ECC enabled (both integrity and reliability ECC).
19:16rw0x9SCRAMBLE_ENRegion is scramble enabled.
15:12rw0x9ERASE_ENRegion can be erased
11:8rw0x9PROG_ENRegion can be programmed
7:4rw0x9RD_ENRegion can be read
3:0rw0x9ENRegion enabled, following fields apply

HW_INFO_CFG_OVERRIDE

HW interface info configuration rule overrides

  • Offset: 0x164
  • Reset default: 0x99
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:4rw0x9ECC_DISThe hardwired hardware info configuration rules for ECC enable are logically AND’d with this field. If the hardware rules hardwires ECC to enable, we can disable via software if needed. By default this field is false.
3:0rw0x9SCRAMBLE_DISThe hardwired hardware info configuration rules for scramble enable are logically AND’d with this field. If the hardware rules hardwires scramble to enable, we can disable via software if needed. By default this field is false.

BANK_CFG_REGWEN

Bank configuration registers configuration enable.

  • Offset: 0x168
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1BANK

BANK_CFG_REGWEN . BANK

Bank register write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0Bank lockedBank can no longer be configured until next reset
0x1Bank enabledBank can be configured

MP_BANK_CFG_SHADOWED

Memory properties bank configuration

  • Offset: 0x16c
  • Reset default: 0x0
  • Reset mask: 0x3
  • Register enable: BANK_CFG_REGWEN

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0ERASE_EN_1Bank wide erase enable
0rw0x0ERASE_EN_0Bank wide erase enable

OP_STATUS

Flash Operation Status

  • Offset: 0x170
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0errFlash operation error. Set by HW, cleared by SW. See ERR_CODE for more details.
0rw0x0doneFlash operation done. Set by HW, cleared by SW

STATUS

Flash Controller Status

  • Offset: 0x174
  • Reset default: 0xa
  • Reset mask: 0x3f

Fields

BitsTypeResetNameDescription
31:6Reserved
5ro0x0initializedFlash controller initialized
4ro0x0init_wipFlash controller undergoing init, inclusive of phy init
3ro0x1prog_emptyFlash program FIFO empty, software must provide data
2ro0x0prog_fullFlash program FIFO full
1ro0x1rd_emptyFlash read FIFO empty
0ro0x0rd_fullFlash read FIFO full, software must consume data

DEBUG_STATE

Current flash fsm state

  • Offset: 0x178
  • Reset default: 0x0
  • Reset mask: 0x7ff

Fields

BitsTypeResetNameDescription
31:11Reserved
10:0roxlcmgr_stateCurrent lcmgr interface staet

ERR_CODE

Flash error code register. This register tabulates detailed error status of the flash. This is separate from OP_STATUS, which is used to indicate the current state of the software initiated flash operation.

Note, all errors in this register are considered recoverable errors, ie, errors that could have been generated by software.

  • Offset: 0x17c
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7rw1c0x0macro_errA recoverable error has been encountered in the flash macro. Please read the flash macro status registers for more details.
6rw1c0x0update_errA shadow register encountered an update error. This is an asynchronous error.
5rw1c0x0prog_type_errFlash program selected unavailable type, see PROG_TYPE_EN. This is a synchronous error.
4rw1c0x0prog_win_errFlash program has a window resolution error. Ie, the start of program and end of program are in different windows. Please check ERR_ADDR. This is a synchronous error.
3rw1c0x0prog_errFlash program has an error. This could be a program integrity error, see STD_FAULT_STATUS. This is a synchronous error.
2rw1c0x0rd_errFlash read has an error. This could be a reliability ECC error or an storage integrity error encountered during a software issued controller read, see STD_FAULT_STATUS. See ERR_ADDR for exact address. This is a synchronous error.
1rw1c0x0mp_errFlash access has encountered an access permission error. Please see ERR_ADDR for exact address. This is a synchronous error.
0rw1c0x0op_errSoftware has supplied an undefined operation. See CONTROL.OP for list of valid operations.

STD_FAULT_STATUS

This register tabulates standard fault status of the flash.

These represent errors that occur in the standard structures of the design. For example fsm integrity, counter integrity and tlul integrity.

  • Offset: 0x180
  • Reset default: 0x0
  • Reset mask: 0x1ff

Fields

BitsTypeResetNameDescription
31:9Reserved
8ro0x0fifo_errFlash primitive fifo’s have encountered a count error.
7ro0x0ctrl_cnt_errFlash ctrl read/prog has encountered a count error.
6ro0x0phy_fsm_errA flash phy fsm has encountered a sparse encoding error.
5ro0x0storage_errA shadow register encountered a storage error.
4ro0x0arb_fsm_errThe arbiter fsm has encountered a sparse encoding error.
3ro0x0lcmgr_intg_errThe life cycle management interface has encountered a transmission integrity error. This is an integrity error on the generated integrity during a life cycle management interface read.
2ro0x0lcmgr_errThe life cycle management interface has encountered a fatal error. The error is either an FSM sparse encoding error or a count error.
1ro0x0prog_intg_errThe flash controller encountered a program data transmission integrity error.
0ro0x0reg_intg_errThe flash controller encountered a register integrity error.

FAULT_STATUS

This register tabulates customized fault status of the flash.

These are errors that are impossible to have been caused by software or unrecoverable in nature.

  • Offset: 0x184
  • Reset default: 0x0
  • Reset mask: 0xfff

Fields

BitsTypeResetNameDescription
31:12Reserved
11ro0x0host_gnt_errA host transaction was granted with illegal properties.
10ro0x0arb_errThe phy arbiter encountered inconsistent results.
9ro0x0spurious_ackThe flash emitted an unexpected acknowledgement.
8ro0x0phy_storage_errThe flash macro encountered a storage integrity ECC error.
7ro0x0phy_relbl_errThe flash macro encountered a storage reliability ECC error.
6ro0x0seed_errThe seed reading process encountered an unexpected error.
5ro0x0prog_type_errThe flash life cycle management interface encountered a program type error. A program type not supported by the flash macro was issued.
4ro0x0prog_win_errThe flash life cycle management interface encountered a program resolution error.
3ro0x0prog_errThe flash life cycle management interface encountered a program error. This could be a program integirty eror, see STD_FAULT_STATUS for more details.
2ro0x0rd_errThe flash life cycle management interface encountered a read error. This could be a reliability ECC error or an integrity ECC error encountered during a read, see STD_FAULT_STATUS for more details.
1ro0x0mp_errThe flash life cycle management interface encountered a memory permission error.
0ro0x0op_errThe flash life cycle management interface has supplied an undefined operation. See CONTROL.OP for list of valid operations.

ERR_ADDR

Synchronous error address

  • Offset: 0x188
  • Reset default: 0x0
  • Reset mask: 0xfffff

Fields

BitsTypeResetNameDescription
31:20Reserved
19:0ro0x0ERR_ADDR

ECC_SINGLE_ERR_CNT

Total number of single bit ECC error count

  • Offset: 0x18c
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

BitsTypeResetNameDescription
31:16Reserved
15:8rw0x0ECC_SINGLE_ERR_CNT_1This count will not wrap when saturated
7:0rw0x0ECC_SINGLE_ERR_CNT_0This count will not wrap when saturated

ECC_SINGLE_ERR_ADDR

Latest address of ECC single err

  • Reset default: 0x0
  • Reset mask: 0xfffff

Instances

NameOffset
ECC_SINGLE_ERR_ADDR_00x190
ECC_SINGLE_ERR_ADDR_10x194

Fields

BitsTypeResetNameDescription
31:20Reserved
19:0ro0x0ECC_SINGLE_ERR_ADDRLatest single error address for this bank

PHY_ALERT_CFG

Phy alert configuration

  • Offset: 0x198
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0alert_trigTrigger flash phy alert
0rw0x0alert_ackAcknowledge flash phy alert

PHY_STATUS

Flash Phy Status

  • Offset: 0x19c
  • Reset default: 0x6
  • Reset mask: 0x7

Fields

BitsTypeResetNameDescription
31:3Reserved
2ro0x1prog_repair_availProgram repair supported
1ro0x1prog_normal_availNormal program supported
0ro0x0init_wipFlash phy controller initializing

Scratch

Flash Controller Scratch

  • Offset: 0x1a0
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0dataFlash ctrl scratch register

FIFO_LVL

Programmable depth where FIFOs should generate interrupts

  • Offset: 0x1a4
  • Reset default: 0xf0f
  • Reset mask: 0x1f1f

Fields

BitsTypeResetNameDescription
31:13Reserved
12:8rw0xfRDWhen the read FIFO fills to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.
7:5Reserved
4:0rw0xfPROGWhen the program FIFO drains to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.

FIFO_RST

Reset for flash controller FIFOs

  • Offset: 0x1a8
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0ENActive high resets for both program and read FIFOs. This is especially useful after the controller encounters an error of some kind. This bit will hold the FIFO in reset as long as it is set.

CURR_FIFO_LVL

Current program and read fifo depth

  • Offset: 0x1ac
  • Reset default: 0x0
  • Reset mask: 0x1f1f

Fields

BitsTypeResetNameDescription
31:13Reserved
12:8ro0x0RDCurrent read fifo depth
7:5Reserved
4:0ro0x0PROGCurrent program fifo depth

prog_fifo

Flash program FIFO.

The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed by software after a program operation has been initiated via the !!CONTROL register. This ensures accidental programming of the program FIFO cannot lock up the system.

  • Word Aligned Offset Range: 0x1b0to0x1b0
  • Size (words): 1
  • Access: wo
  • Byte writes are not supported.

rd_fifo

Flash read FIFO.

The FIFO is 16 entries of 4B flash words

  • Word Aligned Offset Range: 0x1b4to0x1b4
  • Size (words): 1
  • Access: ro
  • Byte writes are not supported.

Summary of the prim interface’s registers

NameOffsetLengthDescription
flash_ctrl.CSR0_REGWEN0x04
flash_ctrl.CSR10x44
flash_ctrl.CSR20x84
flash_ctrl.CSR30xc4
flash_ctrl.CSR40x104
flash_ctrl.CSR50x144
flash_ctrl.CSR60x184
flash_ctrl.CSR70x1c4
flash_ctrl.CSR80x204
flash_ctrl.CSR90x244
flash_ctrl.CSR100x284
flash_ctrl.CSR110x2c4
flash_ctrl.CSR120x304
flash_ctrl.CSR130x344
flash_ctrl.CSR140x384
flash_ctrl.CSR150x3c4
flash_ctrl.CSR160x404
flash_ctrl.CSR170x444
flash_ctrl.CSR180x484
flash_ctrl.CSR190x4c4
flash_ctrl.CSR200x504

CSR0_REGWEN

  • Offset: 0x0
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1field0

CSR0_REGWEN . field0

All values are reserved.

CSR1

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x1fff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:13Reserved
12:8rw0x0field1
7:0rw0x0field0

CSR1 . field1

All values are reserved.

CSR1 . field0

All values are reserved.

CSR2

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetName
31:8Reserved
7rw0x0field7
6rw1c0x0field6
5rw1c0x0field5
4rw1c0x0field4
3rw0x0field3
2rw1c0x0field2
1rw1c0x0field1
0rw1c0x0field0

CSR2 . field7

All values are reserved.

CSR2 . field6

All values are reserved.

CSR2 . field5

All values are reserved.

CSR2 . field4

All values are reserved.

CSR2 . field3

All values are reserved.

CSR2 . field2

All values are reserved.

CSR2 . field1

All values are reserved.

CSR2 . field0

All values are reserved.

CSR3

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0xfffffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:28Reserved
27:26rw0x0field9
25:24rw0x0field8
23:21rw0x0field7
20rw0x0field6
19:17rw0x0field5
16:14rw0x0field4
13:11rw0x0field3
10:8rw0x0field2
7:4rw0x0field1
3:0rw0x0field0

CSR3 . field9

All values are reserved.

CSR3 . field8

All values are reserved.

CSR3 . field7

All values are reserved.

CSR3 . field6

All values are reserved.

CSR3 . field5

All values are reserved.

CSR3 . field4

All values are reserved.

CSR3 . field3

All values are reserved.

CSR3 . field2

All values are reserved.

CSR3 . field1

All values are reserved.

CSR3 . field0

All values are reserved.

CSR4

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xfff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:12Reserved
11:9rw0x0field3
8:6rw0x0field2
5:3rw0x0field1
2:0rw0x0field0

CSR4 . field3

All values are reserved.

CSR4 . field2

All values are reserved.

CSR4 . field1

All values are reserved.

CSR4 . field0

All values are reserved.

CSR5

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0x7fffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:23Reserved
22:19rw0x0field4
18:14rw0x0field3
13:5rw0x0field2
4:3rw0x0field1
2:0rw0x0field0

CSR5 . field4

All values are reserved.

CSR5 . field3

All values are reserved.

CSR5 . field2

All values are reserved.

CSR5 . field1

All values are reserved.

CSR5 . field0

All values are reserved.

CSR6

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0x1ffffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:25Reserved
24rw0x0field8
23rw0x0field7
22:21rw0x0field6
20:19rw0x0field5
18:17rw0x0field4
16:14rw0x0field3
13:6rw0x0field2
5:3rw0x0field1
2:0rw0x0field0

CSR6 . field8

All values are reserved.

CSR6 . field7

All values are reserved.

CSR6 . field6

All values are reserved.

CSR6 . field5

All values are reserved.

CSR6 . field4

All values are reserved.

CSR6 . field3

All values are reserved.

CSR6 . field2

All values are reserved.

CSR6 . field1

All values are reserved.

CSR6 . field0

All values are reserved.

CSR7

  • Offset: 0x1c
  • Reset default: 0x0
  • Reset mask: 0x1ffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:17Reserved
16:8rw0x0field1
7:0rw0x0field0

CSR7 . field1

All values are reserved.

CSR7 . field0

All values are reserved.

CSR8

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:0rw0x0field0

CSR8 . field0

All values are reserved.

CSR9

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:0rw0x0field0

CSR9 . field0

All values are reserved.

CSR10

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:0rw0x0field0

CSR10 . field0

All values are reserved.

CSR11

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:0rw0x0field0

CSR11 . field0

All values are reserved.

CSR12

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0x3ff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:10Reserved
9:0rw0x0field0

CSR12 . field0

All values are reserved.

CSR13

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0x1fffff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:21Reserved
20rw0x0field1
19:0rw0x0field0

CSR13 . field1

All values are reserved.

CSR13 . field0

All values are reserved.

CSR14

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0x1ff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:9Reserved
8rw0x0field1
7:0rw0x0field0

CSR14 . field1

All values are reserved.

CSR14 . field0

All values are reserved.

CSR15

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0x1ff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:9Reserved
8rw0x0field1
7:0rw0x0field0

CSR15 . field1

All values are reserved.

CSR15 . field0

All values are reserved.

CSR16

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0x1ff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:9Reserved
8rw0x0field1
7:0rw0x0field0

CSR16 . field1

All values are reserved.

CSR16 . field0

All values are reserved.

CSR17

  • Offset: 0x44
  • Reset default: 0x0
  • Reset mask: 0x1ff
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:9Reserved
8rw0x0field1
7:0rw0x0field0

CSR17 . field1

All values are reserved.

CSR17 . field0

All values are reserved.

CSR18

  • Offset: 0x48
  • Reset default: 0x0
  • Reset mask: 0x1
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:1Reserved
0rw0x0field0

CSR18 . field0

All values are reserved.

CSR19

  • Offset: 0x4c
  • Reset default: 0x0
  • Reset mask: 0x1
  • Register enable: CSR0_REGWEN

Fields

BitsTypeResetName
31:1Reserved
0rw0x0field0

CSR19 . field0

All values are reserved.

CSR20

  • Offset: 0x50
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

BitsTypeResetName
31:3Reserved
2ro0x0field2
1rw1c0x0field1
0rw1c0x0field0

CSR20 . field2

All values are reserved.

CSR20 . field1

All values are reserved.

CSR20 . field0

All values are reserved.

This interface does not expose any registers.