Testpoints
Stage | Name | Tests | Description |
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V1 | smoke | pwm_smoke | pwm_smoke tests pulse and blink mode for a single channel Stimulus:
Checking:
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V1 | csr_hw_reset | pwm_csr_hw_reset | Verify the reset values as indicated in the RAL specification.
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V1 | csr_rw | pwm_csr_rw | Verify accessibility of CSRs as indicated in the RAL specification.
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V1 | csr_bit_bash | pwm_csr_bit_bash | Verify no aliasing within individual bits of a CSR.
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V1 | csr_aliasing | pwm_csr_aliasing | Verify no aliasing within the CSR address space.
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V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | Verify random reset during CSR/memory access.
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V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw pwm_csr_aliasing | Verify regwen CSR and its corresponding lockable CSRs.
Note:
This is only applicable if the block contains regwen and locakable CSRs. |
V2 | dutycycle | pwm_rand_output | Verify different duty cycle settings in Pulse, Blink and Heart Beat mode. |
V2 | pulse | pwm_rand_output | Verify the pulse mode of the PWM by de-asserting blink_en field in the PWM_PARAM register |
V2 | blink | pwm_rand_output | Verify the blink mode of the PWM by asserting the blink_en field in the PWM_PARAM register |
V2 | heartbeat | pwm_rand_output | Verify the Heart Beat mode of the PWM by asserting the blink_en and HTBT field in the PWM_PARAM register |
V2 | resolution | pwm_rand_output | Verify the PWM generates correct duty cycle for different resolution settings |
V2 | multi_channel | pwm_rand_output | Verifies that PWM correctly generates pulses on multiple channels concurrently |
V2 | polarity | pwm_rand_output | Verify that the polarity of the pulse can be inverted by setting the invert channel bit in the invert register |
V2 | phase | pwm_rand_output | Check that the relative phase between pulses matches the setting in the phase_delay field in the PWM_PARAM register. |
V2 | lowpower | pwm_rand_output | Verify the PWM can continue when the chip is in low power mode. Stimulus: - start PWM on one or more channels - stop the TL UL clock Checks: - Ensure pulses are still generated when in LP mode |
V2 | perf | pwm_perf | Checking ip operation at min/max bandwidth Stimulus: - Program timing registers (CLK_DIV, DC_RESN) to high/low values (slow/fast data rate) - Program other required registers for pwm operation - Start pwm channels Checks: - Ensure the output pulses are correctly modulated for all channels |
V2 | stress_all | pwm_stress_all | Combine above sequences in one test then randomly select for running Stimulus: - Start sequences and randomly add reset between each sequence Checking: - All sequences should be finished and checked by the scoreboard |
V2 | alert_test | pwm_alert_test | Verify common
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V2 | intr_test | pwm_intr_test | Verify common intr_test CSRs that allows SW to mock-inject interrupts.
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V2 | tl_d_oob_addr_access | pwm_tl_errors | Access out of bounds address and verify correctness of response / behavior |
V2 | tl_d_illegal_access | pwm_tl_errors | Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec
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V2 | tl_d_outstanding_access | pwm_csr_hw_reset pwm_csr_rw pwm_csr_aliasing pwm_same_csr_outstanding | Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address. |
V2 | tl_d_partial_access | pwm_csr_hw_reset pwm_csr_rw pwm_csr_aliasing pwm_same_csr_outstanding | Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields. |
V2S | tl_intg_err | pwm_tl_intg_err pwm_sec_cm | Verify that the data integrity check violation generates an alert.
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V2S | sec_cm_bus_integrity | pwm_tl_intg_err | Verify the countermeasure(s) BUS.INTEGRITY. |
Covergroups
Name | Description |
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blink_param_cg | Covers that a good range of combinations of values for X and Y have been seend. Also cover that multiple channels can run concurrently with different settings for X and Y. |
cfg_cg | Covers that valid settings for the PWM.CFG register has been tested. This includes values for: - clk_div - dc_resn - cntr_en |
clock_cg | Cover that a range of frequencies have been tested for the PWM clock including a clock that matches the TL clk. |
duty_cycle_cg | Covers that a good range of combinations of values for A and B have been send. Also cover that multiple channels can run concurrently with different settings for A and B. Cover these cases: - A > B - A < B - A == B |
invert_cg | Covers that channels have been tested with different polarity Also cover that a mix channels with invert enabled and disabled concurrently have been tested. |
lowpower_cg | Covers that the DUT will continue to produce pulses with TL clock disabled (low power mode) |
overwrite_conf_cg | Cover that a the PWM configuration cannot be altered while a channel is active |
pwm_en_cg | Covers that both runs with a single PWM channel and multiple channels has been tested. Verifies both when the channels are enabled for parallel behavior (activated at the same time) and activated individually |
pwm_param_cg | Covers that both pulse, blink and heart beat mode have been tested. Also covers that.
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regwen_cg | Covers that an attempt to write wen REG enable was made and was unsuccessful |
regwen_val_when_new_value_written_cg | Cover each lockable reg field with these 2 cases:
This is only applicable if the block contains regwen and locakable CSRs. |
tl_errors_cg | Cover the following error cases on TL-UL bus:
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tl_intg_err_cg | Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check. Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied. |