Testpoints

Stage Name Tests Description
V1 smoke pwm_smoke

pwm_smoke tests pulse and blink mode for a single channel

Stimulus:

  • configure the envionment for one PWM channel
  • program the duty cycle a and b values
  • configure the ClkDiv and Resn

Checking:

  • ensure pulses are generated correctly in pulse or blink mode
V1 csr_hw_reset pwm_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

  • Write all CSRs with a random value.
  • Apply reset to the DUT as well as the RAL model.
  • Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_rw pwm_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

  • Loop through each CSR to write it with a random value.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_bit_bash pwm_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

  • Walk a 1 through each CSR by flipping 1 bit at a time.
  • Read the CSR back and check for correctness while adhering to its access policies.
  • This verify that writing a specific bit within the CSR did not affect any of the other bits.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_aliasing pwm_csr_aliasing

Verify no aliasing within the CSR address space.

  • Loop through each CSR to write it with a random value
  • Shuffle and read ALL CSRs back.
  • All CSRs except for the one that was written in this iteration should read back the previous value.
  • The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
  • Shuffle the list of CSRs first to remove the effect of ordering.
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

  • Run csr_rw sequence to randomly access CSRs
  • If memory exists, run mem_partial_access in parallel with csr_rw
  • Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
  • It is mandatory to run this test for all available interfaces the CSRs are accessible from.
V1 regwen_csr_and_corresponding_lockable_csrpwm_csr_rw
pwm_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

  • Randomly access all CSRs
  • Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

  • If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
  • If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

V2 dutycycle pwm_rand_output

Verify different duty cycle settings in Pulse, Blink and Heart Beat mode.

V2 pulse pwm_rand_output

Verify the pulse mode of the PWM by de-asserting blink_en field in the PWM_PARAM register

V2 blink pwm_rand_output

Verify the blink mode of the PWM by asserting the blink_en field in the PWM_PARAM register

V2 heartbeat pwm_rand_output

Verify the Heart Beat mode of the PWM by asserting the blink_en and HTBT field in the PWM_PARAM register

V2 resolution pwm_rand_output

Verify the PWM generates correct duty cycle for different resolution settings

V2 multi_channel pwm_rand_output

Verifies that PWM correctly generates pulses on multiple channels concurrently

V2 polarity pwm_rand_output

Verify that the polarity of the pulse can be inverted by setting the invert channel bit in the invert register

V2 phase pwm_rand_output

Check that the relative phase between pulses matches the setting in the phase_delay field in the PWM_PARAM register.

V2 lowpower pwm_rand_output

Verify the PWM can continue when the chip is in low power mode. Stimulus: - start PWM on one or more channels - stop the TL UL clock

Checks: - Ensure pulses are still generated when in LP mode

V2 perf pwm_perf

Checking ip operation at min/max bandwidth

Stimulus: - Program timing registers (CLK_DIV, DC_RESN) to high/low values (slow/fast data rate) - Program other required registers for pwm operation - Start pwm channels

Checks: - Ensure the output pulses are correctly modulated for all channels

V2 stress_all pwm_stress_all

Combine above sequences in one test then randomly select for running

Stimulus: - Start sequences and randomly add reset between each sequence

Checking: - All sequences should be finished and checked by the scoreboard

V2 alert_test pwm_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

  • Enable a random set of alert requests by writing random value to alert_test CSR.
  • Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
  • During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
  • Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
  • Repeat the above steps a bunch of times.
V2 intr_test pwm_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

  • Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
  • Randomly "turn on" interrupts by writing random value(s) to intr_test CSR(s).
  • Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
  • Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
  • Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
  • Repeat the above steps a bunch of times.
V2 tl_d_oob_addr_access pwm_tl_errors

Access out of bounds address and verify correctness of response / behavior

V2 tl_d_illegal_access pwm_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

  • TL-UL protocol error cases
    • invalid opcode
    • some mask bits not set when opcode is PutFullData
    • mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
    • mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
    • address and size aren't aligned, e.g. a_address = 0x01, a_size != 0
    • size is greater than 2
  • OpenTitan defined error cases
    • access unmapped address, expect d_error = 1 when devmode_i == 1
    • write a CSR with unaligned address, e.g. a_address[1:0] != 0
    • write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
    • write a memory with a_mask != '1 when it doesn't support partial accesses
    • read a WO (write-only) memory
    • write a RO (read-only) memory
    • write with instr_type = True
V2 tl_d_outstanding_access pwm_csr_hw_reset
pwm_csr_rw
pwm_csr_aliasing
pwm_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

V2 tl_d_partial_access pwm_csr_hw_reset
pwm_csr_rw
pwm_csr_aliasing
pwm_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

V2S tl_intg_err pwm_tl_intg_err
pwm_sec_cm

Verify that the data integrity check violation generates an alert.

  • Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
  • Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs
V2S sec_cm_bus_integrity pwm_tl_intg_err

Verify the countermeasure(s) BUS.INTEGRITY.

Covergroups

Name Description
blink_param_cg

Covers that a good range of combinations of values for X and Y have been seend. Also cover that multiple channels can run concurrently with different settings for X and Y.

cfg_cg

Covers that valid settings for the PWM.CFG register has been tested. This includes values for: - clk_div - dc_resn - cntr_en

clock_cg

Cover that a range of frequencies have been tested for the PWM clock including a clock that matches the TL clk.

duty_cycle_cg

Covers that a good range of combinations of values for A and B have been send. Also cover that multiple channels can run concurrently with different settings for A and B. Cover these cases: - A > B - A < B - A == B

invert_cg

Covers that channels have been tested with different polarity Also cover that a mix channels with invert enabled and disabled concurrently have been tested.

lowpower_cg

Covers that the DUT will continue to produce pulses with TL clock disabled (low power mode)

overwrite_conf_cg

Cover that a the PWM configuration cannot be altered while a channel is active

pwm_en_cg

Covers that both runs with a single PWM channel and multiple channels has been tested. Verifies both when the channels are enabled for parallel behavior (activated at the same time) and activated individually

pwm_param_cg

Covers that both pulse, blink and heart beat mode have been tested. Also covers that.

  • various phase delays have been tested
  • different delays on different concurrent channels
regwen_cg

Covers that an attempt to write wen REG enable was made and was unsuccessful

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

  • When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
  • When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

tl_errors_cg

Cover the following error cases on TL-UL bus:

  • TL-UL protocol error cases.
  • OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.
tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.