1. OpenTitan
  2. Getting Started
  3. 1. Getting Started
  4. 2. Workflows
    ❱
    1. 2.1. Design Verification
    2. 2.2. Formal Verification
    3. 2.3. Building (and Testing) Software
    4. 2.4. Building Documentation
    5. 2.5. Using OpenOCD
  5. 3. Tools Setup
    ❱
    1. 3.1. FPGA Setup
    2. 3.2. Verilator Setup
    3. 3.3. Installing Vivado
  6. 4. Unofficial Guides
    ❱
    1. 4.1. RedHat/Fedora
  7. Hardware
  8. 5. Introduction
  9. 6. Top Earlgrey
    ❱
    1. 6.1. Datasheet
    2. 6.2. Design
    3. 6.3. Design Verification
      ❱
      1. 6.3.1. Chip Testplan
    4. 6.4. Analog Sensor Top
      ❱
      1. 6.4.1. Interfaces
    5. 6.5. Alert Handler
      ❱
      1. 6.5.1. Theory of Operation
      2. 6.5.2. Design Verification
        ❱
        1. 6.5.2.1. Testplan
      3. 6.5.3. Programmer's Guide
      4. 6.5.4. Interface and Registers
      5. 6.5.5. Device Interface Functions
      6. 6.5.6. Checklist
    6. 6.6. Interrupt Controller
      ❱
      1. 6.6.1. Theory of Operation
      2. 6.6.2. Design Verification
        ❱
        1. 6.6.2.1. Testplan
      3. 6.6.3. Programmer's Guide
      4. 6.6.4. Interface and Registers
      5. 6.6.5. Device Interface Functions
      6. 6.6.6. Checklist
    7. 6.7. Sensor Control
      ❱
      1. 6.7.1. Theory of Operation
      2. 6.7.2. Programmer's Guide
      3. 6.7.3. Interface and Registers
      4. 6.7.4. Device Interface Functions
      5. 6.7.5. Checklist
    8. 6.8. TL-UL Checklist
    9. 6.9. Pinmux Targets
      ❱
      1. 6.9.1. ASIC Target Pinout and Pinmux Connectivity
      2. 6.9.2. CW310 Target Pinout and Pinmux Connectivity
      3. 6.9.3. CW340 Target Pinout and Pinmux Connectivity
  10. 7. Top Darjeeling
    ❱
    1. 7.1. Datasheet
  11. 8. Cores
    ❱
    1. 8.1. Ibex RISC-V Core Wrapper
      ❱
      1. 8.1.1. Theory of Operation
      2. 8.1.2. Design Verification
      3. 8.1.3. Programmer's Guide
      4. 8.1.4. Hardware Interfaces
      5. 8.1.5. Registers
      6. 8.1.6. Checklist
    2. 8.2. OTBN
      ❱
      1. 8.2.1. Theory of Operation
      2. 8.2.2. Introduction to OTBN
      3. 8.2.3. Developing OTBN
      4. 8.2.4. ISA Guide
      5. 8.2.5. Design Verification
        ❱
        1. 8.2.5.1. Random Instruction Generator
          ❱
          1. 8.2.5.1.1. Internals
          2. 8.2.5.1.2. Configuration
        2. 8.2.5.2. memutil wrapper
        3. 8.2.5.3. OTBN Simulation Software
        4. 8.2.5.4. Tracer
        5. 8.2.5.5. Formal Masking Verification Using Alma
      6. 8.2.6. Functional Coverage
      7. 8.2.7. Programmer's Guide
      8. 8.2.8. Hardware Interfaces
      9. 8.2.9. Registers
      10. 8.2.10. Checklist
  12. 9. Hardware IP Blocks
    ❱
    1. 9.1. Analog to Digital Converter Control
      ❱
      1. 9.1.1. Theory of Operation
      2. 9.1.2. Design Verification
        ❱
        1. 9.1.2.1. Testplan
      3. 9.1.3. Programmer's Guide
      4. 9.1.4. Hardware Interfaces
      5. 9.1.5. Registers
      6. 9.1.6. Checklist
    2. 9.2. AES
      ❱
      1. 9.2.1. Theory of Operation
      2. 9.2.2. Design Verification
        ❱
        1. 9.2.2.1. Testplan
      3. 9.2.3. Programmer's Guide
      4. 9.2.4. Hardware Interfaces
      5. 9.2.5. Registers
      6. 9.2.6. Device Interface Functions
      7. 9.2.7. Checklist
    3. 9.3. AON Timer
      ❱
      1. 9.3.1. Theory of Operation
      2. 9.3.2. Design Verification
        ❱
        1. 9.3.2.1. Testplan
      3. 9.3.3. Programmer's Guide
      4. 9.3.4. Hardware Interfaces
      5. 9.3.5. Registers
      6. 9.3.6. Device Interface Functions
      7. 9.3.7. Checklist
    4. 9.4. Clock Manager
      ❱
      1. 9.4.1. Theory of Operation
      2. 9.4.2. Design Verification
        ❱
        1. 9.4.2.1. Testplan
      3. 9.4.3. Programmer's Guide
      4. 9.4.4. Hardware Interfaces
      5. 9.4.5. Registers
      6. 9.4.6. Device Interface Functions
      7. 9.4.7. Checklist
    5. 9.5. CSRNG
      ❱
      1. 9.5.1. Theory of Operation
      2. 9.5.2. Design Verification
        ❱
        1. 9.5.2.1. Testplan
      3. 9.5.3. Programmer's Guide
      4. 9.5.4. Hardware Interfaces
      5. 9.5.5. Registers
      6. 9.5.6. Device Interface Functions
      7. 9.5.7. Checklist
    6. 9.6. EDN
      ❱
      1. 9.6.1. Theory of Operation
      2. 9.6.2. Design Verification
        ❱
        1. 9.6.2.1. Testplan
      3. 9.6.3. Programmer's Guide
      4. 9.6.4. Hardware Interfaces
      5. 9.6.5. Registers
      6. 9.6.6. Device Interface Functions
      7. 9.6.7. Checklist
    7. 9.7. Entropy Source
      ❱
      1. 9.7.1. Theory of Operation
      2. 9.7.2. Design Verification
        ❱
        1. 9.7.2.1. Testplan
      3. 9.7.3. Programmer's Guide
      4. 9.7.4. Hardware Interfaces
      5. 9.7.5. Registers
      6. 9.7.6. Device Interface Functions
      7. 9.7.7. Checklist
    8. 9.8. Flash Controller
      ❱
      1. 9.8.1. Theory of Operation
      2. 9.8.2. Design Verification
        ❱
        1. 9.8.2.1. Testplan
      3. 9.8.3. Programmer's Guide
      4. 9.8.4. Hardware Interfaces
      5. 9.8.5. Registers
      6. 9.8.6. Device Interface Functions
      7. 9.8.7. Checklist
    9. 9.9. GPIO
      ❱
      1. 9.9.1. Theory of Operation
      2. 9.9.2. Design Verification
        ❱
        1. 9.9.2.1. Testplan
      3. 9.9.3. Programmer's Guide
      4. 9.9.4. Hardware Interfaces
      5. 9.9.5. Registers
      6. 9.9.6. Device Interface Functions
      7. 9.9.7. Checklist
    10. 9.10. HMAC
      ❱
      1. 9.10.1. Theory of Operation
      2. 9.10.2. Design Verification
        ❱
        1. 9.10.2.1. Testplan
      3. 9.10.3. Programmer's Guide
      4. 9.10.4. Hardware Interfaces
      5. 9.10.5. Registers
      6. 9.10.6. Device Interface Functions
      7. 9.10.7. Checklist
    11. 9.11. I2C
      ❱
      1. 9.11.1. Theory of Operation
      2. 9.11.2. Design Verification
        ❱
        1. 9.11.2.1. Testplan
      3. 9.11.3. Programmer's Guide
      4. 9.11.4. Hardware Interfaces
      5. 9.11.5. Registers
      6. 9.11.6. Device Interface Functions
      7. 9.11.7. Checklist
    12. 9.12. Key Manager
      ❱
      1. 9.12.1. Theory of Operation
      2. 9.12.2. Design Verification
        ❱
        1. 9.12.2.1. Testplan
      3. 9.12.3. Programmer's Guide
      4. 9.12.4. Hardware Interfaces
      5. 9.12.5. Registers
      6. 9.12.6. Device Interface Functions
      7. 9.12.7. Checklist
    13. 9.13. KMAC
      ❱
      1. 9.13.1. Theory of Operation
      2. 9.13.2. Design Verification
        ❱
        1. 9.13.2.1. Testplan
      3. 9.13.3. Programmer's Guide
      4. 9.13.4. Hardware Interfaces
      5. 9.13.5. Registers
      6. 9.13.6. Device Interface Functions
      7. 9.13.7. Checklist
    14. 9.14. Life Cycle Controller
      ❱
      1. 9.14.1. Theory of Operation
      2. 9.14.2. Design Verification
        ❱
        1. 9.14.2.1. Testplan
      3. 9.14.3. Programmer's Guide
      4. 9.14.4. Hardware Interfaces
      5. 9.14.5. Registers
      6. 9.14.6. Device Interface Functions
      7. 9.14.7. Checklist
    15. 9.15. OTP Controller
      ❱
      1. 9.15.1. Theory of Operation
      2. 9.15.2. Design Verification
        ❱
        1. 9.15.2.1. Testplan
      3. 9.15.3. Programmer's Guide
      4. 9.15.4. Hardware Interfaces
      5. 9.15.5. Registers
      6. 9.15.6. Device Interface Functions
      7. 9.15.7. Checklist
    16. 9.16. Pattern Generator
      ❱
      1. 9.16.1. Theory of Operation
      2. 9.16.2. Design Verification
        ❱
        1. 9.16.2.1. Testplan
      3. 9.16.3. Programmer's Guide
      4. 9.16.4. Hardware Interfaces
      5. 9.16.5. Registers
      6. 9.16.6. Device Interface Functions
      7. 9.16.7. Checklist
    17. 9.17. Pinmux
      ❱
      1. 9.17.1. Theory of Operation
      2. 9.17.2. Design Verification
        ❱
        1. 9.17.2.1. Testplan
      3. 9.17.3. Programmer's Guide
      4. 9.17.4. Hardware Interfaces
      5. 9.17.5. Registers
      6. 9.17.6. Device Interface Functions
      7. 9.17.7. Checklist
    18. 9.18. Pulse Width Modulator
      ❱
      1. 9.18.1. Theory of Operation
      2. 9.18.2. Design Verification
        ❱
        1. 9.18.2.1. Testplan
      3. 9.18.3. Programmer's Guide
      4. 9.18.4. Hardware Interfaces
      5. 9.18.5. Registers
      6. 9.18.6. Device Interface Functions
      7. 9.18.7. Checklist
    19. 9.19. Power Management
      ❱
      1. 9.19.1. Theory of Operation
      2. 9.19.2. Design Verification
        ❱
        1. 9.19.2.1. Testplan
      3. 9.19.3. Programmer's Guide
      4. 9.19.4. Hardware Interfaces
      5. 9.19.5. Registers
      6. 9.19.6. Device Interface Functions
      7. 9.19.7. Checklist
    20. 9.20. ROM Control
      ❱
      1. 9.20.1. Theory of Operation
      2. 9.20.2. Design Verification
        ❱
        1. 9.20.2.1. Testplan
      3. 9.20.3. Programmer's Guide
      4. 9.20.4. Hardware Interfaces
      5. 9.20.5. Registers
      6. 9.20.6. Device Interface Functions
      7. 9.20.7. Checklist
    21. 9.21. Reset Manager
      ❱
      1. 9.21.1. Theory of Operation
      2. 9.21.2. Design Verification
        ❱
        1. 9.21.2.1. Testplan
      3. 9.21.3. Programmer's Guide
      4. 9.21.4. Hardware Interfaces
      5. 9.21.5. Registers
      6. 9.21.6. Device Interface Functions
      7. 9.21.7. Checklist
    22. 9.22. RISC-V Debug Manager
      ❱
      1. 9.22.1. Theory of Operation
      2. 9.22.2. Design Verification
        ❱
        1. 9.22.2.1. Testplan
      3. 9.22.3. Programmer's Guide
      4. 9.22.4. Hardware Interfaces
      5. 9.22.5. Registers
      6. 9.22.6. Checklist
    23. 9.23. SPI Device
      ❱
      1. 9.23.1. Theory of Operation
      2. 9.23.2. Design Verification
        ❱
        1. 9.23.2.1. Testplan
      3. 9.23.3. Programmer's Guide
      4. 9.23.4. Hardware Interfaces
      5. 9.23.5. Registers
      6. 9.23.6. Device Interface Functions
      7. 9.23.7. Checklist
    24. 9.24. SPI Host
      ❱
      1. 9.24.1. Theory of Operation
      2. 9.24.2. Design Verification
        ❱
        1. 9.24.2.1. Testplan
      3. 9.24.3. Programmer's Guide
      4. 9.24.4. Hardware Interfaces
      5. 9.24.5. Registers
      6. 9.24.6. Device Interface Functions
      7. 9.24.7. Checklist
    25. 9.25. SRAM Controller
      ❱
      1. 9.25.1. Theory of Operation
      2. 9.25.2. Design Verification
        ❱
        1. 9.25.2.1. Testplan
      3. 9.25.3. Programmer's Guide
      4. 9.25.4. Hardware Interfaces
      5. 9.25.5. Registers
      6. 9.25.6. Device Interface Functions
      7. 9.25.7. Checklist
    26. 9.26. System Reset Controller
      ❱
      1. 9.26.1. Theory of Operation
      2. 9.26.2. Design Verification
        ❱
        1. 9.26.2.1. Testplan
      3. 9.26.3. Hardware Interfaces
      4. 9.26.4. Registers
      5. 9.26.5. Device Interface Functions
      6. 9.26.6. Checklist
    27. 9.27. Timer
      ❱
      1. 9.27.1. Theory of Operation
      2. 9.27.2. Design Verification
        ❱
        1. 9.27.2.1. Testplan
      3. 9.27.3. Programmer's Guide
      4. 9.27.4. Hardware Interfaces
      5. 9.27.5. Registers
      6. 9.27.6. Device Interface Functions
      7. 9.27.7. Checklist
    28. 9.28. TL-UL Bus
      ❱
      1. 9.28.1. Design Verification
        ❱
        1. 9.28.1.1. Testplan
        2. 9.28.1.2. Protocol Checker
    29. 9.29. UART
      ❱
      1. 9.29.1. Theory of Operation
      2. 9.29.2. Design Verification
        ❱
        1. 9.29.2.1. Testplan
      3. 9.29.3. Programmer's Guide
      4. 9.29.4. Hardware Interfaces
      5. 9.29.5. Registers
      6. 9.29.6. Device Interface Functions
      7. 9.29.7. Checklist
    30. 9.30. USB 2.0
      ❱
      1. 9.30.1. Theory of Operation
      2. 9.30.2. Design Verification
        ❱
        1. 9.30.2.1. Testplan
      3. 9.30.3. Programmer's Guide
      4. 9.30.4. Suspending and Resuming
      5. 9.30.5. Hardware Interfaces
      6. 9.30.6. Registers
      7. 9.30.7. Device Interface Functions
      8. 9.30.8. Checklist
    31. 9.31. lowRISC Hardware Primitives
      ❱
      1. 9.31.1. Two Input Clock
      2. 9.31.2. Flash Wrapper
      3. 9.31.3. Keccak Permutation
      4. 9.31.4. Linear Feedback Shift Register
      5. 9.31.5. Packer
      6. 9.31.6. Packer FIFO
      7. 9.31.7. Present Scrambler
      8. 9.31.8. Prince Scrambler
      9. 9.31.9. SRAM Scrambler
      10. 9.31.10. Pseudo Random Number Generator
  13. 10. Common SystemVerilog and UVM Components
    ❱
    1. 10.1. ALERT_ESC Agent
    2. 10.2. Bus Params Package
    3. 10.3. Comportable IP Testbench Architecture
    4. 10.4. Common Interfaces
    5. 10.5. CSR Utils
    6. 10.6. CSRNG Agent
    7. 10.7. DV Library Classes
    8. 10.8. DV Utils
    9. 10.9. FLASH_PHY_PRIM Agent
    10. 10.10. I2C Agent
    11. 10.11. JTAG Agent
    12. 10.12. JTAG DMI Agent
    13. 10.13. JTAG RISCV Agent
    14. 10.14. KEY_SIDELOAD Agent
    15. 10.15. KMAC_APP Agent
    16. 10.16. Memory Backdoor Scoreboard
    17. 10.17. Memory Backdoor Utility
    18. 10.18. Memory Model
    19. 10.19. PATTGEN Agent
    20. 10.20. PUSH_PULL Agent
    21. 10.21. PWM Monitor
    22. 10.22. RNG Agent
    23. 10.23. Scoreboard
    24. 10.24. Simulation SRAM
    25. 10.25. SPI Agent
    26. 10.26. String Utils
    27. 10.27. Test Vectors
    28. 10.28. Tile Link Agent
    29. 10.29. UART Agent
    30. 10.30. USB20 Agent
  14. Software
  15. 11. Introduction
  16. 12. Build Software
  17. 13. Device Software
    ❱
    1. 13.1. Build & Test Rules
      ❱
      1. 13.1.1. FPGA Bitstreams
      2. 13.1.2. OTP Build and Test Infrastructure
    2. 13.2. Device Libraries
      ❱
      1. 13.2.1. DIF Library
        ❱
        1. 13.2.1.1. ADC Checklist
        2. 13.2.1.2. AES Checklist
        3. 13.2.1.3. Alert Handler Checklist
        4. 13.2.1.4. Always-On Timer Checklist
        5. 13.2.1.5. Clock Manager Checklist
        6. 13.2.1.6. CSRNG Checklist
        7. 13.2.1.7. EDN Checklist
        8. 13.2.1.8. Entropy Source Checklist
        9. 13.2.1.9. Flash Controller Checklist
        10. 13.2.1.10. GPIO Checklist
        11. 13.2.1.11. HMAC Checklist
        12. 13.2.1.12. I2C Checklist
        13. 13.2.1.13. Key Manager Checklist
        14. 13.2.1.14. KMAC Checklist
        15. 13.2.1.15. Lifecycle Checklist
        16. 13.2.1.16. OTBN Checklist
        17. 13.2.1.17. OTP Controller Checklist
        18. 13.2.1.18. Pattern Generator Checklist
        19. 13.2.1.19. Pin Multiplexer Checklist
        20. 13.2.1.20. PWM Checklist
        21. 13.2.1.21. Power Manager Checklist
        22. 13.2.1.22. ROM Checklist
        23. 13.2.1.23. Reset Manager Checklist
        24. 13.2.1.24. RV Core Ibex Checklist
        25. 13.2.1.25. PLIC Checklist
        26. 13.2.1.26. RV Timer Checklist
        27. 13.2.1.27. Sensor Controller Checklist
        28. 13.2.1.28. SPI Device Checklist
        29. 13.2.1.29. SPI Host Checklist
        30. 13.2.1.30. SRAM Controller Checklist
        31. 13.2.1.31. System Reset Controller Checklist
        32. 13.2.1.32. UART Checklist
        33. 13.2.1.33. USB Checklist
      2. 13.2.2. Top-Level Test Libraries
        ❱
        1. 13.2.2.1. On-Device Test Framework
      3. 13.2.3. OpenTitan Standard Library
        ❱
        1. 13.2.3.1. Freestanding C Headers
    3. 13.3. Silicon Creator Software
      ❱
      1. 13.3.1. Manufacturing Firmware
        ❱
        1. 13.3.1.1. Test Plan
      2. 13.3.2. ROM
        ❱
        1. 13.3.2.1. ROM Specification
        2. 13.3.2.2. Bootstrap
        3. 13.3.2.3. Memory Protection
        4. 13.3.2.4. E2E tests
        5. 13.3.2.5. Signing Keys
        6. 13.3.2.6. Signature Verification
        7. 13.3.2.7. Test Plan
        8. 13.3.2.8. Signoff Test Plan
        9. 13.3.2.9. Shutdown Specification
      3. 13.3.3. ROM_EXT
        ❱
        1. 13.3.3.1. ROM_EXT for Silicon Validation
      4. 13.3.4. Manifest Format
      5. 13.3.5. Boot Log
    4. 13.4. Top-Level Tests
      ❱
      1. 13.4.1. Manufacturer Test Hooks
      2. 13.4.2. Crypto Library Tests
      3. 13.4.3. Cryptotest
    5. 13.5. Silicon Validation
      ❱
      1. 13.5.1. Developer Guide
  18. 14. Host Software
    ❱
    1. 14.1. OpenTitanLib
    2. 14.2. OpenTitanTool
    3. 14.3. OpenTitanSession
    4. 14.4. OpenTitan Certificate Generator
    5. 14.5. Hardware Security Module (HSM) tool
      ❱
      1. 14.5.1. Requirements
      2. 14.5.2. Signing Guide
    6. 14.6. TPM2 Test Server
  19. Tooling
  20. 15. Tools Overview
  21. 16. Design-Related Tooling
  22. 17. dvsim
    ❱
    1. 17.1. Design Document
    2. 17.2. Testplanner
    3. 17.3. Glossary
  23. 18. fpvgen: Initial FPV Testbench Generation
  24. 19. reggen & regtool: Register Generator
    ❱
    1. 19.1. Setup and use of regtool
  25. 20. ralgen: FuseSoC UVM RAL Generator
  26. 21. uvmdvgen: Initial Testbench Auto-generation
  27. 22. tlgen: Crossbar Generation
  28. 23. ipgen: Generate IP Blocks from IP Templates
  29. 24. topgen: Top Generator
  30. 25. vendor: Vendoring In Tool
  31. 26. i2csvg: Generate SVGs of I2C Commands
  32. Contributing
  33. 27. Contributing
    ❱
    1. 27.1. Detailed Contribution Guide
    2. 27.2. Directory Structure
    3. 27.3. Contributing to Documentation
      ❱
      1. 27.3.1. An Example IP Block's Documentation
    4. 27.4. Continuous Intergration
    5. 27.5. Top-Level Design and Targets
    6. 27.6. GitHub Notes
    7. 27.7. Bazel Notes
    8. 27.8. Using the Container
  34. 28. Contributing to Hardware
    ❱
    1. 28.1. Comportability
    2. 28.2. Hardware Design
    3. 28.3. Design Methodology
    4. 28.4. Vendoring in Hardware
    5. 28.5. Linting
    6. 28.6. Synthesis Flow
  35. 29. Contributing to Verification
    ❱
    1. 29.1. Verification Methodology
    2. 29.2. Security Countermeasure Verification Framework
    3. 29.3. Assertions
  36. 30. Contributing to Software
    ❱
    1. 30.1. Device Interface Functions
    2. 30.2. Writing and Building Software for OTBN
  37. 31. Style Guides
    ❱
    1. 31.1. HJSON
    2. 31.2. Python
    3. 31.3. C & C++
    4. 31.4. Markdown
    5. 31.5. RISC-V Assembly
    6. 31.6. OTBN Assembly
    7. 31.7. Guidance for Volatile
  38. 32. Developing on an FPGA
    ❱
    1. 32.1. Get a Board
    2. 32.2. FPGA Reference Manual
    3. 32.3. Debugging with an ILA
  39. Project Governance
  40. 33. Introduction
  41. 34. Committers
  42. 35. RFC Process
  43. 36. Generalized Priority Definitions
  44. 37. OpenTitan Technical Committee
  45. 38. Hardware Development Stages
  46. 39. Signoff Checklist
  47. Security
  48. 40. Security
  49. 41. Cryptography Library
    ❱
    1. 41.1. API Documentation
  50. 42. Implementation Guidelines
    ❱
    1. 42.1. Secure Hardware Design Guidelines
    2. 42.2. Reset vs. Non-Reset Flops
  51. 43. Logical Security Model
  52. 44. Security Model Specification
    ❱
    1. 44.1. Device Attestation
    2. 44.2. Device Life Cycle
    3. 44.3. Device Provisioning
    4. 44.4. Firmware Update
    5. 44.5. Identities and Root Keys
    6. 44.6. Ownership Transfer
    7. 44.7. Secure Boot
  53. 45. Lightweight Threat Model
  54. Use Cases
  55. 46. Use Cases
  56. 47. Platform Integrity Module
  57. 48. Trusted Platform Module
  58. 49. Universal 2nd-Factor Security Key
  59. Rust for C Developers
  60. 50. Rust for Embedded C Programmers
  61. Appendix
  62. 51. Glossary
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Programmer’s Guide

Device Interface Functions (DIFs)

  • Device Interface Functions