Registers

A number of memory-mapped registers are available to control Ibex-related functionality that’s specific to OpenTitan.

Summary

NameOffsetLengthDescription
rv_core_ibex.ALERT_TEST0x04Alert Test Register
rv_core_ibex.SW_RECOV_ERR0x44Software recoverable error
rv_core_ibex.SW_FATAL_ERR0x84Software fatal error
rv_core_ibex.IBUS_REGWEN_00xc4Ibus address control regwen.
rv_core_ibex.IBUS_REGWEN_10x104Ibus address control regwen.
rv_core_ibex.IBUS_ADDR_EN_00x144Enable Ibus address matching
rv_core_ibex.IBUS_ADDR_EN_10x184Enable Ibus address matching
rv_core_ibex.IBUS_ADDR_MATCHING_00x1c4Matching region programming for ibus.
rv_core_ibex.IBUS_ADDR_MATCHING_10x204Matching region programming for ibus.
rv_core_ibex.IBUS_REMAP_ADDR_00x244The remap address after a match has been made.
rv_core_ibex.IBUS_REMAP_ADDR_10x284The remap address after a match has been made.
rv_core_ibex.DBUS_REGWEN_00x2c4Dbus address control regwen.
rv_core_ibex.DBUS_REGWEN_10x304Dbus address control regwen.
rv_core_ibex.DBUS_ADDR_EN_00x344Enable dbus address matching
rv_core_ibex.DBUS_ADDR_EN_10x384Enable dbus address matching
rv_core_ibex.DBUS_ADDR_MATCHING_00x3c4See !!IBUS_ADDR_MATCHING_0 for detailed description.
rv_core_ibex.DBUS_ADDR_MATCHING_10x404See !!IBUS_ADDR_MATCHING_0 for detailed description.
rv_core_ibex.DBUS_REMAP_ADDR_00x444See !!IBUS_REMAP_ADDR_0 for a detailed description.
rv_core_ibex.DBUS_REMAP_ADDR_10x484See !!IBUS_REMAP_ADDR_0 for a detailed description.
rv_core_ibex.NMI_ENABLE0x4c4Enable mask for NMI.
rv_core_ibex.NMI_STATE0x504Current NMI state
rv_core_ibex.ERR_STATUS0x544error status
rv_core_ibex.RND_DATA0x584Random data from EDN
rv_core_ibex.RND_STATUS0x5c4Status of random data in !!RND_DATA
rv_core_ibex.FPGA_INFO0x604FPGA build timestamp info.
rv_core_ibex.DV_SIM_WINDOW0x8032Exposed tlul window for DV only purposes.

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3wo0x0recov_hw_errWrite 1 to trigger one alert event of this kind.
2wo0x0fatal_hw_errWrite 1 to trigger one alert event of this kind.
1wo0x0recov_sw_errWrite 1 to trigger one alert event of this kind.
0wo0x0fatal_sw_errWrite 1 to trigger one alert event of this kind.

SW_RECOV_ERR

Software recoverable error

  • Offset: 0x4
  • Reset default: 0x9
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw0x9VALSoftware recoverable alert. When set to any value other than kMultiBitBool4False, a recoverable alert is sent. Once the alert is sent, the field is then reset to kMultiBitBool4False.

SW_FATAL_ERR

Software fatal error

  • Offset: 0x8
  • Reset default: 0x9
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw1s0x9VALSoftware fatal alert. When set to any value other than kMultiBitBool4False, a fatal alert is sent. Note, this field once cleared cannot be set and will continuously cause alert events.

IBUS_REGWEN

Ibus address control regwen.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
IBUS_REGWEN_00xc
IBUS_REGWEN_10x10

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1EN

IBUS_REGWEN . EN

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0lockedAddress controls can no longer be configured until next reset.
0x1enabledAddress controls can still be configured.

IBUS_ADDR_EN

Enable Ibus address matching

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
IBUS_ADDR_EN_00x14
IBUS_ADDR_EN_10x18

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0ENEnable ibus address matching.

IBUS_ADDR_MATCHING

Matching region programming for ibus.

The value programmed is done at power-of-2 alignment. For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.

The value programmed can be determined from the translation granule. Assume the user wishes to translate a specific 64KB block to a different address: 64KB has a hex value of 0x10000. Subtract 1 from this value and then right shift by one to obtain 0x7FFF. This value is then logically OR’d with the upper address bits that would select which 64KB to translate.

In this example, the user wishes to translate the 0x8000-th 64KB block. The value programmed is then 0x8000_7FFF.

If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
IBUS_ADDR_MATCHING_00x1c
IBUS_ADDR_MATCHING_10x20

Fields

BitsTypeResetNameDescription
31:0rw0x0VALMatching region value

IBUS_REMAP_ADDR

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

For example, if the translation region is 64KB, the remapped address applies only to the upper address bits that select which 64KB to be translated.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
IBUS_REMAP_ADDR_00x24
IBUS_REMAP_ADDR_10x28

Fields

BitsTypeResetNameDescription
31:0rw0x0VALRemap addr value

DBUS_REGWEN

Dbus address control regwen.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
DBUS_REGWEN_00x2c
DBUS_REGWEN_10x30

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1EN

DBUS_REGWEN . EN

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

ValueNameDescription
0x0lockedAddress controls can no longer be configured until next reset.
0x1enabledAddress controls can still be configured.

DBUS_ADDR_EN

Enable dbus address matching

  • Reset default: 0x0
  • Reset mask: 0x1

Instances

NameOffset
DBUS_ADDR_EN_00x34
DBUS_ADDR_EN_10x38

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0ENEnable dbus address matching.

DBUS_ADDR_MATCHING

See IBUS_ADDR_MATCHING_0 for detailed description.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
DBUS_ADDR_MATCHING_00x3c
DBUS_ADDR_MATCHING_10x40

Fields

BitsTypeResetNameDescription
31:0rw0x0VALMatching region value

DBUS_REMAP_ADDR

See IBUS_REMAP_ADDR_0 for a detailed description.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
DBUS_REMAP_ADDR_00x44
DBUS_REMAP_ADDR_10x48

Fields

BitsTypeResetNameDescription
31:0rw0x0VALRemap addr value

NMI_ENABLE

Enable mask for NMI. Once an enable mask is set, it cannot be disabled.

  • Offset: 0x4c
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw1s0x0WDOG_ENEnable mask for watchdog NMI
0rw1s0x0ALERT_ENEnable mask for alert NMI

NMI_STATE

Current NMI state

  • Offset: 0x50
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw1c0x0WDOGCurrent state for watchdog NMI
0rw1c0x0ALERTCurrent state for alert NMI

ERR_STATUS

error status

  • Offset: 0x54
  • Reset default: 0x0
  • Reset mask: 0x701

Fields

BitsTypeResetNameDescription
31:11Reserved
10rw1c0x0RECOV_CORE_ERRrv_core_ibex detected a recoverable internal error (alert_minor from Ibex seen)
9rw1c0x0FATAL_CORE_ERRrv_core_ibex detected a fatal internal error (alert_major_internal_o from Ibex seen)
8rw1c0x0FATAL_INTG_ERRrv_core_ibex detected a response integrity error
7:1Reserved
0rw1c0x0REG_INTG_ERRrv_core_ibex_peri detected a register transmission integrity error

RND_DATA

Random data from EDN

  • Offset: 0x58
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0ro0x0DATA

RND_DATA . DATA

Random bits taken from the EDN. RND_STATUS.RND_DATA_VALID indicates if this data is valid. When valid, reading from this register invalidates the data and requests new data from the EDN. The register becomes valid again when the EDN provides new data. When invalid the register value will read as 0x0 with an EDN request for new data pending. Upon reset the data will be invalid with a new EDN request pending.

RND_STATUS

Status of random data in RND_DATA

  • Offset: 0x5c
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1ro0x0RND_DATA_FIPSWhen RND_STATUS.RND_DATA_VALID is 1, this bit indicates whether RND_DATA is fips quality. When RND_STATUS.RND_DATA_VALID is 0, this bit has no meaning.
0ro0x0RND_DATA_VALIDWhen set, the data in RND_DATA is valid. When clear an EDN request for new data for RND_DATA is pending.

FPGA_INFO

FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0.

  • Offset: 0x60
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x0VALFPGA build timestamp information.

DV_SIM_WINDOW

Exposed tlul window for DV only purposes.

  • Word Aligned Offset Range: 0x80to0x9c
  • Size (words): 8
  • Access: rw
  • Byte writes are supported.