Pinmux Checklist

This checklist is for Hardware Stage transitions for the Pinmux peripheral. All checklist items refer to the content in the Checklist.

Design Checklist

D1

TypeItemResolutionNote/Collaterals
DocumentationSPEC_COMPLETEDonePinmux spec
DocumentationCSR_DEFINEDDone
RTLCLKRST_CONNECTEDDone
RTLIP_TOPDone
RTLIP_INSTANTIABLEDone
RTLPHYSICAL_MACROS_DEFINED_80Done
RTLFUNC_IMPLEMENTEDDone
RTLASSERT_KNOWN_ADDEDDonePrimary I/Os are exempted from KNOWN assertions since the chip-level testbench may drive X’es onto some of these signals.
Code QualityLINT_SETUPDone

D2

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURESDone
DocumentationBLOCK_DIAGRAMDone
DocumentationDOC_INTERFACEDone
DocumentationDOC_INTEGRATION_GUIDEWaivedThis checklist item has been added retrospectively.
DocumentationMISSING_FUNCDone
DocumentationFEATURE_FROZENDone
RTLFEATURE_COMPLETEDone
RTLPORT_FROZENDone
RTLARCHITECTURE_FROZENDone
RTLREVIEW_TODODone
RTLSTYLE_XDone
RTLCDC_SYNCMACRODone
Code QualityLINT_PASSDone
Code QualityCDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_SETUPWaivedNo block-level flow available - waived to top-level signoff.
Code QualityAREA_CHECKDone
Code QualityTIMING_CHECKDone
SecuritySEC_CM_DOCUMENTEDN/A

D2S

TypeItemResolutionNote/Collaterals
SecuritySEC_CM_ASSETS_LISTEDDone
SecuritySEC_CM_IMPLEMENTEDDone
SecuritySEC_CM_RND_CNSTN/A
SecuritySEC_CM_NON_RESET_FLOPSN/A
SecuritySEC_CM_SHADOW_REGSN/A
SecuritySEC_CM_RTL_REVIEWEDN/A
SecuritySEC_CM_COUNCIL_REVIEWEDN/AThis block only contains the bus-integrity CM.

D3

TypeItemResolutionNote/Collaterals
DocumentationNEW_FEATURES_D3Done
RTLTODO_COMPLETEDone
Code QualityLINT_COMPLETEDone
Code QualityCDC_COMPLETEWaivedNo block-level flow available - waived to top-level signoff.
Code QualityRDC_COMPLETEWaivedNo block-level flow available - waived to top-level signoff.
ReviewREVIEW_RTLDoneNote that the USB wakeup detector submodule u_usbdev_aon_wake is excluded in this review as it will be reviewed as part of the USB sign-off process.
ReviewREVIEW_DELETED_FFWaivedNo block-level flow available - waived to top-level signoff.
ReviewREVIEW_SW_CHANGEDone
ReviewREVIEW_SW_ERRATADone
ReviewReviewer(s)Donemsf@ tjaychen@ chencindy@ awill@
ReviewSignoff dateDone2022-08-17

Verification Checklist

V1

TypeItemResolutionNote/Collaterals
DocumentationDV_DOC_DRAFT_COMPLETEDDone
DocumentationTESTPLAN_COMPLETEDDone
TestbenchTB_TOP_CREATEDDone
TestbenchPRELIMINARY_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_CREATEDN/A
TestbenchSIM_RAL_MODEL_GEN_AUTOMATEDN/AThis block uses FPV
TestbenchCSR_CHECK_GEN_AUTOMATEDDone
TestbenchTB_GEN_AUTOMATEDDone
TestsSIM_SMOKE_TEST_PASSINGN/A
TestsSIM_CSR_MEM_TEST_SUITE_PASSINGN/A
TestsFPV_MAIN_ASSERTIONS_PROVENDone
Tool SetupSIM_ALT_TOOL_SETUPN/A
RegressionSIM_SMOKE_REGRESSION_SETUPN/A
RegressionSIM_NIGHTLY_REGRESSION_SETUPN/A
RegressionFPV_REGRESSION_SETUPDone
CoverageSIM_COVERAGE_MODEL_ADDEDN/A
Code QualityTB_LINT_SETUPDone
IntegrationPRE_VERIFIED_SUB_MODULES_V1Waivedusbdev will be verified by a separate DV testbench.
ReviewDESIGN_SPEC_REVIEWEDNot Started
ReviewTESTPLAN_REVIEWEDDone
ReviewSTD_TEST_CATEGORIES_PLANNEDN/A
ReviewV2_CHECKLIST_SCOPEDDone

V2

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V2Done
DocumentationDV_DOC_COMPLETEDDone
TestbenchFUNCTIONAL_COVERAGE_IMPLEMENTEDDone
TestbenchALL_INTERFACES_EXERCISEDDone
TestbenchALL_ASSERTION_CHECKS_ADDEDDone
TestbenchSIM_TB_ENV_COMPLETEDN/A
TestsSIM_ALL_TESTS_PASSINGN/A
TestsFPV_ALL_ASSERTIONS_WRITTENDone
TestsFPV_ALL_ASSUMPTIONS_REVIEWEDDone
TestsSIM_FW_SIMULATEDN/A
RegressionSIM_NIGHTLY_REGRESSION_V2N/A
CoverageSIM_CODE_COVERAGE_V2N/A
CoverageSIM_FUNCTIONAL_COVERAGE_V2N/A
CoverageFPV_CODE_COVERAGE_V2Done
CoverageFPV_COI_COVERAGE_V2Done
IntegrationPRE_VERIFIED_SUB_MODULES_V2Waivedusbdev will be verified by a separate DV testbench.
IssuesNO_HIGH_PRIORITY_ISSUES_PENDINGDone
IssuesALL_LOW_PRIORITY_ISSUES_ROOT_CAUSEDDone
ReviewDV_DOC_TESTPLAN_REVIEWEDDone
ReviewV3_CHECKLIST_SCOPEDDone

V2S

TypeItemResolutionNote/Collaterals
DocumentationSEC_CM_TESTPLAN_COMPLETEDDoneThe testplan has been generated, but there is no DV environment to test these CMs. The CMs (bus integrity and LC gated TAP muxing/demuxing) are tested with the FPV testbench instead.
Tests[FPV_SEC_CM_PROVEN][]DoneThe SEC_CM behavior has been proven with formal.
TestsSIM_SEC_CM_VERIFIEDN/AThis module only has an FPV testbench.
CoverageSIM_COVERAGE_REVIEWEDN/AThis module only has an FPV testbench.
ReviewSEC_CM_DV_REVIEWEDDone

V3

TypeItemResolutionNote/Collaterals
DocumentationDESIGN_DELTAS_CAPTURED_V3Not Started
TestsX_PROP_ANALYSIS_COMPLETEDNot Started
TestsFPV_ASSERTIONS_PROVEN_AT_V3Not Started
RegressionSIM_NIGHTLY_REGRESSION_AT_V3Not Started
CoverageSIM_CODE_COVERAGE_AT_100Not Started
CoverageSIM_FUNCTIONAL_COVERAGE_AT_100Not Started
CoverageFPV_CODE_COVERAGE_AT_100Not Started
CoverageFPV_COI_COVERAGE_AT_100Not Started
Code QualityALL_TODOS_RESOLVEDNot Started
Code QualityNO_TOOL_WARNINGS_THROWNNot Started
Code QualityTB_LINT_COMPLETENot Started
IntegrationPRE_VERIFIED_SUB_MODULES_V3Not Started
IssuesNO_ISSUES_PENDINGNot Started
ReviewReviewer(s)Not Started
ReviewSignoff dateNot Started