Testplan

Testpoints

Stage V1 Testpoints

`wake_up`

Test: otp_ctrl_wake_up

Wake_up test walks through otp_ctrl’s power-on initialization, read, program, and digest functionalities.

drive pwrmgr’s request pin to trigger OTP initialization after reset, check status after OTP initialization
write all-ones to a random address within OTP partition 0, wait until this operation completes
read out the random selected write address, check if the readout value is all-ones
trigger a digest calculation for a Software partition, check if the OtpError interrupt is set
trigger a digest calculation for a non-software partition, expect operation completes without the OtpError interrupt
read out secrets through the hardware interfaces

`smoke`

Test: otp_ctrl_smoke

OTP_CTRL smoke test provisions and locks partitions.

drive pwrmgr’s request pin to trigger OTP initialization after reset, check status after OTP initialization
randomly read out keys pertaining to key_manager, flash, sram, otbn
randomly issue LC program request
write random values to random addresses within each OTP partition
read out the random selected write addresses, check if the readout values are expected
during read and write operations, check if direct_access_regwen is correctly set by HW
perform a system-level reset and check corresponding CSRs are set correctly
lock all partitions except life_cycle by triggering digest calculations
read back and verify the digest
perform a system-level reset to verify the corresponding CSRs exposing the digests have been populated

Checks:

Assertion checks to ensure vendor specific I/Os: otp_vendor_test_status_o, otp_vendor_test_ctrl_i, cio_test_o, and cio_test_en_o are connected currently with lc_dft_en_i On and Off.

`csr_hw_reset`

Test: otp_ctrl_csr_hw_reset

Verify the reset values as indicated in the RAL specification.

Write all CSRs with a random value.
Apply reset to the DUT as well as the RAL model.
Read each CSR and compare it against the reset value. it is mandatory to replicate this test for each reset that affects all or a subset of the CSRs.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_rw`

Test: otp_ctrl_csr_rw

Verify accessibility of CSRs as indicated in the RAL specification.

Loop through each CSR to write it with a random value.
Read the CSR back and check for correctness while adhering to its access policies.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_bit_bash`

Test: otp_ctrl_csr_bit_bash

Verify no aliasing within individual bits of a CSR.

Walk a 1 through each CSR by flipping 1 bit at a time.
Read the CSR back and check for correctness while adhering to its access policies.
This verify that writing a specific bit within the CSR did not affect any of the other bits.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_aliasing`

Test: otp_ctrl_csr_aliasing

Verify no aliasing within the CSR address space.

Loop through each CSR to write it with a random value
Shuffle and read ALL CSRs back.
All CSRs except for the one that was written in this iteration should read back the previous value.
The CSR that was written in this iteration is checked for correctness while adhering to its access policies.
It is mandatory to run this test for all available interfaces the CSRs are accessible from.
Shuffle the list of CSRs first to remove the effect of ordering.

`csr_mem_rw_with_rand_reset`

Test: otp_ctrl_csr_mem_rw_with_rand_reset

Verify random reset during CSR/memory access.

Run csr_rw sequence to randomly access CSRs
If memory exists, run mem_partial_access in parallel with csr_rw
Randomly issue reset and then use hw_reset sequence to check all CSRs are reset to default value
It is mandatory to run this test for all available interfaces the CSRs are accessible from.

`regwen_csr_and_corresponding_lockable_csr`

Tests:

otp_ctrl_csr_rw
otp_ctrl_csr_aliasing

Verify regwen CSR and its corresponding lockable CSRs.

Randomly access all CSRs
Test when regwen CSR is set, its corresponding lockable CSRs become read-only registers

Note:

If regwen CSR is HW read-only, this feature can be fully tested by common CSR tests - csr_rw and csr_aliasing.
If regwen CSR is HW updated, a separate test should be created to test it.

This is only applicable if the block contains regwen and locakable CSRs.

`mem_walk`

Test: otp_ctrl_mem_walk

Verify accessibility of all memories in the design.

Run the standard UVM mem walk sequence on all memories in the RAL model.
It is mandatory to run this test from all available interfaces the memories are accessible from.

`mem_partial_access`

Test: otp_ctrl_mem_partial_access

Verify partial-accessibility of all memories in the design.

Do partial reads and writes into the memories and verify the outcome for correctness.
Also test outstanding access on memories

Stage V2 Testpoints

`dai_access_partition_walk`

Test: otp_ctrl_partition_walk

Similar to UVM’s memory walk test, this test ensures every address in each partition can be accessed successfully via DAI and TLUL interfacs according to its access policy.

`init_fail`

Test: otp_ctrl_init_fail

Based on OTP_CTRL smoke test, this test creates OTP_CTRL’s initialization failure:

write and read OTP memory via DAI interface
randomly issue DAI digest command to lock HW partitions
keep writing to OTP memory via DAI interface without asserting reset
if digests are not locked, backdoor inject ECC correctable or uncorrectable errors
issue reset and power initialization
if the injected errors are all correctable errors, disable the lc_bypass_chk_en after LC program request to create an LC partition check failure

If fatal error is triggered, this test will check:

OTP initialization failure triggers fatal alert
status, intr_state, err_code CSRs reflect correct fatal error

If OTP initialization finished without any fatal error, this test will check:

OTP initialization finishes with power init output goes to 1
status, intr_state, err_code CSRs reflect ECC correctable error

`partition_check`

Tests:

otp_ctrl_check_fail
otp_ctrl_background_chks

Randomly program the partition check related CSRs including:

check_timeout
integrity_check_period
consistency_check_period
check_trigger

Create a failure scenario by randomly picking one of these three methods:

inject ECC errors into the OTP macro via backdoor
set the check_timeout CSR with a very small value
write to a random OTP partition after digest is issued but before reset is asserted

Checks:

the corresponding alerts are triggered
the error_code register is set correctly Note that due to limited simulation time, for background checks, this test only write random value that is less than 20 to the check period.

`regwen_during_otp_init`

Test: otp_ctrl_regwen

The direct_access_regwen is a RO register which controls the write-enable of other reigsters. It is not verified by the common CSR tests. HW sets it to 0 when the DAI interface is busy.

Stimulus and checks:

randomly read direct_access_regwen and verify that it returns 0 during OTP initialization
verify that the writes to the registers controlled by it do not go through during OTP initialization

This test will cover two methods of locking read and write: digest calculation and CSR write. After locking the partitions, issue read or program sequences and check if the operations are locked correctly, and check if the AccessError is set.

`interface_key_check`

Test: otp_ctrl_parallel_key_req

OTP_CTRL will generate keys to flash, sram, and otbn upon their requests. Based on the DAI access sequence, this test will run key requests sequence in parallel, and check if correct keys are generated.

`lc_interactions`

Tests:

otp_ctrl_parallel_lc_req
otp_ctrl_parallel_lc_esc

Verify the procotols between OTP_CTRL and LC_CTRL. Based on the DAI access sequence, run the following sequences in parallel:

request a LC state transition via the programming interface
enable the lc_escalation_en signal

Checks:

if the LC program request has AccessError, check the LC program response sets the error bit to 1
if lc_escalation_en is enabled, verify that alert is triggered and OTP_CTRL entered terminal state

`otp_dai_errors`

Test: otp_ctrl_dai_errs

Based on the otp_dai_lock test, this test will randomly run the following OTP errors:

DAI interface writes non-blank OTP address
DAI interface accesses LC partition
DAI interface writes HW digests
DAI interface writes non-empty memory

Checks:

err_code and status CSRs
otp_error interrupt

`otp_macro_errors`

Test: otp_ctrl_macro_errs

Randomly run the following OTP errors:

MacroError
MacroEccCorrError
MacroEccUncorrError

Checks:

err_code and status CSRs
otp_error interrupt
if the error is unrecoverable, verify that alert is triggered and OTP_CTRL entered terminal state

`test_access`

Test: otp_ctrl_test_access

This test checks if the test access to OTP macro is connected correctly.

Stimulus and Checks:

Write and check read results from the prim_tl_i/o.
Ensure no error or alert occurs from DUT.

`stress_all`

Test: otp_ctrl_stress_all

combine above sequences in one test to run sequentially, except csr sequence
randomly add reset between each sequence

`intr_test`

Test: otp_ctrl_intr_test

Verify common intr_test CSRs that allows SW to mock-inject interrupts.

Enable a random set of interrupts by writing random value(s) to intr_enable CSR(s).
Randomly “turn on” interrupts by writing random value(s) to intr_test CSR(s).
Read all intr_state CSR(s) back to verify that it reflects the same value as what was written to the corresponding intr_test CSR.
Check the cfg.intr_vif pins to verify that only the interrupts that were enabled and turned on are set.
Clear a random set of interrupts by writing a randomly value to intr_state CSR(s).
Repeat the above steps a bunch of times.

`alert_test`

Test: otp_ctrl_alert_test

Verify common alert_test CSR that allows SW to mock-inject alert requests.

Enable a random set of alert requests by writing random value to alert_test CSR.
Check each alert_tx.alert_p pin to verify that only the requested alerts are triggered.
During alert_handshakes, write alert_test CSR again to verify that: If alert_test writes to current ongoing alert handshake, the alert_test request will be ignored. If alert_test writes to current idle alert handshake, a new alert_handshake should be triggered.
Wait for the alert handshakes to finish and verify alert_tx.alert_p pins all sets back to 0.
Repeat the above steps a bunch of times.

`tl_d_oob_addr_access`

Test: otp_ctrl_tl_errors

Access out of bounds address and verify correctness of response / behavior

`tl_d_illegal_access`

Test: otp_ctrl_tl_errors

Drive unsupported requests via TL interface and verify correctness of response / behavior. Below error cases are tested bases on the TLUL spec

TL-UL protocol error cases
- invalid opcode
- some mask bits not set when opcode is PutFullData
- mask does not match the transfer size, e.g. a_address = 0x00, a_size = 0, a_mask = 'b0010
- mask and address misaligned, e.g. a_address = 0x01, a_mask = 'b0001
- address and size aren’t aligned, e.g. a_address = 0x01, a_size != 0
- size is greater than 2
OpenTitan defined error cases
- access unmapped address, expect d_error = 1
- write a CSR with unaligned address, e.g. a_address[1:0] != 0
- write a CSR less than its width, e.g. when CSR is 2 bytes wide, only write 1 byte
- write a memory with a_mask != '1 when it doesn’t support partial accesses
- read a WO (write-only) memory
- write a RO (read-only) memory
- write with instr_type = True

`tl_d_outstanding_access`

Tests:

otp_ctrl_csr_hw_reset
otp_ctrl_csr_rw
otp_ctrl_csr_aliasing
otp_ctrl_same_csr_outstanding

Drive back-to-back requests without waiting for response to ensure there is one transaction outstanding within the TL device. Also, verify one outstanding when back- to-back accesses are made to the same address.

`tl_d_partial_access`

Tests:

otp_ctrl_csr_hw_reset
otp_ctrl_csr_rw
otp_ctrl_csr_aliasing
otp_ctrl_same_csr_outstanding

Access CSR with one or more bytes of data. For read, expect to return all word value of the CSR. For write, enabling bytes should cover all CSR valid fields.

Stage V2S Testpoints

`sec_cm_additional_check`

Test: otp_ctrl_sec_cm

Verify the outcome of injecting faults to security countermeasures.

Stimulus: As mentioned in prim_count_check, prim_fsm_check and prim_double_lfsr_check.

Checks:

Check the value of status register according to where the fault is injected.
Check OTP_CTRL is locked after the fatal fault injection by trying to access OTP_CTRL via dai, kdi, and lci interfaces.

`tl_intg_err`

Tests:

otp_ctrl_tl_intg_err
otp_ctrl_sec_cm

Verify that the data integrity check violation generates an alert.

Randomly inject errors on the control, data, or the ECC bits during CSR accesses. Verify that triggers the correct fatal alert.
Inject a fault at the onehot check in u_reg.u_prim_reg_we_check and verify the corresponding fatal alert occurs

`prim_count_check`

Test: otp_ctrl_sec_cm

Verify that violating prim_count counter properties generate a fatal alert.

Stimulus:

At the falling edge (non-active edge), force the counter to a different value than expected.
Randomly force the counter back to a normal value to ensure the error is latched and won’t go away until reset.
Within the next few cycles, the violation of hardened counter property should generate a fatal alert.
Repeat for ALL prim_count instances in the DUT.

Checks:

Check that fatal alert is triggered.
Check that err_code/fault_status is updated correctly and preserved until reset.
Verify any operations that follow fail (as applicable).

`prim_fsm_check`

Test: otp_ctrl_sec_cm

Verify that entering to an undefined state generates a fatal alert.

Stimulus:

Backdoor force the FSM to any of the undefined values.
Randomly force the FSM back to a defined state to ensure the error is latched and won’t go away until reset.
Within the next few cycles, the FSM landing in an invalid state should trigger a fatal alert.
Repeat for ALL prim_fsm instances in the DUT.

Checks:

Check that fatal alert is triggered.
Check that err_code/fault_status is updated correctly and preserved until reset.
Verify any operations that follow fail (as applicable).

`sec_cm_dai_fsm_local_esc`

Tests:

otp_ctrl_parallel_lc_esc
otp_ctrl_sec_cm

Verify the countermeasure(s) DAI.FSM.LOCAL_ESC.

`sec_cm_lci_fsm_local_esc`

Test: otp_ctrl_parallel_lc_esc

Verify the countermeasure(s) LCI.FSM.LOCAL_ESC.

`sec_cm_kdi_fsm_local_esc`

Test: otp_ctrl_parallel_lc_esc

Verify the countermeasure(s) KDI.FSM.LOCAL_ESC.

`sec_cm_part_fsm_local_esc`

Tests:

otp_ctrl_parallel_lc_esc
otp_ctrl_macro_errs

Verify the countermeasure(s) PART.FSM.LOCAL_ESC.

`sec_cm_scrmbl_fsm_local_esc`

Test: otp_ctrl_parallel_lc_esc

Verify the countermeasure(s) SCRMBL.FSM.LOCAL_ESC.

`sec_cm_timer_fsm_local_esc`

Tests:

otp_ctrl_parallel_lc_esc
otp_ctrl_sec_cm

Verify the countermeasure(s) TIMER.FSM.LOCAL_ESC.

`sec_cm_dai_fsm_global_esc`

Tests:

otp_ctrl_parallel_lc_esc
otp_ctrl_sec_cm

Verify the countermeasure(s) DAI.FSM.GLOBAL_ESC.

`sec_cm_lci_fsm_global_esc`

Test: otp_ctrl_parallel_lc_esc

Verify the countermeasure(s) LCI.FSM.GLOBAL_ESC.

`sec_cm_kdi_fsm_global_esc`

Test: otp_ctrl_parallel_lc_esc

Verify the countermeasure(s) KDI.FSM.GLOBAL_ESC.

`sec_cm_part_fsm_global_esc`

Tests:

otp_ctrl_parallel_lc_esc
otp_ctrl_macro_errs

Verify the countermeasure(s) PART.FSM.GLOBAL_ESC.

`sec_cm_scrmbl_fsm_global_esc`

Test: otp_ctrl_parallel_lc_esc

Verify the countermeasure(s) SCRMBL.FSM.GLOBAL_ESC.

`sec_cm_timer_fsm_global_esc`

Tests:

otp_ctrl_parallel_lc_esc
otp_ctrl_sec_cm

Verify the countermeasure(s) MACRO.MEM.INTEGRITY.

`sec_cm_macro_mem_cm`

Test: N/A

Verify the countermeasure(s) MACRO.MEM.CM.

Stage V3 Testpoints

`otp_ctrl_low_freq_read`

Test: otp_ctrl_low_freq_read

This test checks if OTP’s read operation can operate successfully in a low clock frequency before the clock is calibrated.

Stimulus and Checks:

Configure OTP_CTRL’s clock to 6MHz low frequency.
Backdoor write OTP memory.
Use DAI access to read each memory address and compare if the value is correct.
If DAI address is in a SW partition, read and check again via TLUL interface.

`stress_all_with_rand_reset`

Test: otp_ctrl_stress_all_with_rand_reset

This test runs 3 parallel threads - stress_all, tl_errors and random reset. After reset is asserted, the test will read and check all valid CSR registers.

Covergroups

buf_err_code_cg

This is an array of covergroups to cover all applicable error codes in five buffered partitions.

csr_rd_after_alert_cg

Covers if the following CSRs are being read and the value is checked in scoreboard after any fatal alert is triggered:

unbuffered partitions’ digest CSRs
HW partition’s digest CSRs
secrets partitions’ digest CSRs
direct_access read data CSRs
status CSR
error_code CSR

dai_access_secret2_cg

Covers whether lc_creator_seed_sw_rw_en is On during any DAI accesses.

dai_err_code_cg

Covers all applicable error codes in DAI, and cross each error code with all 7 partitions.

flash_addr_req_condition_cg

Covers the following conditions when lc_escalation_en is On:

whether any key requests is in progress
whether DAI interface is busy
whether lc_esc_en is On

flash_data_req_condition_cg

Covers the following conditions when lc_escalation_en is On:

whether any key requests is in progress
whether DAI interface is busy
whether lc_esc_en is On

flash_req_cg

Covers whether secret1 partition is locked during flash data or address request.

issue_checks_after_alert_cg

Covers if sequence issued various OTP_CTRL’s background checks after any fatal alert is triggered.

keymgr_o_cg

Covers the following conditions when scoreboard checks keymgr_o value:

whether secret2 partition is locked
whether lc_seed_hw_rd_en_i is On

lc_esc_en_condition_cg

Covers the following conditions when lc_escalation_en is On:

whether any key requests is in progress
whether LC program reqeust is in progress
whether DAI interface is busy

lc_prog_cg

Covers whether the error bit is set during LC program request.

lc_prog_req_condition_cg

Covers the following conditions when lc_escalation_en is On:

whether any key requests is in progress
whether DAI interface is busy
whether lc_esc_en is On

lci_err_code_cg

Covers all applicable error codes in LCI.

otbn_req_cg

Covers whether secret1 partition is locked during otbn key request.

otbn_req_condition_cg

Covers the following conditions when lc_escalation_en is On:

whether any key requests is in progress
whether DAI interface is busy
whether lc_esc_en is On

power_on_cg

Covers the following conditions when OTP_CTRL finishes power-on initialization:

whether lc_escalation_en is On
whether any partition (except life cycle partition) is locked

regwen_val_when_new_value_written_cg

Cover each lockable reg field with these 2 cases:

When regwen = 1, a different value is written to the lockable CSR field, and a read occurs after that.
When regwen = 0, a different value is written to the lockable CSR field, and a read occurs after that.

This is only applicable if the block contains regwen and locakable CSRs.

req_dai_access_after_alert_cg

Covers if sequence issued various DAI requests after any fatal alert is triggered.

sram_0_req_condition_cg

Covers the following conditions when lc_escalation_en is On:

whether any key requests is in progress
whether DAI interface is busy
whether lc_esc_en is On

sram_1_req_condition_cg

Covers the following conditions when lc_escalation_en is On:

whether any key requests is in progress
whether DAI interface is busy
whether lc_esc_en is On

sram_req_cg

Covers whether secret1 partition is locked during all srams key request.

status_csr_cg

Covers the value of every bit in status CSR.

tl_errors_cg

Cover the following error cases on TL-UL bus:

TL-UL protocol error cases.
OpenTitan defined error cases, refer to testpoint tl_d_illegal_access.

tl_intg_err_cg

Cover all kinds of integrity errors (command, data or both) and cover number of error bits on each integrity check.

Cover the kinds of integrity errors with byte enabled write on memory if applicable: Some memories store the integrity values. When there is a subword write, design re-calculate the integrity with full word data and update integrity in the memory. This coverage ensures that memory byte write has been issued and the related design logic has been verfied.

unbuf_access_lock_cg_wrap_cg

This is an array of covergroups to cover lock conditions below in three unbuffered partitions:

the partition is write-locked
the partition is read-locked
the current operation type Then cross the three coverpoints.

unbuf_err_code_cg

This is an array of covergroups to cover all applicable error codes in three unbuffered partitions.