Registers

Summary of the core interface’s registers

NameOffsetLengthDescription
otp_ctrl.INTR_STATE0x04Interrupt State Register
otp_ctrl.INTR_ENABLE0x44Interrupt Enable Register
otp_ctrl.INTR_TEST0x84Interrupt Test Register
otp_ctrl.ALERT_TEST0xc4Alert Test Register
otp_ctrl.STATUS0x104OTP status register.
otp_ctrl.ERR_CODE_00x144This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_10x184This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_20x1c4This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_30x204This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_40x244This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_50x284This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_60x2c4This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_70x304This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_80x344This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_90x384This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_100x3c4This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_110x404This register holds information about error conditions that occurred in the agents
otp_ctrl.ERR_CODE_120x444This register holds information about error conditions that occurred in the agents
otp_ctrl.DIRECT_ACCESS_REGWEN0x484Register write enable for all direct access interface registers.
otp_ctrl.DIRECT_ACCESS_CMD0x4c4Command register for direct accesses.
otp_ctrl.DIRECT_ACCESS_ADDRESS0x504Address register for direct accesses.
otp_ctrl.DIRECT_ACCESS_WDATA_00x544Write data for direct accesses.
otp_ctrl.DIRECT_ACCESS_WDATA_10x584Write data for direct accesses.
otp_ctrl.DIRECT_ACCESS_RDATA_00x5c4Read data for direct accesses.
otp_ctrl.DIRECT_ACCESS_RDATA_10x604Read data for direct accesses.
otp_ctrl.CHECK_TRIGGER_REGWEN0x644Register write enable for !!CHECK_TRIGGER.
otp_ctrl.CHECK_TRIGGER0x684Command register for direct accesses.
otp_ctrl.CHECK_REGWEN0x6c4Register write enable for !!INTEGRITY_CHECK_PERIOD and !!CONSISTENCY_CHECK_PERIOD.
otp_ctrl.CHECK_TIMEOUT0x704Timeout value for the integrity and consistency checks.
otp_ctrl.INTEGRITY_CHECK_PERIOD0x744This value specifies the maximum period that can be generated pseudo-randomly.
otp_ctrl.CONSISTENCY_CHECK_PERIOD0x784This value specifies the maximum period that can be generated pseudo-randomly.
otp_ctrl.VENDOR_TEST_READ_LOCK0x7c4Runtime read lock for the VENDOR_TEST partition.
otp_ctrl.CREATOR_SW_CFG_READ_LOCK0x804Runtime read lock for the CREATOR_SW_CFG partition.
otp_ctrl.OWNER_SW_CFG_READ_LOCK0x844Runtime read lock for the OWNER_SW_CFG partition.
otp_ctrl.ROT_CREATOR_AUTH_CODESIGN_READ_LOCK0x884Runtime read lock for the ROT_CREATOR_AUTH_CODESIGN partition.
otp_ctrl.ROT_CREATOR_AUTH_STATE_READ_LOCK0x8c4Runtime read lock for the ROT_CREATOR_AUTH_STATE partition.
otp_ctrl.VENDOR_TEST_DIGEST_00x904Integrity digest for the VENDOR_TEST partition.
otp_ctrl.VENDOR_TEST_DIGEST_10x944Integrity digest for the VENDOR_TEST partition.
otp_ctrl.CREATOR_SW_CFG_DIGEST_00x984Integrity digest for the CREATOR_SW_CFG partition.
otp_ctrl.CREATOR_SW_CFG_DIGEST_10x9c4Integrity digest for the CREATOR_SW_CFG partition.
otp_ctrl.OWNER_SW_CFG_DIGEST_00xa04Integrity digest for the OWNER_SW_CFG partition.
otp_ctrl.OWNER_SW_CFG_DIGEST_10xa44Integrity digest for the OWNER_SW_CFG partition.
otp_ctrl.ROT_CREATOR_AUTH_CODESIGN_DIGEST_00xa84Integrity digest for the ROT_CREATOR_AUTH_CODESIGN partition.
otp_ctrl.ROT_CREATOR_AUTH_CODESIGN_DIGEST_10xac4Integrity digest for the ROT_CREATOR_AUTH_CODESIGN partition.
otp_ctrl.ROT_CREATOR_AUTH_STATE_DIGEST_00xb04Integrity digest for the ROT_CREATOR_AUTH_STATE partition.
otp_ctrl.ROT_CREATOR_AUTH_STATE_DIGEST_10xb44Integrity digest for the ROT_CREATOR_AUTH_STATE partition.
otp_ctrl.HW_CFG0_DIGEST_00xb84Integrity digest for the HW_CFG0 partition.
otp_ctrl.HW_CFG0_DIGEST_10xbc4Integrity digest for the HW_CFG0 partition.
otp_ctrl.HW_CFG1_DIGEST_00xc04Integrity digest for the HW_CFG1 partition.
otp_ctrl.HW_CFG1_DIGEST_10xc44Integrity digest for the HW_CFG1 partition.
otp_ctrl.SECRET0_DIGEST_00xc84Integrity digest for the SECRET0 partition.
otp_ctrl.SECRET0_DIGEST_10xcc4Integrity digest for the SECRET0 partition.
otp_ctrl.SECRET1_DIGEST_00xd04Integrity digest for the SECRET1 partition.
otp_ctrl.SECRET1_DIGEST_10xd44Integrity digest for the SECRET1 partition.
otp_ctrl.SECRET2_DIGEST_00xd84Integrity digest for the SECRET2 partition.
otp_ctrl.SECRET2_DIGEST_10xdc4Integrity digest for the SECRET2 partition.
otp_ctrl.SW_CFG_WINDOW0x8002048Any read to this window directly maps to the corresponding offset in the creator and owner software

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw1c0x0otp_errorAn error has occurred in the OTP controller. Check the ERR_CODE register to get more information.
0rw1c0x0otp_operation_doneA direct access command or digest calculation operation has completed.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0otp_errorEnable interrupt when INTR_STATE.otp_error is set.
0rw0x0otp_operation_doneEnable interrupt when INTR_STATE.otp_operation_done is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0otp_errorWrite 1 to force INTR_STATE.otp_error to 1.
0wo0x0otp_operation_doneWrite 1 to force INTR_STATE.otp_operation_done to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

BitsTypeResetNameDescription
31:5Reserved
4wo0x0recov_prim_otp_alertWrite 1 to trigger one alert event of this kind.
3wo0x0fatal_prim_otp_alertWrite 1 to trigger one alert event of this kind.
2wo0x0fatal_bus_integ_errorWrite 1 to trigger one alert event of this kind.
1wo0x0fatal_check_errorWrite 1 to trigger one alert event of this kind.
0wo0x0fatal_macro_errorWrite 1 to trigger one alert event of this kind.

STATUS

OTP status register.

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xfffff

Fields

BitsTypeResetNameDescription
31:20Reserved
19ro0x0CHECK_PENDINGSet to 1 if an integrity or consistency check triggered by the LFSR timer or via CHECK_TRIGGER is pending.
18ro0x0DAI_IDLESet to 1 if the DAI is idle and ready to accept commands.
17ro0x0BUS_INTEG_ERRORThis bit is set to 1 if a fatal bus integrity fault is detected. This error triggers a fatal_bus_integ_error alert.
16ro0x0KEY_DERIV_FSM_ERRORSet to 1 if the key derivation FSM has reached an invalid state. This raises an fatal_check_error alert and is an unrecoverable error condition.
15ro0x0SCRAMBLING_FSM_ERRORSet to 1 if the scrambling datapath FSM has reached an invalid state. This raises an fatal_check_error alert and is an unrecoverable error condition.
14ro0x0LFSR_FSM_ERRORSet to 1 if the LFSR timer FSM has reached an invalid state. This raises an fatal_check_error alert and is an unrecoverable error condition.
13ro0x0TIMEOUT_ERRORSet to 1 if an integrity or consistency check times out. This raises an fatal_check_error alert and is an unrecoverable error condition.
12ro0x0LCI_ERRORSet to 1 if an error occurred in the LCI. If set to 1, SW should check the ERR_CODE register at the corresponding index.
11ro0x0DAI_ERRORSet to 1 if an error occurred in the DAI. If set to 1, SW should check the ERR_CODE register at the corresponding index.
10ro0x0LIFE_CYCLE_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
9ro0x0SECRET2_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
8ro0x0SECRET1_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
7ro0x0SECRET0_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
6ro0x0HW_CFG1_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
5ro0x0HW_CFG0_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
4ro0x0ROT_CREATOR_AUTH_STATE_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
3ro0x0ROT_CREATOR_AUTH_CODESIGN_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
2ro0x0OWNER_SW_CFG_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
1ro0x0CREATOR_SW_CFG_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.
0ro0x0VENDOR_TEST_ERRORSet to 1 if an error occurred in this partition. If set to 1, SW should check the ERR_CODE register at the corresponding index.

ERR_CODE

This register holds information about error conditions that occurred in the agents interacting with the OTP macro via the internal bus. The error codes should be checked if the partitions, DAI or LCI flag an error in the STATUS register, or when an INTR_STATE.otp_error has been triggered. Note that all errors trigger an otp_error interrupt, and in addition some errors may trigger either an fatal_macro_error or an fatal_check_error alert.

  • Reset default: 0x0
  • Reset mask: 0x7

Instances

NameOffset
ERR_CODE_00x14
ERR_CODE_10x18
ERR_CODE_20x1c
ERR_CODE_30x20
ERR_CODE_40x24
ERR_CODE_50x28
ERR_CODE_60x2c
ERR_CODE_70x30
ERR_CODE_80x34
ERR_CODE_90x38
ERR_CODE_100x3c
ERR_CODE_110x40
ERR_CODE_120x44

Fields

BitsTypeResetName
31:3Reserved
2:0ro0x0ERR_CODE

ERR_CODE . ERR_CODE

ValueNameDescription
0x0NO_ERRORNo error condition has occurred.
0x1MACRO_ERRORReturned if the OTP macro command was invalid or did not complete successfully due to a macro malfunction. This error should never occur during normal operation and is not recoverable. This error triggers an fatal_macro_error alert.
0x2MACRO_ECC_CORR_ERRORA correctable ECC error has occured during an OTP read operation. The corresponding controller automatically recovers from this error when issuing a new command.
0x3MACRO_ECC_UNCORR_ERRORAn uncorrectable ECC error has occurred during an OTP read operation. This error should never occur during normal operation and is not recoverable. If this error is present this may be a sign that the device is malfunctioning. This error triggers an fatal_macro_error alert.
0x4MACRO_WRITE_BLANK_ERRORThis error is returned if a programming operation attempted to clear a bit that has previously been programmed to 1. The corresponding controller automatically recovers from this error when issuing a new command. Note however that the affected OTP word may be left in an inconsistent state if this error occurs. This can cause several issues when the word is accessed again (either as part of a regular read operation, as part of the readout at boot, or as part of a background check). It is important that SW ensures that each word is only written once, since this can render the device useless.
0x5ACCESS_ERRORThis error indicates that a locked memory region has been accessed. The corresponding controller automatically recovers from this error when issuing a new command.
0x6CHECK_FAIL_ERRORAn ECC, integrity or consistency mismatch has been detected in the buffer registers. This error should never occur during normal operation and is not recoverable. This error triggers an fatal_check_error alert.
0x7FSM_STATE_ERRORThe FSM of the corresponding controller has reached an invalid state, or the FSM has been moved into a terminal error state due to an escalation action via lc_escalate_en_i. This error should never occur during normal operation and is not recoverable. If this error is present, this is a sign that the device has fallen victim to an invasive attack. This error triggers an fatal_check_error alert.

DIRECT_ACCESS_REGWEN

Register write enable for all direct access interface registers.

  • Offset: 0x48
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x1DIRECT_ACCESS_REGWEN

DIRECT_ACCESS_REGWEN . DIRECT_ACCESS_REGWEN

This bit controls whether the DAI registers can be written. Write 0 to it in order to clear the bit.

Note that the hardware also modulates this bit and sets it to 0 temporarily during an OTP operation such that the corresponding address and data registers cannot be modified while an operation is pending. The DAI_IDLE status bit will also be set to 0 in such a case.

DIRECT_ACCESS_CMD

Command register for direct accesses.

Fields

BitsTypeResetNameDescription
31:3Reserved
2r0w1c0x0DIGESTInitiates the digest calculation and locking sequence for the partition specified by DIRECT_ACCESS_ADDRESS.
1r0w1c0x0WRInitiates a programming sequence that writes the data in DIRECT_ACCESS_WDATA_0 and DIRECT_ACCESS_WDATA_1 (for 64bit partitions) to the location specified by DIRECT_ACCESS_ADDRESS.
0r0w1c0x0RDInitiates a readout sequence that reads the location specified by DIRECT_ACCESS_ADDRESS. The command places the data read into DIRECT_ACCESS_RDATA_0 and DIRECT_ACCESS_RDATA_1 (for 64bit partitions).

DIRECT_ACCESS_ADDRESS

Address register for direct accesses.

Fields

BitsTypeResetName
31:11Reserved
10:0rw0x0DIRECT_ACCESS_ADDRESS

DIRECT_ACCESS_ADDRESS . DIRECT_ACCESS_ADDRESS

This is the address for the OTP word to be read or written through the direct access interface. Note that the address is aligned to the access size internally, hence bits 1:0 are ignored for 32bit accesses, and bits 2:0 are ignored for 64bit accesses.

For the digest calculation command, set this register to the partition base offset.

DIRECT_ACCESS_WDATA

Write data for direct accesses. Hardware automatically determines the access granule (32bit or 64bit) based on which partition is being written to.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
DIRECT_ACCESS_WDATA_00x54
DIRECT_ACCESS_WDATA_10x58

Fields

BitsTypeResetNameDescription
31:0rw0x0DIRECT_ACCESS_WDATA

DIRECT_ACCESS_RDATA

Read data for direct accesses. Hardware automatically determines the access granule (32bit or 64bit) based on which partition is read from.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
DIRECT_ACCESS_RDATA_00x5c
DIRECT_ACCESS_RDATA_10x60

Fields

BitsTypeResetNameDescription
31:0ro0x0DIRECT_ACCESS_RDATA

CHECK_TRIGGER_REGWEN

Register write enable for CHECK_TRIGGER.

  • Offset: 0x64
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CHECK_TRIGGER_REGWENWhen cleared to 0, the CHECK_TRIGGER register cannot be written anymore. Write 0 to clear this bit.

CHECK_TRIGGER

Command register for direct accesses.

Fields

BitsTypeResetName
31:2Reserved
1r0w1c0x0CONSISTENCY
0r0w1c0x0INTEGRITY

CHECK_TRIGGER . CONSISTENCY

Writing 1 to this bit triggers a consistency check. SW should monitor STATUS.CHECK_PENDING and wait until the check has been completed. If there are any errors, those will be flagged in the STATUS and ERR_CODE registers, and via interrupts and alerts.

CHECK_TRIGGER . INTEGRITY

Writing 1 to this bit triggers an integrity check. SW should monitor STATUS.CHECK_PENDING and wait until the check has been completed. If there are any errors, those will be flagged in the STATUS and ERR_CODE registers, and via the interrupts and alerts.

CHECK_REGWEN

Register write enable for INTEGRITY_CHECK_PERIOD and CONSISTENCY_CHECK_PERIOD.

  • Offset: 0x6c
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CHECK_REGWENWhen cleared to 0, INTEGRITY_CHECK_PERIOD and CONSISTENCY_CHECK_PERIOD registers cannot be written anymore. Write 0 to clear this bit.

CHECK_TIMEOUT

Timeout value for the integrity and consistency checks.

  • Offset: 0x70
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CHECK_REGWEN

Fields

BitsTypeResetName
31:0rw0x0CHECK_TIMEOUT

CHECK_TIMEOUT . CHECK_TIMEOUT

Timeout value in cycles for the for the integrity and consistency checks. If an integrity or consistency check does not complete within the timeout window, an error will be flagged in the STATUS register, an otp_error interrupt will be raised, and an fatal_check_error alert will be sent out. The timeout should be set to a large value to stay on the safe side. The maximum check time can be upper bounded by the number of cycles it takes to readout, scramble and digest the entire OTP array. Since this amounts to roughly 25k cycles, it is recommended to set this value to at least 100’000 cycles in order to stay on the safe side. A value of zero disables the timeout mechanism (default).

INTEGRITY_CHECK_PERIOD

This value specifies the maximum period that can be generated pseudo-randomly. Only applies to the HW_CFG* and SECRET* partitions once they are locked.

  • Offset: 0x74
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CHECK_REGWEN

Fields

BitsTypeResetName
31:0rw0x0INTEGRITY_CHECK_PERIOD

INTEGRITY_CHECK_PERIOD . INTEGRITY_CHECK_PERIOD

The pseudo-random period is generated using a 40bit LFSR internally, and this register defines the bit mask to be applied to the LFSR output in order to limit its range. The value of this register is left shifted by 8bits and the lower bits are set to 8’hFF in order to form the 40bit mask. A recommended value is 0x3_FFFF, corresponding to a maximum period of ~2.8s at 24MHz. A value of zero disables the timer (default). Note that a one-off check can always be triggered via CHECK_TRIGGER.INTEGRITY.

CONSISTENCY_CHECK_PERIOD

This value specifies the maximum period that can be generated pseudo-randomly. This applies to the LIFE_CYCLE partition and the HW_CFG* and SECRET* partitions once they are locked.

  • Offset: 0x78
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: CHECK_REGWEN

Fields

BitsTypeResetName
31:0rw0x0CONSISTENCY_CHECK_PERIOD

CONSISTENCY_CHECK_PERIOD . CONSISTENCY_CHECK_PERIOD

The pseudo-random period is generated using a 40bit LFSR internally, and this register defines the bit mask to be applied to the LFSR output in order to limit its range. The value of this register is left shifted by 8bits and the lower bits are set to 8’hFF in order to form the 40bit mask. A recommended value is 0x3FF_FFFF, corresponding to a maximum period of ~716s at 24MHz. A value of zero disables the timer (default). Note that a one-off check can always be triggered via CHECK_TRIGGER.CONSISTENCY.

VENDOR_TEST_READ_LOCK

Runtime read lock for the VENDOR_TEST partition.

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1VENDOR_TEST_READ_LOCKWhen cleared to 0, read access to the VENDOR_TEST partition is locked. Write 0 to clear this bit.

CREATOR_SW_CFG_READ_LOCK

Runtime read lock for the CREATOR_SW_CFG partition.

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1CREATOR_SW_CFG_READ_LOCKWhen cleared to 0, read access to the CREATOR_SW_CFG partition is locked. Write 0 to clear this bit.

OWNER_SW_CFG_READ_LOCK

Runtime read lock for the OWNER_SW_CFG partition.

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1OWNER_SW_CFG_READ_LOCKWhen cleared to 0, read access to the OWNER_SW_CFG partition is locked. Write 0 to clear this bit.

ROT_CREATOR_AUTH_CODESIGN_READ_LOCK

Runtime read lock for the ROT_CREATOR_AUTH_CODESIGN partition.

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ROT_CREATOR_AUTH_CODESIGN_READ_LOCKWhen cleared to 0, read access to the ROT_CREATOR_AUTH_CODESIGN partition is locked. Write 0 to clear this bit.

ROT_CREATOR_AUTH_STATE_READ_LOCK

Runtime read lock for the ROT_CREATOR_AUTH_STATE partition.

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ROT_CREATOR_AUTH_STATE_READ_LOCKWhen cleared to 0, read access to the ROT_CREATOR_AUTH_STATE partition is locked. Write 0 to clear this bit.

VENDOR_TEST_DIGEST

Integrity digest for the VENDOR_TEST partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the VENDOR_TEST partition is locked and the digest becomes visible in this CSR.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
VENDOR_TEST_DIGEST_00x90
VENDOR_TEST_DIGEST_10x94

Fields

BitsTypeResetNameDescription
31:0ro0x0VENDOR_TEST_DIGEST

CREATOR_SW_CFG_DIGEST

Integrity digest for the CREATOR_SW_CFG partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the CREATOR_SW_CFG partition is locked and the digest becomes visible in this CSR.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
CREATOR_SW_CFG_DIGEST_00x98
CREATOR_SW_CFG_DIGEST_10x9c

Fields

BitsTypeResetNameDescription
31:0ro0x0CREATOR_SW_CFG_DIGEST

OWNER_SW_CFG_DIGEST

Integrity digest for the OWNER_SW_CFG partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the OWNER_SW_CFG partition is locked and the digest becomes visible in this CSR.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
OWNER_SW_CFG_DIGEST_00xa0
OWNER_SW_CFG_DIGEST_10xa4

Fields

BitsTypeResetNameDescription
31:0ro0x0OWNER_SW_CFG_DIGEST

ROT_CREATOR_AUTH_CODESIGN_DIGEST

Integrity digest for the ROT_CREATOR_AUTH_CODESIGN partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the ROT_CREATOR_AUTH_CODESIGN partition is locked and the digest becomes visible in this CSR.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
ROT_CREATOR_AUTH_CODESIGN_DIGEST_00xa8
ROT_CREATOR_AUTH_CODESIGN_DIGEST_10xac

Fields

BitsTypeResetNameDescription
31:0ro0x0ROT_CREATOR_AUTH_CODESIGN_DIGEST

ROT_CREATOR_AUTH_STATE_DIGEST

Integrity digest for the ROT_CREATOR_AUTH_STATE partition. The integrity digest is 0 by default. Software must write this digest value via the direct access interface in order to lock the partition. After a reset, write access to the ROT_CREATOR_AUTH_STATE partition is locked and the digest becomes visible in this CSR.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
ROT_CREATOR_AUTH_STATE_DIGEST_00xb0
ROT_CREATOR_AUTH_STATE_DIGEST_10xb4

Fields

BitsTypeResetNameDescription
31:0ro0x0ROT_CREATOR_AUTH_STATE_DIGEST

HW_CFG0_DIGEST

Integrity digest for the HW_CFG0 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
HW_CFG0_DIGEST_00xb8
HW_CFG0_DIGEST_10xbc

Fields

BitsTypeResetNameDescription
31:0ro0x0HW_CFG0_DIGEST

HW_CFG1_DIGEST

Integrity digest for the HW_CFG1 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
HW_CFG1_DIGEST_00xc0
HW_CFG1_DIGEST_10xc4

Fields

BitsTypeResetNameDescription
31:0ro0x0HW_CFG1_DIGEST

SECRET0_DIGEST

Integrity digest for the SECRET0 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
SECRET0_DIGEST_00xc8
SECRET0_DIGEST_10xcc

Fields

BitsTypeResetNameDescription
31:0ro0x0SECRET0_DIGEST

SECRET1_DIGEST

Integrity digest for the SECRET1 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
SECRET1_DIGEST_00xd0
SECRET1_DIGEST_10xd4

Fields

BitsTypeResetNameDescription
31:0ro0x0SECRET1_DIGEST

SECRET2_DIGEST

Integrity digest for the SECRET2 partition. The integrity digest is 0 by default. The digest calculation can be triggered via the DIRECT_ACCESS_CMD. After a reset, the digest then becomes visible in this CSR, and the corresponding partition becomes write-locked.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
SECRET2_DIGEST_00xd8
SECRET2_DIGEST_10xdc

Fields

BitsTypeResetNameDescription
31:0ro0x0SECRET2_DIGEST

SW_CFG_WINDOW

Any read to this window directly maps to the corresponding offset in the creator and owner software config partitions, and triggers an OTP readout of the bytes requested. Note that the transaction will block until OTP readout has completed.

  • Word Aligned Offset Range: 0x800to0xffc
  • Size (words): 512
  • Access: ro
  • Byte writes are not supported.

Summary of the prim interface’s registers

NameOffsetLengthDescription
otp_ctrl.CSR00x04
otp_ctrl.CSR10x44
otp_ctrl.CSR20x84
otp_ctrl.CSR30xc4
otp_ctrl.CSR40x104
otp_ctrl.CSR50x144
otp_ctrl.CSR60x184
otp_ctrl.CSR70x1c4

CSR0

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x7ff3ff7

Fields

BitsTypeResetNameDescription
31:27Reserved
26:16rw0x0field4
15:14Reserved
13:4rw0x0field3
3Reserved
2rw0x0field2
1rw0x0field1
0rw0x0field0

CSR1

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16rw0x0field4
15rw0x0field3
14:8rw0x0field2
7rw0x0field1
6:0rw0x0field0

CSR2

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0field0

CSR3

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x7f3ff7

Fields

BitsTypeResetNameDescription
31:23Reserved
22ro0x0field8
21ro0x0field7
20ro0x0field6
19ro0x0field5
18ro0x0field4
17ro0x0field3
16rw1c0x0field2
15:14Reserved
13:4rw1c0x0field1
3Reserved
2:0rw1c0x0field0

CSR4

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0x73ff

Fields

BitsTypeResetNameDescription
31:15Reserved
14rw0x0field3
13rw0x0field2
12rw0x0field1
11:10Reserved
9:0rw0x0field0

CSR5

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0xffff3fff

Fields

BitsTypeResetNameDescription
31:16rw0x0field6
15:14Reserved
13ro0x0field5
12ro0x0field4
11:9ro0x0field3
8ro0x0field2
7:6rw0x0field1
5:0rw0x0field0

CSR6

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0xffff1bff

Fields

BitsTypeResetNameDescription
31:16rw0x0field3
15:13Reserved
12rw0x0field2
11rw0x0field1
10Reserved
9:0rw0x0field0

CSR7

  • Offset: 0x1c
  • Reset default: 0x0
  • Reset mask: 0xc73f

Fields

BitsTypeResetNameDescription
31:16Reserved
15ro0x0field3
14ro0x0field2
13:11Reserved
10:8ro0x0field1
7:6Reserved
5:0ro0x0field0