Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module rstmgr has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: clk_aon_i, clk_io_div4_i, clk_main_i, clk_io_i, clk_io_div2_i, clk_usb_i, clk_por_i
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none
  • Interrupts: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
por_nlogicunircv2Root power on reset signals from ast. There is one root reset signal for each core power domain.
pwrpwr_rstreq_rsprsp1Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert.
resetsrstmgr_pkg::rstmgr_outunireq1Leaf resets fed to the system.
rst_enrstmgr_pkg::rstmgr_rst_enunireq1Low-power-group outputs used by alert handler.
alert_dumpalert_pkg::alert_crashdumpunircv1Alert handler crash dump information.
cpu_dumprv_core_ibex_pkg::cpu_crash_dumpunircv1Main processing element crash dump information.
sw_rst_reqprim_mubi_pkg::mubi4unireq1Software requested system reset to pwrmgr.
tltlul_pkg::tlreq_rsprsp1

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal structural fault is detected. Structural faults include errors such as sparse fsm errors and tlul integrity errors.
fatal_cnsty_faultThis fatal alert is triggered when a reset consistency fault is detected. It is separated from the category above for clearer error collection and debug.

Security Countermeasures

Countermeasure IDDescription
RSTMGR.BUS.INTEGRITYEnd-to-end bus integrity scheme.
RSTMGR.SCAN.INTERSIG.MUBIscan control signals are multibit
RSTMGR.LEAF.RST.BKGN_CHKBackground consistency checks for each leaf reset.
RSTMGR.LEAF.RST.SHADOWLeaf resets to blocks containing shadow registers are shadowed
RSTMGR.LEAF.FSM.SPARSESparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets
RSTMGR.SW_RST.CONFIG.REGWENSoftware reset controls are protected by regwen
RSTMGR.DUMP_CTRL.CONFIG.REGWENCrash dump controls are protected by regwen

Registers

Summary

NameOffsetLengthDescription
rstmgr.ALERT_TEST0x04Alert Test Register
rstmgr.RESET_REQ0x44Software requested system reset.
rstmgr.RESET_INFO0x84Device reset reason.
rstmgr.ALERT_REGWEN0xc4Alert write enable
rstmgr.ALERT_INFO_CTRL0x104Alert info dump controls.
rstmgr.ALERT_INFO_ATTR0x144Alert info dump attributes.
rstmgr.ALERT_INFO0x184Alert dump information prior to last reset.
rstmgr.CPU_REGWEN0x1c4Cpu write enable
rstmgr.CPU_INFO_CTRL0x204Cpu info dump controls.
rstmgr.CPU_INFO_ATTR0x244Cpu info dump attributes.
rstmgr.CPU_INFO0x284Cpu dump information prior to last reset.
rstmgr.SW_RST_REGWEN_00x2c4Register write enable for software controllable resets.
rstmgr.SW_RST_REGWEN_10x304Register write enable for software controllable resets.
rstmgr.SW_RST_REGWEN_20x344Register write enable for software controllable resets.
rstmgr.SW_RST_REGWEN_30x384Register write enable for software controllable resets.
rstmgr.SW_RST_REGWEN_40x3c4Register write enable for software controllable resets.
rstmgr.SW_RST_REGWEN_50x404Register write enable for software controllable resets.
rstmgr.SW_RST_REGWEN_60x444Register write enable for software controllable resets.
rstmgr.SW_RST_REGWEN_70x484Register write enable for software controllable resets.
rstmgr.SW_RST_CTRL_N_00x4c4Software controllable resets.
rstmgr.SW_RST_CTRL_N_10x504Software controllable resets.
rstmgr.SW_RST_CTRL_N_20x544Software controllable resets.
rstmgr.SW_RST_CTRL_N_30x584Software controllable resets.
rstmgr.SW_RST_CTRL_N_40x5c4Software controllable resets.
rstmgr.SW_RST_CTRL_N_50x604Software controllable resets.
rstmgr.SW_RST_CTRL_N_60x644Software controllable resets.
rstmgr.SW_RST_CTRL_N_70x684Software controllable resets.
rstmgr.ERR_CODE0x6c4A bit vector of all the errors that have occurred in reset manager

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0fatal_cnsty_faultWrite 1 to trigger one alert event of this kind.
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

RESET_REQ

Software requested system reset.

  • Offset: 0x4
  • Reset default: 0x9
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw0x9VALWhen set to kMultiBitBool4True, a reset to power manager is requested. Upon completion of reset, this bit is automatically cleared by hardware.

RESET_INFO

Device reset reason.

  • Offset: 0x8
  • Reset default: 0x1
  • Reset mask: 0xff

Fields

BitsTypeResetName
31:8Reserved
7:3rw1c0x0HW_REQ
2rw1c0x0SW_RESET
1rw1c0x0LOW_POWER_EXIT
0rw1c0x1POR

RESET_INFO . HW_REQ

Indicates when a device has reset due to a hardware requested reset. The bit mapping is as follows: b3: sysrst_ctrl_aon: OpenTitan reset request to rstmgr (running on AON clock). b4: aon_timer_aon: watchdog reset requestt b5: pwrmgr_aon: main power glitch reset request b6: alert_handler: escalation reset request b7: rv_dm: non-debug-module reset request

RESET_INFO . SW_RESET

Indicates when a device has reset due to RESET_REQ.

RESET_INFO . LOW_POWER_EXIT

Indicates when a device has reset due low power exit.

RESET_INFO . POR

Indicates when a device has reset due to power up.

ALERT_REGWEN

Alert write enable

  • Offset: 0xc
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENWhen 1, ALERT_INFO_CTRL can be modified.

ALERT_INFO_CTRL

Alert info dump controls.

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xf1
  • Register enable: ALERT_REGWEN

Fields

BitsTypeResetNameDescription
31:8Reserved
7:4rw0x0INDEXControls which 32-bit value to read.
3:1Reserved
0rw0x0ENEnable alert dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset).

ALERT_INFO_ATTR

Alert info dump attributes.

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0ro0x0CNT_AVAILThe number of 32-bit values contained in the alert info dump.

ALERT_INFO

Alert dump information prior to last reset. Which value read is controlled by the ALERT_INFO_CTRL register.

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x0VALUEThe current 32-bit value of crash dump.

CPU_REGWEN

Cpu write enable

  • Offset: 0x1c
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENWhen 1, CPU_INFO_CTRL can be modified.

CPU_INFO_CTRL

Cpu info dump controls.

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0xf1
  • Register enable: CPU_REGWEN

Fields

BitsTypeResetNameDescription
31:8Reserved
7:4rw0x0INDEXControls which 32-bit value to read.
3:1Reserved
0rw0x0ENEnable cpu dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset).

CPU_INFO_ATTR

Cpu info dump attributes.

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0ro0x0CNT_AVAILThe number of 32-bit values contained in the cpu info dump.

CPU_INFO

Cpu dump information prior to last reset. Which value read is controlled by the CPU_INFO_CTRL register.

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x0VALUEThe current 32-bit value of crash dump.

SW_RST_REGWEN

Register write enable for software controllable resets. When a particular bit value is 0, the corresponding value in SW_RST_CTRL_N can no longer be changed. When a particular bit value is 1, the corresponding value in SW_RST_CTRL_N can be changed.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
SW_RST_REGWEN_00x2c
SW_RST_REGWEN_10x30
SW_RST_REGWEN_20x34
SW_RST_REGWEN_30x38
SW_RST_REGWEN_40x3c
SW_RST_REGWEN_50x40
SW_RST_REGWEN_60x44
SW_RST_REGWEN_70x48

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENRegister write enable for software controllable resets

SW_RST_CTRL_N

Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset.

  • Reset default: 0x1
  • Reset mask: 0x1

Instances

NameOffset
SW_RST_CTRL_N_00x4c
SW_RST_CTRL_N_10x50
SW_RST_CTRL_N_20x54
SW_RST_CTRL_N_30x58
SW_RST_CTRL_N_40x5c
SW_RST_CTRL_N_50x60
SW_RST_CTRL_N_60x64
SW_RST_CTRL_N_70x68

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x1VALSoftware reset value

ERR_CODE

A bit vector of all the errors that have occurred in reset manager

  • Offset: 0x6c
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

BitsTypeResetNameDescription
31:3Reserved
2ro0x0FSM_ERRSparsely encoded fsm error.
1ro0x0RESET_CONSISTENCY_ERRA inconsistent parent / child reset was observed.
0ro0x0REG_INTG_ERRThe register file has experienced an integrity error.