Hardware Interfaces and Registers
Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module rstmgr
has the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: clk_aon_i
, clk_io_div4_i
, clk_main_i
, clk_io_i
, clk_io_div2_i
, clk_usb_i
, clk_por_i
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO: none
Inter-Module Signals: Reference
Port Name | Package::Struct | Type | Act | Width | Description |
---|---|---|---|---|---|
por_n | logic | uni | rcv | 2 | Root power on reset signals from ast. There is one root reset signal for each core power domain. |
pwr | pwr_rst | req_rsp | rsp | 1 | Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert. |
resets | rstmgr_pkg::rstmgr_out | uni | req | 1 | Leaf resets fed to the system. |
rst_en | rstmgr_pkg::rstmgr_rst_en | uni | req | 1 | Low-power-group outputs used by alert handler. |
alert_dump | alert_pkg::alert_crashdump | uni | rcv | 1 | Alert handler crash dump information. |
cpu_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | rcv | 1 | Main processing element crash dump information. |
sw_rst_req | prim_mubi_pkg::mubi4 | uni | req | 1 | Software requested system reset to pwrmgr. |
tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts: none
Security Alerts:
Alert Name | Description |
---|---|
fatal_fault | This fatal alert is triggered when a fatal structural fault is detected. Structural faults include errors such as sparse fsm errors and tlul integrity errors. |
fatal_cnsty_fault | This fatal alert is triggered when a reset consistency fault is detected. It is separated from the category above for clearer error collection and debug. |
Security Countermeasures:
Countermeasure ID | Description |
---|---|
RSTMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. |
RSTMGR.SCAN.INTERSIG.MUBI | scan control signals are multibit |
RSTMGR.LEAF.RST.BKGN_CHK | Background consistency checks for each leaf reset. |
RSTMGR.LEAF.RST.SHADOW | Leaf resets to blocks containing shadow registers are shadowed |
RSTMGR.LEAF.FSM.SPARSE | Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets |
RSTMGR.SW_RST.CONFIG.REGWEN | Software reset controls are protected by regwen |
RSTMGR.DUMP_CTRL.CONFIG.REGWEN | Crash dump controls are protected by regwen |
Registers
Summary | |||
---|---|---|---|
Name | Offset | Length | Description |
rstmgr.ALERT_TEST | 0x0 | 4 | Alert Test Register |
rstmgr.RESET_REQ | 0x4 | 4 | Software requested system reset. |
rstmgr.RESET_INFO | 0x8 | 4 | Device reset reason. |
rstmgr.ALERT_REGWEN | 0xc | 4 | Alert write enable |
rstmgr.ALERT_INFO_CTRL | 0x10 | 4 | Alert info dump controls. |
rstmgr.ALERT_INFO_ATTR | 0x14 | 4 | Alert info dump attributes. |
rstmgr.ALERT_INFO | 0x18 | 4 | Alert dump information prior to last reset.
Which value read is controlled by the |
rstmgr.CPU_REGWEN | 0x1c | 4 | Cpu write enable |
rstmgr.CPU_INFO_CTRL | 0x20 | 4 | Cpu info dump controls. |
rstmgr.CPU_INFO_ATTR | 0x24 | 4 | Cpu info dump attributes. |
rstmgr.CPU_INFO | 0x28 | 4 | Cpu dump information prior to last reset.
Which value read is controlled by the |
rstmgr.SW_RST_REGWEN_0 | 0x2c | 4 | Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in |
rstmgr.SW_RST_REGWEN_1 | 0x30 | 4 | Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in |
rstmgr.SW_RST_REGWEN_2 | 0x34 | 4 | Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in |
rstmgr.SW_RST_REGWEN_3 | 0x38 | 4 | Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in |
rstmgr.SW_RST_REGWEN_4 | 0x3c | 4 | Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in |
rstmgr.SW_RST_REGWEN_5 | 0x40 | 4 | Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in |
rstmgr.SW_RST_REGWEN_6 | 0x44 | 4 | Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in |
rstmgr.SW_RST_REGWEN_7 | 0x48 | 4 | Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in |
rstmgr.SW_RST_CTRL_N_0 | 0x4c | 4 | Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. |
rstmgr.SW_RST_CTRL_N_1 | 0x50 | 4 | Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. |
rstmgr.SW_RST_CTRL_N_2 | 0x54 | 4 | Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. |
rstmgr.SW_RST_CTRL_N_3 | 0x58 | 4 | Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. |
rstmgr.SW_RST_CTRL_N_4 | 0x5c | 4 | Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. |
rstmgr.SW_RST_CTRL_N_5 | 0x60 | 4 | Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. |
rstmgr.SW_RST_CTRL_N_6 | 0x64 | 4 | Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. |
rstmgr.SW_RST_CTRL_N_7 | 0x68 | 4 | Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. |
rstmgr.ERR_CODE | 0x6c | 4 | A bit vector of all the errors that have occurred in reset manager |
rstmgr.ALERT_TEST @ 0x0
Alert Test Register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | fatal_cnsty_fault | Write 1 to trigger one alert event of this kind. |
rstmgr.RESET_REQ @ 0x4
Software requested system reset. Reset default = 0x9, mask 0xf
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x9 | VAL | When set to kMultiBitBool4True, a reset to power manager is requested. Upon completion of reset, this bit is automatically cleared by hardware. |
rstmgr.RESET_INFO @ 0x8
Device reset reason. Reset default = 0x1, mask 0xff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x1 | POR | Indicates when a device has reset due to power up. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | LOW_POWER_EXIT | Indicates when a device has reset due low power exit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw1c | 0x0 | SW_RESET | Indicates when a device has reset due to | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:3 | rw1c | 0x0 | HW_REQ | Indicates when a device has reset due to a hardware requested reset.
The bit mapping is as follows:
b3: sysrst_ctrl_aon: OpenTitan reset request to |
rstmgr.ALERT_REGWEN @ 0xc
Alert write enable Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN | When 1, |
rstmgr.ALERT_INFO_CTRL @ 0x10
Alert info dump controls. Reset default = 0x0, mask 0xf1
Register enable = ALERT_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | EN | Enable alert dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:1 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. |
rstmgr.ALERT_INFO_ATTR @ 0x14
Alert info dump attributes. Reset default = 0x0, mask 0xf
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the alert info dump. |
rstmgr.ALERT_INFO @ 0x18
Alert dump information prior to last reset.
Which value read is controlled by the Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. |
rstmgr.CPU_REGWEN @ 0x1c
Cpu write enable Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN | When 1, |
rstmgr.CPU_INFO_CTRL @ 0x20
Cpu info dump controls. Reset default = 0x0, mask 0xf1
Register enable = CPU_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | EN | Enable cpu dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:1 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. |
rstmgr.CPU_INFO_ATTR @ 0x24
Cpu info dump attributes. Reset default = 0x0, mask 0xf
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the cpu info dump. |
rstmgr.CPU_INFO @ 0x28
Cpu dump information prior to last reset.
Which value read is controlled by the Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. |
rstmgr.SW_RST_REGWEN_0 @ 0x2c
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN_0 | Register write enable for software controllable resets |
rstmgr.SW_RST_REGWEN_1 @ 0x30
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN_1 | For RSTMGR_SW_RST1 |
rstmgr.SW_RST_REGWEN_2 @ 0x34
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN_2 | For RSTMGR_SW_RST2 |
rstmgr.SW_RST_REGWEN_3 @ 0x38
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN_3 | For RSTMGR_SW_RST3 |
rstmgr.SW_RST_REGWEN_4 @ 0x3c
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN_4 | For RSTMGR_SW_RST4 |
rstmgr.SW_RST_REGWEN_5 @ 0x40
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN_5 | For RSTMGR_SW_RST5 |
rstmgr.SW_RST_REGWEN_6 @ 0x44
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN_6 | For RSTMGR_SW_RST6 |
rstmgr.SW_RST_REGWEN_7 @ 0x48
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | EN_7 | For RSTMGR_SW_RST7 |
rstmgr.SW_RST_CTRL_N_0 @ 0x4c
Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_0 |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x1 | VAL_0 | Software reset value |
rstmgr.SW_RST_CTRL_N_1 @ 0x50
Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_1 |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x1 | VAL_1 | For RSTMGR_SW_RST1 |
rstmgr.SW_RST_CTRL_N_2 @ 0x54
Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_2 |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x1 | VAL_2 | For RSTMGR_SW_RST2 |
rstmgr.SW_RST_CTRL_N_3 @ 0x58
Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_3 |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x1 | VAL_3 | For RSTMGR_SW_RST3 |
rstmgr.SW_RST_CTRL_N_4 @ 0x5c
Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_4 |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x1 | VAL_4 | For RSTMGR_SW_RST4 |
rstmgr.SW_RST_CTRL_N_5 @ 0x60
Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_5 |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x1 | VAL_5 | For RSTMGR_SW_RST5 |
rstmgr.SW_RST_CTRL_N_6 @ 0x64
Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_6 |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x1 | VAL_6 | For RSTMGR_SW_RST6 |
rstmgr.SW_RST_CTRL_N_7 @ 0x68
Software controllable resets. When a particular bit value is 0, the corresponding module is held in reset. When a particular bit value is 1, the corresponding module is not held in reset. Reset default = 0x1, mask 0x1
Register enable = SW_RST_REGWEN_7 |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x1 | VAL_7 | For RSTMGR_SW_RST7 |
rstmgr.ERR_CODE @ 0x6c
A bit vector of all the errors that have occurred in reset manager Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x0 | REG_INTG_ERR | The register file has experienced an integrity error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | 0x0 | RESET_CONSISTENCY_ERR | A inconsistent parent / child reset was observed. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | ro | 0x0 | FSM_ERR | Sparsely encoded fsm error. |