Referring to the Comportable guideline for peripheral device functionality, the module rstmgr has the following hardware interfaces defined
- Primary Clock:
clk_i
- Other Clocks:
clk_aon_i, clk_io_div4_i, clk_main_i, clk_io_i, clk_io_div2_i, clk_usb_i, clk_por_i
- Bus Device Interfaces (TL-UL):
tl
- Bus Host Interfaces (TL-UL): none
- Peripheral Pins for Chip IO: none
- Interrupts: none
| Port Name | Package::Struct | Type | Act | Width | Description |
|---|
| por_n | logic | uni | rcv | 2 | Root power on reset signals from ast. There is one root reset signal for each core power domain. |
| pwr | pwr_rst | req_rsp | rsp | 1 | Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert. |
| resets | rstmgr_pkg::rstmgr_out | uni | req | 1 | Leaf resets fed to the system. |
| rst_en | rstmgr_pkg::rstmgr_rst_en | uni | req | 1 | Low-power-group outputs used by alert handler. |
| alert_dump | alert_pkg::alert_crashdump | uni | rcv | 1 | Alert handler crash dump information. |
| cpu_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | rcv | 1 | Main processing element crash dump information. |
| sw_rst_req | prim_mubi_pkg::mubi4 | uni | req | 1 | Software requested system reset to pwrmgr. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Alert Name | Description |
|---|
| fatal_fault | This fatal alert is triggered when a fatal structural fault is detected. Structural faults include errors such as sparse fsm errors and tlul integrity errors. |
| fatal_cnsty_fault | This fatal alert is triggered when a reset consistency fault is detected. It is separated from the category above for clearer error collection and debug. |
| Countermeasure ID | Description |
|---|
| RSTMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. |
| RSTMGR.SCAN.INTERSIG.MUBI | scan control signals are multibit |
| RSTMGR.LEAF.RST.BKGN_CHK | Background consistency checks for each leaf reset. |
| RSTMGR.LEAF.RST.SHADOW | Leaf resets to blocks containing shadow registers are shadowed |
| RSTMGR.LEAF.FSM.SPARSE | Sparsely encoded fsm for each leaf rst check. The Hamming delta is only 3 as there are a significant number of leaf resets |
| RSTMGR.SW_RST.CONFIG.REGWEN | Software reset controls are protected by regwen |
| RSTMGR.DUMP_CTRL.CONFIG.REGWEN | Crash dump controls are protected by regwen |
Alert Test Register
- Offset:
0x0
- Reset default:
0x0
- Reset mask:
0x3
| Bits | Type | Reset | Name | Description |
|---|
| 31:2 | | | | Reserved |
| 1 | wo | 0x0 | fatal_cnsty_fault | Write 1 to trigger one alert event of this kind. |
| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. |
Software requested system reset.
- Offset:
0x4
- Reset default:
0x9
- Reset mask:
0xf
| Bits | Type | Reset | Name | Description |
|---|
| 31:4 | | | | Reserved |
| 3:0 | rw | 0x9 | VAL | When set to kMultiBitBool4True, a reset to power manager is requested. Upon completion of reset, this bit is automatically cleared by hardware. |
Device reset reason.
- Offset:
0x8
- Reset default:
0x1
- Reset mask:
0xff
Indicates when a device has reset due to a hardware requested reset.
The bit mapping is as follows:
b3: sysrst_ctrl_aon: OpenTitan reset request to rstmgr (running on AON clock).
b4: aon_timer_aon: watchdog reset requestt
b5: pwrmgr_aon: main power glitch reset request
b6: alert_handler: escalation reset request
b7: rv_dm: non-debug-module reset request
Indicates when a device has reset due to RESET_REQ.
Indicates when a device has reset due low power exit.
Indicates when a device has reset due to power up.
Alert write enable
- Offset:
0xc
- Reset default:
0x1
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw0c | 0x1 | EN | When 1, ALERT_INFO_CTRL can be modified. |
Alert info dump controls.
- Offset:
0x10
- Reset default:
0x0
- Reset mask:
0xf1
- Register enable:
ALERT_REGWEN
| Bits | Type | Reset | Name | Description |
|---|
| 31:8 | | | | Reserved |
| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. |
| 3:1 | | | | Reserved |
| 0 | rw | 0x0 | EN | Enable alert dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). |
Alert info dump attributes.
- Offset:
0x14
- Reset default:
0x0
- Reset mask:
0xf
| Bits | Type | Reset | Name | Description |
|---|
| 31:4 | | | | Reserved |
| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the alert info dump. |
Alert dump information prior to last reset.
Which value read is controlled by the ALERT_INFO_CTRL register.
- Offset:
0x18
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. |
Cpu write enable
- Offset:
0x1c
- Reset default:
0x1
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw0c | 0x1 | EN | When 1, CPU_INFO_CTRL can be modified. |
Cpu info dump controls.
- Offset:
0x20
- Reset default:
0x0
- Reset mask:
0xf1
- Register enable:
CPU_REGWEN
| Bits | Type | Reset | Name | Description |
|---|
| 31:8 | | | | Reserved |
| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. |
| 3:1 | | | | Reserved |
| 0 | rw | 0x0 | EN | Enable cpu dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). |
Cpu info dump attributes.
- Offset:
0x24
- Reset default:
0x0
- Reset mask:
0xf
| Bits | Type | Reset | Name | Description |
|---|
| 31:4 | | | | Reserved |
| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the cpu info dump. |
Cpu dump information prior to last reset.
Which value read is controlled by the CPU_INFO_CTRL register.
- Offset:
0x28
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. |
Register write enable for software controllable resets.
When a particular bit value is 0, the corresponding value in SW_RST_CTRL_N can no longer be changed.
When a particular bit value is 1, the corresponding value in SW_RST_CTRL_N can be changed.
- Reset default:
0x1
- Reset mask:
0x1
| Name | Offset |
|---|
| SW_RST_REGWEN_0 | 0x2c |
| SW_RST_REGWEN_1 | 0x30 |
| SW_RST_REGWEN_2 | 0x34 |
| SW_RST_REGWEN_3 | 0x38 |
| SW_RST_REGWEN_4 | 0x3c |
| SW_RST_REGWEN_5 | 0x40 |
| SW_RST_REGWEN_6 | 0x44 |
| SW_RST_REGWEN_7 | 0x48 |
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw0c | 0x1 | EN | Register write enable for software controllable resets |
Software controllable resets.
When a particular bit value is 0, the corresponding module is held in reset.
When a particular bit value is 1, the corresponding module is not held in reset.
- Reset default:
0x1
- Reset mask:
0x1
| Name | Offset |
|---|
| SW_RST_CTRL_N_0 | 0x4c |
| SW_RST_CTRL_N_1 | 0x50 |
| SW_RST_CTRL_N_2 | 0x54 |
| SW_RST_CTRL_N_3 | 0x58 |
| SW_RST_CTRL_N_4 | 0x5c |
| SW_RST_CTRL_N_5 | 0x60 |
| SW_RST_CTRL_N_6 | 0x64 |
| SW_RST_CTRL_N_7 | 0x68 |
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw | 0x1 | VAL | Software reset value |
A bit vector of all the errors that have occurred in reset manager
- Offset:
0x6c
- Reset default:
0x0
- Reset mask:
0x7
| Bits | Type | Reset | Name | Description |
|---|
| 31:3 | | | | Reserved |
| 2 | ro | 0x0 | FSM_ERR | Sparsely encoded fsm error. |
| 1 | ro | 0x0 | RESET_CONSISTENCY_ERR | A inconsistent parent / child reset was observed. |
| 0 | ro | 0x0 | REG_INTG_ERR | The register file has experienced an integrity error. |