Hardware Interfaces and Registers
Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module rom_ctrl
has the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: none
Bus Device Interfaces (TL-UL): regs_tl
, rom_tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO: none
Inter-Module Signals: Reference
Port Name | Package::Struct | Type | Act | Width | Description |
---|---|---|---|---|---|
rom_cfg | prim_rom_pkg::rom_cfg | uni | rcv | 1 | |
pwrmgr_data | rom_ctrl_pkg::pwrmgr_data | uni | req | 1 | |
keymgr_data | rom_ctrl_pkg::keymgr_data | uni | req | 1 | |
kmac_data | kmac_pkg::app | req_rsp | req | 1 | |
regs_tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
rom_tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts: none
Security Alerts:
Alert Name | Description |
---|---|
fatal | A fatal error. Fatal alerts are non-recoverable and will be asserted until a hard reset. |
Security Countermeasures:
Countermeasure ID | Description |
---|---|
ROM_CTRL.CHECKER.CTR.CONSISTENCY | Once rom_ctrl has handed control of the mux to the bus, the internal FSM counter should point at the top of ROM (where we ensure the word has invalid ECC bits). The unexpected_counter_change signal in rom_ctrl_fsm goes high and generates a fatal alert if that counter is perturbed in any way. |
ROM_CTRL.CHECKER.CTRL_FLOW.CONSISTENCY | The main checker FSM steps on internal 'done' signals, coming from its address counter, the KMAC response and its comparison counter. If any of these are asserted at times we don't expect, the FSM jumps to an invalid state. This triggers an alert and will not set the external 'done' signal for pwrmgr to continue boot. |
ROM_CTRL.CHECKER.FSM.LOCAL_ESC | The main checker FSM moves to an invalid state on local escalation. |
ROM_CTRL.COMPARE.CTRL_FLOW.CONSISTENCY | The hash comparison module triggers a fatal error if the checker FSM triggers a second comparison after a reset. This is handled by the start_alert signal in the rom_ctrl_compare module and could be triggered if the checker FSM was somehow glitched to jump backwards. |
ROM_CTRL.COMPARE.CTR.CONSISTENCY | The hash comparison module has an internal count (indexing 32-bit words in the 256-bit digests). If this glitches to a nonzero value before the comparison starts or to a value other than the last index after the comparison ends then an fatal alert is generated. This is handled by the wait_addr_alert and done_addr_alert signals in rom_ctrl_compare. |
ROM_CTRL.COMPARE.CTR.REDUN | The hash comparison module has an internal count (indexing 32-bit words in the 256-bit digests) implemented using a redundant counter module. In case a mismatch is detected between the redundant counters a fatal alert is generated. |
ROM_CTRL.FSM.SPARSE | FSMs are sparsely encoded. There are two FSMs. The first is in rom_ctrl_fsm. The second, simpler FSM is in rom_ctrl_compare. |
ROM_CTRL.MEM.SCRAMBLE | The ROM is scrambled. |
ROM_CTRL.MEM.DIGEST | A cSHAKE digest is computed of the ROM contents. |
ROM_CTRL.INTERSIG.MUBI | Checker FSM 'done' signal is multi-bit encoded when passed to pwrmgr. This signal is derived from the (multi-bit) sparse FSM state in the rom_ctrl_fsm module. |
ROM_CTRL.BUS.INTEGRITY | TL bus control and data signals are integrity protected (using the system-wide end-to-end integrity scheme). |
ROM_CTRL.BUS.LOCAL_ESC | To avoid responding to a request with erroneous data, even though an alert went out, the bus_rom_rvalid signal used to signal a response to the ROM-side TL bus can only be high if no internal consistency error has been spotted. |
ROM_CTRL.MUX.MUBI | The mux that arbitrates between the checker and the bus is multi-bit encoded. An invalid value generates a fatal alert with the sel_invalid signal in the rom_ctrl_mux module. |
ROM_CTRL.MUX.CONSISTENCY | The mux that arbitrates between the checker and the bus gives access to the checker at the start of time and then switches to the bus, never going back. If a glitch does cause it to switch back, a fatal alert is generated with the sel_reverted or sel_q_reverted signals in the rom_ctrl_mux module. |
ROM_CTRL.CTRL.REDUN | Addresses from TL accesses are passed redundantly to the scrambled ROM module, to ensure the address lines are not independently faultable downstream of the bus integrity ECC check. See the bus_rom_prince_index and bus_rom_rom_index signals in the rom_ctrl module. |
ROM_CTRL.CTRL.MEM.INTEGRITY | End-to-end data/memory integrity scheme. |
ROM_CTRL.TLUL_FIFO.CTR.REDUN | The TL-UL response FIFO pointers are implemented with duplicate counters. |
Registers
Registers visible under device interface regs
Summary | |||
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Name | Offset | Length | Description |
rom_ctrl.ALERT_TEST | 0x0 | 4 | Alert Test Register |
rom_ctrl.FATAL_ALERT_CAUSE | 0x4 | 4 | The cause of a fatal alert. |
rom_ctrl.DIGEST_0 | 0x8 | 4 | The digest computed from the contents of ROM |
rom_ctrl.DIGEST_1 | 0xc | 4 | The digest computed from the contents of ROM |
rom_ctrl.DIGEST_2 | 0x10 | 4 | The digest computed from the contents of ROM |
rom_ctrl.DIGEST_3 | 0x14 | 4 | The digest computed from the contents of ROM |
rom_ctrl.DIGEST_4 | 0x18 | 4 | The digest computed from the contents of ROM |
rom_ctrl.DIGEST_5 | 0x1c | 4 | The digest computed from the contents of ROM |
rom_ctrl.DIGEST_6 | 0x20 | 4 | The digest computed from the contents of ROM |
rom_ctrl.DIGEST_7 | 0x24 | 4 | The digest computed from the contents of ROM |
rom_ctrl.EXP_DIGEST_0 | 0x28 | 4 | The expected digest, stored in the top words of ROM |
rom_ctrl.EXP_DIGEST_1 | 0x2c | 4 | The expected digest, stored in the top words of ROM |
rom_ctrl.EXP_DIGEST_2 | 0x30 | 4 | The expected digest, stored in the top words of ROM |
rom_ctrl.EXP_DIGEST_3 | 0x34 | 4 | The expected digest, stored in the top words of ROM |
rom_ctrl.EXP_DIGEST_4 | 0x38 | 4 | The expected digest, stored in the top words of ROM |
rom_ctrl.EXP_DIGEST_5 | 0x3c | 4 | The expected digest, stored in the top words of ROM |
rom_ctrl.EXP_DIGEST_6 | 0x40 | 4 | The expected digest, stored in the top words of ROM |
rom_ctrl.EXP_DIGEST_7 | 0x44 | 4 | The expected digest, stored in the top words of ROM |
rom_ctrl.ALERT_TEST @ 0x0
Alert Test Register Reset default = 0x0, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | fatal | Write 1 to trigger one alert event of this kind. |
rom_ctrl.FATAL_ALERT_CAUSE @ 0x4
The cause of a fatal alert. Reset default = 0x0, mask 0x3
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The bits of this register correspond to errors that can cause a fatal alert. Software can read these bits to see what went wrong. Once set, these bits cannot be cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x0 | checker_error | Set on a fatal error detected by the ROM checker. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | 0x0 | integrity_error | Set on an integrity error from the register interface. |
rom_ctrl.DIGEST_0 @ 0x8
The digest computed from the contents of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_0 | 32 bits of the digest |
rom_ctrl.DIGEST_1 @ 0xc
The digest computed from the contents of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_1 | For ROM_CTRL1 |
rom_ctrl.DIGEST_2 @ 0x10
The digest computed from the contents of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_2 | For ROM_CTRL2 |
rom_ctrl.DIGEST_3 @ 0x14
The digest computed from the contents of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_3 | For ROM_CTRL3 |
rom_ctrl.DIGEST_4 @ 0x18
The digest computed from the contents of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_4 | For ROM_CTRL4 |
rom_ctrl.DIGEST_5 @ 0x1c
The digest computed from the contents of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_5 | For ROM_CTRL5 |
rom_ctrl.DIGEST_6 @ 0x20
The digest computed from the contents of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_6 | For ROM_CTRL6 |
rom_ctrl.DIGEST_7 @ 0x24
The digest computed from the contents of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_7 | For ROM_CTRL7 |
rom_ctrl.EXP_DIGEST_0 @ 0x28
The expected digest, stored in the top words of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_0 | 32 bits of the digest |
rom_ctrl.EXP_DIGEST_1 @ 0x2c
The expected digest, stored in the top words of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_1 | For ROM_CTRL1 |
rom_ctrl.EXP_DIGEST_2 @ 0x30
The expected digest, stored in the top words of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_2 | For ROM_CTRL2 |
rom_ctrl.EXP_DIGEST_3 @ 0x34
The expected digest, stored in the top words of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_3 | For ROM_CTRL3 |
rom_ctrl.EXP_DIGEST_4 @ 0x38
The expected digest, stored in the top words of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_4 | For ROM_CTRL4 |
rom_ctrl.EXP_DIGEST_5 @ 0x3c
The expected digest, stored in the top words of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_5 | For ROM_CTRL5 |
rom_ctrl.EXP_DIGEST_6 @ 0x40
The expected digest, stored in the top words of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_6 | For ROM_CTRL6 |
rom_ctrl.EXP_DIGEST_7 @ 0x44
The expected digest, stored in the top words of ROM Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | DIGEST_7 | For ROM_CTRL7 |
Registers visible under device interface rom
Summary | |||
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Name | Offset | Length | Description |
rom_ctrl.ROM | 0x0 | 32768 | ROM data |
rom_ctrl.ROM @ + 0x0
8192 item ro window
Byte writes are not supported
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ROM data |