Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module rom_ctrl has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): regs_tl, rom_tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none
  • Interrupts: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
rom_cfgprim_rom_pkg::rom_cfgunircv1
pwrmgr_datarom_ctrl_pkg::pwrmgr_dataunireq1
keymgr_datarom_ctrl_pkg::keymgr_dataunireq1
kmac_datakmac_pkg::appreq_rspreq1
regs_tltlul_pkg::tlreq_rsprsp1
rom_tltlul_pkg::tlreq_rsprsp1

Security Alerts

Alert NameDescription
fatalA fatal error. Fatal alerts are non-recoverable and will be asserted until a hard reset.

Security Countermeasures

Countermeasure IDDescription
ROM_CTRL.CHECKER.CTR.CONSISTENCYOnce rom_ctrl has handed control of the mux to the bus, the internal FSM counter should point at the top of ROM (where we ensure the word has invalid ECC bits). The unexpected_counter_change signal in rom_ctrl_fsm goes high and generates a fatal alert if that counter is perturbed in any way.
ROM_CTRL.CHECKER.CTRL_FLOW.CONSISTENCYThe main checker FSM steps on internal ‘done’ signals, coming from its address counter, the KMAC response and its comparison counter. If any of these are asserted at times we don’t expect, the FSM jumps to an invalid state. This triggers an alert and will not set the external ‘done’ signal for pwrmgr to continue boot.
ROM_CTRL.CHECKER.FSM.LOCAL_ESCThe main checker FSM moves to an invalid state on local escalation.
ROM_CTRL.COMPARE.CTRL_FLOW.CONSISTENCYThe hash comparison module triggers a fatal error if the checker FSM triggers a second comparison after a reset. This is handled by the start_alert signal in the rom_ctrl_compare module and could be triggered if the checker FSM was somehow glitched to jump backwards.
ROM_CTRL.COMPARE.CTR.CONSISTENCYThe hash comparison module has an internal count (indexing 32-bit words in the 256-bit digests). If this glitches to a nonzero value before the comparison starts or to a value other than the last index after the comparison ends then an fatal alert is generated. This is handled by the wait_addr_alert and done_addr_alert signals in rom_ctrl_compare.
ROM_CTRL.COMPARE.CTR.REDUNThe hash comparison module has an internal count (indexing 32-bit words in the 256-bit digests) implemented using a redundant counter module. In case a mismatch is detected between the redundant counters a fatal alert is generated.
ROM_CTRL.FSM.SPARSEFSMs are sparsely encoded. There are two FSMs. The first is in rom_ctrl_fsm. The second, simpler FSM is in rom_ctrl_compare.
ROM_CTRL.MEM.SCRAMBLEThe ROM is scrambled.
ROM_CTRL.MEM.DIGESTA cSHAKE digest is computed of the ROM contents.
ROM_CTRL.INTERSIG.MUBIChecker FSM ‘done’ signal is multi-bit encoded when passed to pwrmgr. This signal is derived from the (multi-bit) sparse FSM state in the rom_ctrl_fsm module.
ROM_CTRL.BUS.INTEGRITYTL bus control and data signals are integrity protected (using the system-wide end-to-end integrity scheme).
ROM_CTRL.BUS.LOCAL_ESCTo avoid responding to a request with erroneous data, even though an alert went out, the bus_rom_rvalid signal used to signal a response to the ROM-side TL bus can only be high if no internal consistency error has been spotted.
ROM_CTRL.MUX.MUBIThe mux that arbitrates between the checker and the bus is multi-bit encoded. An invalid value generates a fatal alert with the sel_invalid signal in the rom_ctrl_mux module.
ROM_CTRL.MUX.CONSISTENCYThe mux that arbitrates between the checker and the bus gives access to the checker at the start of time and then switches to the bus, never going back. If a glitch does cause it to switch back, a fatal alert is generated with the sel_reverted or sel_q_reverted signals in the rom_ctrl_mux module.
ROM_CTRL.CTRL.REDUNAddresses from TL accesses are passed redundantly to the scrambled ROM module, to ensure the address lines are not independently faultable downstream of the bus integrity ECC check. See the bus_rom_prince_index and bus_rom_rom_index signals in the rom_ctrl module.
ROM_CTRL.CTRL.MEM.INTEGRITYEnd-to-end data/memory integrity scheme.
ROM_CTRL.TLUL_FIFO.CTR.REDUNThe TL-UL response FIFO pointers are implemented with duplicate counters.

Registers

Summary of the regs interface’s registers

NameOffsetLengthDescription
rom_ctrl.ALERT_TEST0x04Alert Test Register
rom_ctrl.FATAL_ALERT_CAUSE0x44The cause of a fatal alert.
rom_ctrl.DIGEST_00x84The digest computed from the contents of ROM
rom_ctrl.DIGEST_10xc4The digest computed from the contents of ROM
rom_ctrl.DIGEST_20x104The digest computed from the contents of ROM
rom_ctrl.DIGEST_30x144The digest computed from the contents of ROM
rom_ctrl.DIGEST_40x184The digest computed from the contents of ROM
rom_ctrl.DIGEST_50x1c4The digest computed from the contents of ROM
rom_ctrl.DIGEST_60x204The digest computed from the contents of ROM
rom_ctrl.DIGEST_70x244The digest computed from the contents of ROM
rom_ctrl.EXP_DIGEST_00x284The expected digest, stored in the top words of ROM
rom_ctrl.EXP_DIGEST_10x2c4The expected digest, stored in the top words of ROM
rom_ctrl.EXP_DIGEST_20x304The expected digest, stored in the top words of ROM
rom_ctrl.EXP_DIGEST_30x344The expected digest, stored in the top words of ROM
rom_ctrl.EXP_DIGEST_40x384The expected digest, stored in the top words of ROM
rom_ctrl.EXP_DIGEST_50x3c4The expected digest, stored in the top words of ROM
rom_ctrl.EXP_DIGEST_60x404The expected digest, stored in the top words of ROM
rom_ctrl.EXP_DIGEST_70x444The expected digest, stored in the top words of ROM

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatalWrite 1 to trigger one alert event of this kind.

FATAL_ALERT_CAUSE

The cause of a fatal alert.

The bits of this register correspond to errors that can cause a fatal alert. Software can read these bits to see what went wrong. Once set, these bits cannot be cleared.

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1ro0x0integrity_errorSet on an integrity error from the register interface.
0ro0x0checker_errorSet on a fatal error detected by the ROM checker.

DIGEST

The digest computed from the contents of ROM

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
DIGEST_00x8
DIGEST_10xc
DIGEST_20x10
DIGEST_30x14
DIGEST_40x18
DIGEST_50x1c
DIGEST_60x20
DIGEST_70x24

Fields

BitsTypeResetNameDescription
31:0ro0x0DIGEST32 bits of the digest

EXP_DIGEST

The expected digest, stored in the top words of ROM

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
EXP_DIGEST_00x28
EXP_DIGEST_10x2c
EXP_DIGEST_20x30
EXP_DIGEST_30x34
EXP_DIGEST_40x38
EXP_DIGEST_50x3c
EXP_DIGEST_60x40
EXP_DIGEST_70x44

Fields

BitsTypeResetNameDescription
31:0ro0x0DIGEST32 bits of the digest

Summary of the rom interface’s registers

NameOffsetLengthDescription
rom_ctrl.ROM0x032768ROM data

ROM

ROM data

  • Word Aligned Offset Range: 0x0to0x7ffc
  • Size (words): 8192
  • Access: ro
  • Byte writes are not supported.