Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pattgen has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
pda0_txoutput

Serial output data bit for pattern generation on Channel 0

pcl0_txoutput

Clock corresponding to pattern data on Channel 0

pda1_txoutput

Serial output data bit for pattern generation on Channel 1

pcl1_txoutput

Clock corresponding to pattern data on Channel 1

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
done_ch0Event

raise if pattern generation on Channel 0 is complete

done_ch1Event

raise if pattern generation on Channel 1 is complete

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
PATTGEN.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
pattgen.INTR_STATE 0x0 4

Interrupt State Register

pattgen.INTR_ENABLE 0x4 4

Interrupt Enable Register

pattgen.INTR_TEST 0x8 4

Interrupt Test Register

pattgen.ALERT_TEST 0xc 4

Alert Test Register

pattgen.CTRL 0x10 4

PATTGEN control register

pattgen.PREDIV_CH0 0x14 4

PATTGEN pre-divider register for Channel 0

pattgen.PREDIV_CH1 0x18 4

PATTGEN pre-divider register for Channel 1

pattgen.DATA_CH0_0 0x1c 4

PATTGEN seed pattern multi-registers for Channel 0.

pattgen.DATA_CH0_1 0x20 4

PATTGEN seed pattern multi-registers for Channel 0.

pattgen.DATA_CH1_0 0x24 4

PATTGEN seed pattern multi-registers for Channel 1.

pattgen.DATA_CH1_1 0x28 4

PATTGEN seed pattern multi-registers for Channel 1.

pattgen.SIZE 0x2c 4

PATTGEN pattern length

pattgen.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  done_ch1 done_ch0
BitsTypeResetNameDescription
0rw1c0x0done_ch0

raise if pattern generation on Channel 0 is complete

1rw1c0x0done_ch1

raise if pattern generation on Channel 1 is complete


pattgen.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  done_ch1 done_ch0
BitsTypeResetNameDescription
0rw0x0done_ch0

Enable interrupt when INTR_STATE.done_ch0 is set.

1rw0x0done_ch1

Enable interrupt when INTR_STATE.done_ch1 is set.


pattgen.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  done_ch1 done_ch0
BitsTypeResetNameDescription
0wo0x0done_ch0

Write 1 to force INTR_STATE.done_ch0 to 1.

1wo0x0done_ch1

Write 1 to force INTR_STATE.done_ch1 to 1.


pattgen.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


pattgen.CTRL @ 0x10

PATTGEN control register

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  POLARITY_CH1 POLARITY_CH0 ENABLE_CH1 ENABLE_CH0
BitsTypeResetNameDescription
0rw0x0ENABLE_CH0

Enable pattern generator functionality for Channel 0

1rw0x0ENABLE_CH1

Enable pattern generator functionality for Channel 1

2rw0x0POLARITY_CH0

Clock (pcl) polarity for Channel 0. If low, pda signal changes on falling edge of pcl signal, otherwise pda changes on rising edge. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

3rw0x0POLARITY_CH1

Clock (pcl) polarity for Channel 1. If low, pda signal changes on falling edge of pcl signal, otherwise pda changes on rising edge. Note that writes to a channel's configuration registers have no effect while the channel is enabled.


pattgen.PREDIV_CH0 @ 0x14

PATTGEN pre-divider register for Channel 0

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
CLK_RATIO...
1514131211109876543210
...CLK_RATIO
BitsTypeResetNameDescription
31:0rw0x0CLK_RATIO

Clock divider ratio fpr Channel 0 (relative to I/O clock). Note that writes to a channel's configuration registers have no effect while the channel is enabled.


pattgen.PREDIV_CH1 @ 0x18

PATTGEN pre-divider register for Channel 1

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
CLK_RATIO...
1514131211109876543210
...CLK_RATIO
BitsTypeResetNameDescription
31:0rw0x0CLK_RATIO

Clock divider ratio for Channel 1 (relative to I/O clock). Note that writes to a channel's configuration registers have no effect while the channel is enabled.


pattgen.DATA_CH0_0 @ 0x1c

PATTGEN seed pattern multi-registers for Channel 0.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DATA_0...
1514131211109876543210
...DATA_0
BitsTypeResetNameDescription
31:0rw0x0DATA_0

Seed pattern for Channel 0 (1-64 bits). Note that writes to a channel's configuration registers have no effect while the channel is enabled.


pattgen.DATA_CH0_1 @ 0x20

PATTGEN seed pattern multi-registers for Channel 0.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DATA_1...
1514131211109876543210
...DATA_1
BitsTypeResetNameDescription
31:0rw0x0DATA_1

For PATTGEN1


pattgen.DATA_CH1_0 @ 0x24

PATTGEN seed pattern multi-registers for Channel 1.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DATA_0...
1514131211109876543210
...DATA_0
BitsTypeResetNameDescription
31:0rw0x0DATA_0

Seed pattern for Channel 1 (1-64 bits). Note that writes to a channel's configuration registers have no effect while the channel is enabled.


pattgen.DATA_CH1_1 @ 0x28

PATTGEN seed pattern multi-registers for Channel 1.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DATA_1...
1514131211109876543210
...DATA_1
BitsTypeResetNameDescription
31:0rw0x0DATA_1

For PATTGEN1


pattgen.SIZE @ 0x2c

PATTGEN pattern length

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
REPS_CH1 LEN_CH1
1514131211109876543210
REPS_CH0 LEN_CH0
BitsTypeResetNameDescription
5:0rw0x0LEN_CH0

Length of the seed pattern for Channel 0, minus 1. Valid values: 0..63. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

15:6rw0x0REPS_CH0

Number of pattern repetitions for Channel 0, minus 1. Valid values: 0..1023. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

21:16rw0x0LEN_CH1

Length of the seed pattern for Channel 1, minus 1. Valid values: 0..63. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

31:22rw0x0REPS_CH1

Number of pattern repetitions for Channel 1, minus 1. Valid values: 0..1023. Note that writes to a channel's configuration registers have no effect while the channel is enabled.