Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pattgen has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin name	direction	Description
pda0_tx	output	Serial output data bit for pattern generation on Channel 0
pcl0_tx	output	Clock corresponding to pattern data on Channel 0
pda1_tx	output	Serial output data bit for pattern generation on Channel 1
pcl1_tx	output	Clock corresponding to pattern data on Channel 1

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width	Description
tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts:

Interrupt Name	Type	Description
done_ch0	Event	raise if pattern generation on Channel 0 is complete
done_ch1	Event	raise if pattern generation on Channel 1 is complete

Security Alerts:

Alert Name	Description
fatal_fault	This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure ID	Description
PATTGEN.BUS.INTEGRITY	End-to-end bus integrity scheme.

Registers

Summary
Name	Offset	Length	Description
pattgen.INTR_STATE	0x0	4	Interrupt State Register
pattgen.INTR_ENABLE	0x4	4	Interrupt Enable Register
pattgen.INTR_TEST	0x8	4	Interrupt Test Register
pattgen.ALERT_TEST	0xc	4	Alert Test Register
pattgen.CTRL	0x10	4	PATTGEN control register
pattgen.PREDIV_CH0	0x14	4	PATTGEN pre-divider register for Channel 0
pattgen.PREDIV_CH1	0x18	4	PATTGEN pre-divider register for Channel 1
pattgen.DATA_CH0_0	0x1c	4	PATTGEN seed pattern multi-registers for Channel 0.
pattgen.DATA_CH0_1	0x20	4	PATTGEN seed pattern multi-registers for Channel 0.
pattgen.DATA_CH1_0	0x24	4	PATTGEN seed pattern multi-registers for Channel 1.
pattgen.DATA_CH1_1	0x28	4	PATTGEN seed pattern multi-registers for Channel 1.
pattgen.SIZE	0x2c	4	PATTGEN pattern length

pattgen.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														done_ch1	done_ch0

Bits

Type

Reset

Name

Description

rw1c

0x0

done_ch0

raise if pattern generation on Channel 0 is complete

rw1c

0x0

done_ch1

raise if pattern generation on Channel 1 is complete

pattgen.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														done_ch1	done_ch0

Bits Type Reset Name Description

0x0

done_ch0

Enable interrupt when INTR_STATE.done_ch0 is set.

0x0

done_ch1

Enable interrupt when INTR_STATE.done_ch1 is set.

pattgen.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														done_ch1	done_ch0

Bits Type Reset Name Description

0x0

done_ch0

Write 1 to force INTR_STATE.done_ch0 to 1.

0x0

done_ch1

Write 1 to force INTR_STATE.done_ch1 to 1.

pattgen.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															fatal_fault

Bits

Type

Reset

Name

Description

0x0

fatal_fault

Write 1 to trigger one alert event of this kind.

pattgen.CTRL @ 0x10

PATTGEN control register

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												POLARITY_CH1	POLARITY_CH0	ENABLE_CH1	ENABLE_CH0

Bits Type Reset Name Description

0x0

ENABLE_CH0

Enable pattern generator functionality for Channel 0

0x0

ENABLE_CH1

Enable pattern generator functionality for Channel 1

0x0

POLARITY_CH0

Clock (pcl) polarity for Channel 0. If low, pda signal changes on falling edge of pcl signal, otherwise pda changes on rising edge. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

0x0

POLARITY_CH1

Clock (pcl) polarity for Channel 1. If low, pda signal changes on falling edge of pcl signal, otherwise pda changes on rising edge. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

pattgen.PREDIV_CH0 @ 0x14

PATTGEN pre-divider register for Channel 0

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLK_RATIO...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLK_RATIO

Bits

Type

Reset

Name

Description

31:0

0x0

CLK_RATIO

Clock divider ratio fpr Channel 0 (relative to I/O clock). Note that writes to a channel's configuration registers have no effect while the channel is enabled.

pattgen.PREDIV_CH1 @ 0x18

PATTGEN pre-divider register for Channel 1

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLK_RATIO...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CLK_RATIO

Bits

Type

Reset

Name

Description

31:0

0x0

CLK_RATIO

Clock divider ratio for Channel 1 (relative to I/O clock). Note that writes to a channel's configuration registers have no effect while the channel is enabled.

pattgen.DATA_CH0_0 @ 0x1c

PATTGEN seed pattern multi-registers for Channel 0.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...DATA_0

Bits

Type

Reset

Name

Description

31:0

0x0

DATA_0

Seed pattern for Channel 0 (1-64 bits). Note that writes to a channel's configuration registers have no effect while the channel is enabled.

pattgen.DATA_CH0_1 @ 0x20

PATTGEN seed pattern multi-registers for Channel 0.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...DATA_1

Bits

Type

Reset

Name

Description

31:0

0x0

DATA_1

For PATTGEN1

pattgen.DATA_CH1_0 @ 0x24

PATTGEN seed pattern multi-registers for Channel 1.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...DATA_0

Bits

Type

Reset

Name

Description

31:0

0x0

DATA_0

Seed pattern for Channel 1 (1-64 bits). Note that writes to a channel's configuration registers have no effect while the channel is enabled.

pattgen.DATA_CH1_1 @ 0x28

PATTGEN seed pattern multi-registers for Channel 1.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...DATA_1

Bits

Type

Reset

Name

Description

31:0

0x0

DATA_1

For PATTGEN1

pattgen.SIZE @ 0x2c

PATTGEN pattern length

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REPS_CH1										LEN_CH1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REPS_CH0										LEN_CH0

Bits

Type

Reset

Name

Description

5:0

0x0

LEN_CH0

Length of the seed pattern for Channel 0, minus 1. Valid values: 0..63. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

15:6

0x0

REPS_CH0

Number of pattern repetitions for Channel 0, minus 1. Valid values: 0..1023. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

21:16

0x0

LEN_CH1

Length of the seed pattern for Channel 1, minus 1. Valid values: 0..63. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

31:22

0x0

REPS_CH1

Number of pattern repetitions for Channel 1, minus 1. Valid values: 0..1023. Note that writes to a channel's configuration registers have no effect while the channel is enabled.

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers