Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pattgen has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO

Pin nameDirectionDescription
pda0_txoutputSerial output data bit for pattern generation on Channel 0
pcl0_txoutputClock corresponding to pattern data on Channel 0
pda1_txoutputSerial output data bit for pattern generation on Channel 1
pcl1_txoutputClock corresponding to pattern data on Channel 1

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
done_ch0Eventraise if pattern generation on Channel 0 is complete
done_ch1Eventraise if pattern generation on Channel 1 is complete

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure IDDescription
PATTGEN.BUS.INTEGRITYEnd-to-end bus integrity scheme.

Registers

Summary

NameOffsetLengthDescription
pattgen.INTR_STATE0x04Interrupt State Register
pattgen.INTR_ENABLE0x44Interrupt Enable Register
pattgen.INTR_TEST0x84Interrupt Test Register
pattgen.ALERT_TEST0xc4Alert Test Register
pattgen.CTRL0x104PATTGEN control register
pattgen.PREDIV_CH00x144PATTGEN pre-divider register for Channel 0
pattgen.PREDIV_CH10x184PATTGEN pre-divider register for Channel 1
pattgen.DATA_CH0_00x1c4PATTGEN seed pattern multi-registers for Channel 0.
pattgen.DATA_CH0_10x204PATTGEN seed pattern multi-registers for Channel 0.
pattgen.DATA_CH1_00x244PATTGEN seed pattern multi-registers for Channel 1.
pattgen.DATA_CH1_10x284PATTGEN seed pattern multi-registers for Channel 1.
pattgen.SIZE0x2c4PATTGEN pattern length

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw1c0x0done_ch1raise if pattern generation on Channel 1 is complete
0rw1c0x0done_ch0raise if pattern generation on Channel 0 is complete

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0done_ch1Enable interrupt when INTR_STATE.done_ch1 is set.
0rw0x0done_ch0Enable interrupt when INTR_STATE.done_ch0 is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0done_ch1Write 1 to force INTR_STATE.done_ch1 to 1.
0wo0x0done_ch0Write 1 to force INTR_STATE.done_ch0 to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

CTRL

PATTGEN control register

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw0x0POLARITY_CH1Clock (pcl) polarity for Channel 1. If low, pda signal changes on falling edge of pcl signal, otherwise pda changes on rising edge. Note that writes to a channel’s configuration registers have no effect while the channel is enabled.
2rw0x0POLARITY_CH0Clock (pcl) polarity for Channel 0. If low, pda signal changes on falling edge of pcl signal, otherwise pda changes on rising edge. Note that writes to a channel’s configuration registers have no effect while the channel is enabled.
1rw0x0ENABLE_CH1Enable pattern generator functionality for Channel 1
0rw0x0ENABLE_CH0Enable pattern generator functionality for Channel 0

PREDIV_CH0

PATTGEN pre-divider register for Channel 0

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0CLK_RATIOClock divider ratio fpr Channel 0 (relative to I/O clock). Note that writes to a channel’s configuration registers have no effect while the channel is enabled.

PREDIV_CH1

PATTGEN pre-divider register for Channel 1

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0CLK_RATIOClock divider ratio for Channel 1 (relative to I/O clock). Note that writes to a channel’s configuration registers have no effect while the channel is enabled.

DATA_CH0

PATTGEN seed pattern multi-registers for Channel 0.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
DATA_CH0_00x1c
DATA_CH0_10x20

Fields

BitsTypeResetNameDescription
31:0rw0x0DATASeed pattern for Channel 0 (1-64 bits). Note that writes to a channel’s configuration registers have no effect while the channel is enabled.

DATA_CH1

PATTGEN seed pattern multi-registers for Channel 1.

  • Reset default: 0x0
  • Reset mask: 0xffffffff

Instances

NameOffset
DATA_CH1_00x24
DATA_CH1_10x28

Fields

BitsTypeResetNameDescription
31:0rw0x0DATASeed pattern for Channel 1 (1-64 bits). Note that writes to a channel’s configuration registers have no effect while the channel is enabled.

SIZE

PATTGEN pattern length

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:22rw0x0REPS_CH1Number of pattern repetitions for Channel 1, minus 1. Valid values: 0..1023. Note that writes to a channel’s configuration registers have no effect while the channel is enabled.
21:16rw0x0LEN_CH1Length of the seed pattern for Channel 1, minus 1. Valid values: 0..63. Note that writes to a channel’s configuration registers have no effect while the channel is enabled.
15:6rw0x0REPS_CH0Number of pattern repetitions for Channel 0, minus 1. Valid values: 0..1023. Note that writes to a channel’s configuration registers have no effect while the channel is enabled.
5:0rw0x0LEN_CH0Length of the seed pattern for Channel 0, minus 1. Valid values: 0..63. Note that writes to a channel’s configuration registers have no effect while the channel is enabled.