Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module rv_core_ibex has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_edn_i, clk_esc_i, clk_otp_i

Bus Device Interfaces (TL-UL): cfg_tl_d

Bus Host Interfaces (TL-UL): corei_tl_h, cored_tl_h

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width
rst_cpu_n	logic	uni	req	1
ram_cfg	prim_ram_1p_pkg::ram_1p_cfg	uni	rcv	1
hart_id	logic	uni	rcv	32
boot_addr	logic	uni	rcv	32
irq_software	logic	uni	rcv	1
irq_timer	logic	uni	rcv	1
irq_external	logic	uni	rcv	1
esc_tx	prim_esc_pkg::esc_tx	uni	rcv	1
esc_rx	prim_esc_pkg::esc_rx	uni	req	1
debug_req	logic	uni	rcv	1
crash_dump	rv_core_ibex_pkg::cpu_crash_dump	uni	req	1
lc_cpu_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
pwrmgr_cpu_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
pwrmgr	pwrmgr_pkg::pwr_cpu	uni	req	1
nmi_wdog	logic	uni	rcv	1
edn	edn_pkg::edn	req_rsp	req	1
icache_otp_key	otp_ctrl_pkg::sram_otp_key	req_rsp	req	1
fpga_info	logic	uni	rcv	32
corei_tl_h	tlul_pkg::tl	req_rsp	req	1
cored_tl_h	tlul_pkg::tl	req_rsp	req	1
cfg_tl_d	tlul_pkg::tl	req_rsp	rsp	1

Interrupts: none

Security Alerts:

Alert Name	Description
fatal_sw_err	Software triggered alert for fatal faults
recov_sw_err	Software triggered Alert for recoverable faults
fatal_hw_err	Triggered when - Ibex raises `alert_major_internal_o` - Ibex raises `alert_major_bus_o` - A double fault is seen (Ibex raises `double_fault_seen_o`) - A bus integrity error is seen
recov_hw_err	Triggered when Ibex raises `alert_minor_o`

Security Countermeasures:

Countermeasure ID	Description
RV_CORE_IBEX.BUS.INTEGRITY	End-to-end bus integrity scheme.
RV_CORE_IBEX.SCRAMBLE.KEY.SIDELOAD	The scrambling key for the icache is sideloaded from OTP and thus unreadable by SW.
RV_CORE_IBEX.CORE.DATA_REG_SW.SCA	Data independent timing.
RV_CORE_IBEX.PC.CTRL_FLOW.CONSISTENCY	Correct PC increment check.
RV_CORE_IBEX.CTRL_FLOW.UNPREDICTABLE	Randomized dummy instruction insertion.
RV_CORE_IBEX.DATA_REG_SW.INTEGRITY	Register file integrity checking. Note that whilst the core itself is duplicated (see LOGIC.SHADOW) the register file is not. Protection is provided by an ECC.
RV_CORE_IBEX.DATA_REG_SW.GLITCH_DETECT	This countermeasure augments DATA_REG_SW.INTEGRITY and checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes.
RV_CORE_IBEX.LOGIC.SHADOW	Shadow core run in lockstep to crosscheck CPU behaviour. This provides broad protection for all assets with the the Ibex core.
RV_CORE_IBEX.FETCH.CTRL.LC_GATED	Fetch enable so core execution can be halted.
RV_CORE_IBEX.EXCEPTION.CTRL_FLOW.LOCAL_ESC	A mechanism to detect and act on double faults. Local escalation shuts down the core when a double fault is seen.
RV_CORE_IBEX.EXCEPTION.CTRL_FLOW.GLOBAL_ESC	A mechanism to detect and act on double faults. Global escalation sends a fatal alert when a double fault is seen.
RV_CORE_IBEX.ICACHE.MEM.SCRAMBLE	ICache memory scrambling.
RV_CORE_IBEX.ICACHE.MEM.INTEGRITY	ICache memory integrity checking.

Registers

Summary
Name	Offset	Length	Description
rv_core_ibex.ALERT_TEST	0x0	4	Alert Test Register
rv_core_ibex.SW_RECOV_ERR	0x4	4	Software recoverable error
rv_core_ibex.SW_FATAL_ERR	0x8	4	Software fatal error
rv_core_ibex.IBUS_REGWEN_0	0xc	4	Ibus address control regwen.
rv_core_ibex.IBUS_REGWEN_1	0x10	4	Ibus address control regwen.
rv_core_ibex.IBUS_ADDR_EN_0	0x14	4	Enable Ibus address matching
rv_core_ibex.IBUS_ADDR_EN_1	0x18	4	Enable Ibus address matching
rv_core_ibex.IBUS_ADDR_MATCHING_0	0x1c	4	Matching region programming for ibus.
rv_core_ibex.IBUS_ADDR_MATCHING_1	0x20	4	Matching region programming for ibus.
rv_core_ibex.IBUS_REMAP_ADDR_0	0x24	4	The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.
rv_core_ibex.IBUS_REMAP_ADDR_1	0x28	4	The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.
rv_core_ibex.DBUS_REGWEN_0	0x2c	4	Dbus address control regwen.
rv_core_ibex.DBUS_REGWEN_1	0x30	4	Dbus address control regwen.
rv_core_ibex.DBUS_ADDR_EN_0	0x34	4	Enable dbus address matching
rv_core_ibex.DBUS_ADDR_EN_1	0x38	4	Enable dbus address matching
rv_core_ibex.DBUS_ADDR_MATCHING_0	0x3c	4	See `IBUS_ADDR_MATCHING_0` for detailed description.
rv_core_ibex.DBUS_ADDR_MATCHING_1	0x40	4	See `IBUS_ADDR_MATCHING_0` for detailed description.
rv_core_ibex.DBUS_REMAP_ADDR_0	0x44	4	See `IBUS_REMAP_ADDR_0` for a detailed description.
rv_core_ibex.DBUS_REMAP_ADDR_1	0x48	4	See `IBUS_REMAP_ADDR_0` for a detailed description.
rv_core_ibex.NMI_ENABLE	0x4c	4	Enable mask for NMI. Once an enable mask is set, it cannot be disabled.
rv_core_ibex.NMI_STATE	0x50	4	Current NMI state
rv_core_ibex.ERR_STATUS	0x54	4	error status
rv_core_ibex.RND_DATA	0x58	4	Random data from EDN
rv_core_ibex.RND_STATUS	0x5c	4	Status of random data in `RND_DATA`
rv_core_ibex.FPGA_INFO	0x60	4	FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0.
rv_core_ibex.DV_SIM_WINDOW	0x80	32	Exposed tlul window for DV only purposes.

rv_core_ibex.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												recov_hw_err	fatal_hw_err	recov_sw_err	fatal_sw_err

Bits

Type

Reset

Name

Description

0x0

fatal_sw_err

Write 1 to trigger one alert event of this kind.

0x0

recov_sw_err

Write 1 to trigger one alert event of this kind.

0x0

fatal_hw_err

Write 1 to trigger one alert event of this kind.

0x0

recov_hw_err

Write 1 to trigger one alert event of this kind.

rv_core_ibex.SW_RECOV_ERR @ 0x4

Software recoverable error

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VAL

Bits

Type

Reset

Name

Description

3:0

0x9

VAL

Software recoverable alert. When set to any value other than kMultiBitBool4False, a recoverable alert is sent. Once the alert is sent, the field is then reset to kMultiBitBool4False.

rv_core_ibex.SW_FATAL_ERR @ 0x8

Software fatal error

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VAL

Bits

Type

Reset

Name

Description

3:0

rw0c

0x9

VAL

Software fatal alert. When set to any value other than kMultiBitBool4False, a fatal alert is sent. Note, this field once cleared cannot be set and will continuously cause alert events.

rv_core_ibex.IBUS_REGWEN_0 @ 0xc

Ibus address control regwen.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

0x0	locked	Address controls can no longer be configured until next reset.
0x1	enabled	Address controls can still be configured.

rv_core_ibex.IBUS_REGWEN_1 @ 0x10

Ibus address control regwen.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For IBUS_REGWEN1

rv_core_ibex.IBUS_ADDR_EN_0 @ 0x14

Enable Ibus address matching

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

0x0

EN_0

Enable ibus address matching.

rv_core_ibex.IBUS_ADDR_EN_1 @ 0x18

Enable Ibus address matching

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

0x0

EN_1

For IBUS_ADDR_CFG1

rv_core_ibex.IBUS_ADDR_MATCHING_0 @ 0x1c

Matching region programming for ibus.

Reset default = 0x0, mask 0xffffffff

The value programmed is done at power-of-2 alignment. For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.

The value programmed can be determined from the translation granule. Assume the user wishes to translate a specific 64KB block to a different address: 64KB has a hex value of 0x10000. Subtract 1 from this value and then right shift by one to obtain 0x7FFF. This value is then logically OR'd with the upper address bits that would select which 64KB to translate.

In this example, the user wishes to translate the 0x8000-th 64KB block. The value programmed is then 0x8000_7FFF.

If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL_0

Bits

Type

Reset

Name

Description

31:0

0x0

VAL_0

Matching region value

rv_core_ibex.IBUS_ADDR_MATCHING_1 @ 0x20

Matching region programming for ibus.

Reset default = 0x0, mask 0xffffffff

The value programmed is done at power-of-2 alignment. For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.

In this example, the user wishes to translate the 0x8000-th 64KB block. The value programmed is then 0x8000_7FFF.

If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL_1

Bits

Type

Reset

Name

Description

31:0

0x0

VAL_1

For IBUS_ADDR_MATCHING1

rv_core_ibex.IBUS_REMAP_ADDR_0 @ 0x24

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

Reset default = 0x0, mask 0xffffffff

For example, if the translation region is 64KB, the remapped address applies only to the upper address bits that select which 64KB to be translated.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL_0

Bits

Type

Reset

Name

Description

31:0

0x0

VAL_0

Remap addr value

rv_core_ibex.IBUS_REMAP_ADDR_1 @ 0x28

The remap address after a match has been made. The remap bits apply only to top portion of address bits not covered by the matching region.

Reset default = 0x0, mask 0xffffffff

For example, if the translation region is 64KB, the remapped address applies only to the upper address bits that select which 64KB to be translated.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL_1

Bits

Type

Reset

Name

Description

31:0

0x0

VAL_1

For IBUS_REMAP_ADDR1

rv_core_ibex.DBUS_REGWEN_0 @ 0x2c

Dbus address control regwen.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

Ibus address controls write enable. Once set to 0, it can longer be configured to 1

0x0	locked	Address controls can no longer be configured until next reset.
0x1	enabled	Address controls can still be configured.

rv_core_ibex.DBUS_REGWEN_1 @ 0x30

Dbus address control regwen.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For DBUS_REGWEN1

rv_core_ibex.DBUS_ADDR_EN_0 @ 0x34

Enable dbus address matching

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

0x0

EN_0

Enable dbus address matching.

rv_core_ibex.DBUS_ADDR_EN_1 @ 0x38

Enable dbus address matching

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

0x0

EN_1

For DBUS_ADDR_CFG1

rv_core_ibex.DBUS_ADDR_MATCHING_0 @ 0x3c

See IBUS_ADDR_MATCHING_0 for detailed description.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL_0

Bits Type Reset Name Description

31:0

0x0

VAL_0

Matching region value

rv_core_ibex.DBUS_ADDR_MATCHING_1 @ 0x40

See IBUS_ADDR_MATCHING_0 for detailed description.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL_1

Bits Type Reset Name Description

31:0

0x0

VAL_1

For DBUS_ADDR_MATCHING1

rv_core_ibex.DBUS_REMAP_ADDR_0 @ 0x44

See IBUS_REMAP_ADDR_0 for a detailed description.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL_0

Bits Type Reset Name Description

31:0

0x0

VAL_0

Remap addr value

rv_core_ibex.DBUS_REMAP_ADDR_1 @ 0x48

See IBUS_REMAP_ADDR_0 for a detailed description.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL_1

Bits Type Reset Name Description

31:0

0x0

VAL_1

For DBUS_REMAP_ADDR1

rv_core_ibex.NMI_ENABLE @ 0x4c

Enable mask for NMI. Once an enable mask is set, it cannot be disabled.

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														WDOG_EN	ALERT_EN

Bits

Type

Reset

Name

Description

rw1s

0x0

ALERT_EN

Enable mask for alert NMI

rw1s

0x0

WDOG_EN

Enable mask for watchdog NMI

rv_core_ibex.NMI_STATE @ 0x50

Current NMI state

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														WDOG	ALERT

Bits

Type

Reset

Name

Description

rw1c

0x0

ALERT

Current state for alert NMI

rw1c

0x0

WDOG

Current state for watchdog NMI

rv_core_ibex.ERR_STATUS @ 0x54

error status

Reset default = 0x0, mask 0x701

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					RECOV_CORE_ERR	FATAL_CORE_ERR	FATAL_INTG_ERR								REG_INTG_ERR

Bits Type Reset Name Description

rw1c

0x0

REG_INTG_ERR

rv_core_ibex_peri detected a register transmission integrity error

7:1 Reserved

rw1c

0x0

FATAL_INTG_ERR

rv_core_ibex detected a response integrity error

rw1c

0x0

FATAL_CORE_ERR

rv_core_ibex detected a fatal internal error (alert_major_internal_o from Ibex seen)

rw1c

0x0

RECOV_CORE_ERR

rv_core_ibex detected a recoverable internal error (alert_minor from Ibex seen)

rv_core_ibex.RND_DATA @ 0x58

Random data from EDN

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...DATA

Bits Type Reset Name Description

31:0

0x0

DATA

Random bits taken from the EDN. RND_STATUS.RND_DATA_VALID indicates if this data is valid. When valid, reading from this register invalidates the data and requests new data from the EDN. The register becomes valid again when the EDN provides new data. When invalid the register value will read as 0x0 with an EDN request for new data pending. Upon reset the data will be invalid with a new EDN request pending.

rv_core_ibex.RND_STATUS @ 0x5c

Status of random data in RND_DATA

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RND_DATA_FIPS	RND_DATA_VALID

Bits Type Reset Name Description

0x0

RND_DATA_VALID

When set, the data in RND_DATA is valid. When clear an EDN request for new data for RND_DATA is pending.

0x0

RND_DATA_FIPS

When RND_STATUS.RND_DATA_VALID is 1, this bit indicates whether RND_DATA is fips quality.

When RND_STATUS.RND_DATA_VALID is 0, this bit has no meaning.

rv_core_ibex.FPGA_INFO @ 0x60

FPGA build timestamp info. This register only contains valid data for fpga, for all other variants it is simply 0.

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VAL...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL

Bits

Type

Reset

Name

Description

31:0

0x0

VAL

FPGA build timestamp information.

rv_core_ibex.DV_SIM_WINDOW @ + 0x80

8 item rw window

Byte writes are supported

	31	0
+0x80
+0x84
	...
+0x98
+0x9c

Exposed tlul window for DV only purposes.

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers