Referring to the Comportable guideline for peripheral device functionality, the module rv_core_ibex
has the following hardware interfaces defined
- Primary Clock:
clk_i
- Other Clocks:
clk_edn_i
, clk_esc_i
, clk_otp_i
- Bus Device Interfaces (TL-UL):
cfg_tl_d
- Bus Host Interfaces (TL-UL):
corei_tl_h
, cored_tl_h
- Peripheral Pins for Chip IO: none
- Interrupts: none
Port Name | Package::Struct | Type | Act | Width | Description |
rst_cpu_n | logic | uni | req | 1 | |
ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
hart_id | logic | uni | rcv | 32 | |
boot_addr | logic | uni | rcv | 32 | |
irq_software | logic | uni | rcv | 1 | |
irq_timer | logic | uni | rcv | 1 | |
irq_external | logic | uni | rcv | 1 | |
esc_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | |
esc_rx | prim_esc_pkg::esc_rx | uni | req | 1 | |
debug_req | logic | uni | rcv | 1 | |
crash_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | req | 1 | |
lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
pwrmgr_cpu_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
pwrmgr | pwrmgr_pkg::pwr_cpu | uni | req | 1 | |
nmi_wdog | logic | uni | rcv | 1 | |
edn | edn_pkg::edn | req_rsp | req | 1 | |
icache_otp_key | otp_ctrl_pkg::sram_otp_key | req_rsp | req | 1 | |
fpga_info | logic | uni | rcv | 32 | |
corei_tl_h | tlul_pkg::tl | req_rsp | req | 1 | |
cored_tl_h | tlul_pkg::tl | req_rsp | req | 1 | |
cfg_tl_d | tlul_pkg::tl | req_rsp | rsp | 1 | |
Alert Name | Description |
fatal_sw_err | Software triggered alert for fatal faults |
recov_sw_err | Software triggered Alert for recoverable faults |
fatal_hw_err | Triggered when - Ibex raises alert_major_internal_o - Ibex raises alert_major_bus_o - A double fault is seen (Ibex raises double_fault_seen_o ) - A bus integrity error is seen |
recov_hw_err | Triggered when Ibex raises alert_minor_o |
Countermeasure ID | Description |
RV_CORE_IBEX.BUS.INTEGRITY | End-to-end bus integrity scheme. |
RV_CORE_IBEX.SCRAMBLE.KEY.SIDELOAD | The scrambling key for the icache is sideloaded from OTP and thus unreadable by SW. |
RV_CORE_IBEX.CORE.DATA_REG_SW.SCA | Data independent timing. |
RV_CORE_IBEX.PC.CTRL_FLOW.CONSISTENCY | Correct PC increment check. |
RV_CORE_IBEX.CTRL_FLOW.UNPREDICTABLE | Randomized dummy instruction insertion. |
RV_CORE_IBEX.DATA_REG_SW.INTEGRITY | Register file integrity checking. Note that whilst the core itself is duplicated (see LOGIC.SHADOW) the register file is not. Protection is provided by an ECC. |
RV_CORE_IBEX.DATA_REG_SW.GLITCH_DETECT | This countermeasure augments DATA_REG_SW.INTEGRITY and checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes. |
RV_CORE_IBEX.LOGIC.SHADOW | Shadow core run in lockstep to crosscheck CPU behaviour. This provides broad protection for all assets with the Ibex core. |
RV_CORE_IBEX.FETCH.CTRL.LC_GATED | Fetch enable so core execution can be halted. |
RV_CORE_IBEX.EXCEPTION.CTRL_FLOW.LOCAL_ESC | A mechanism to detect and act on double faults. Local escalation shuts down the core when a double fault is seen. |
RV_CORE_IBEX.EXCEPTION.CTRL_FLOW.GLOBAL_ESC | A mechanism to detect and act on double faults. Global escalation sends a fatal alert when a double fault is seen. |
RV_CORE_IBEX.ICACHE.MEM.SCRAMBLE | ICache memory scrambling. |
RV_CORE_IBEX.ICACHE.MEM.INTEGRITY | ICache memory integrity checking. |
Alert Test Register
- Offset:
0x0
- Reset default:
0x0
- Reset mask:
0xf
Bits | Type | Reset | Name | Description |
31:4 | | | | Reserved |
3 | wo | 0x0 | recov_hw_err | Write 1 to trigger one alert event of this kind. |
2 | wo | 0x0 | fatal_hw_err | Write 1 to trigger one alert event of this kind. |
1 | wo | 0x0 | recov_sw_err | Write 1 to trigger one alert event of this kind. |
0 | wo | 0x0 | fatal_sw_err | Write 1 to trigger one alert event of this kind. |
Software recoverable error
- Offset:
0x4
- Reset default:
0x9
- Reset mask:
0xf
Bits | Type | Reset | Name | Description |
31:4 | | | | Reserved |
3:0 | rw | 0x9 | VAL | Software recoverable alert. When set to any value other than kMultiBitBool4False, a recoverable alert is sent. Once the alert is sent, the field is then reset to kMultiBitBool4False. |
Software fatal error
- Offset:
0x8
- Reset default:
0x9
- Reset mask:
0xf
Bits | Type | Reset | Name | Description |
31:4 | | | | Reserved |
3:0 | rw0c | 0x9 | VAL | Software fatal alert. When set to any value other than kMultiBitBool4False, a fatal alert is sent. Note, this field once cleared cannot be set and will continuously cause alert events. |
Ibus address control regwen.
- Reset default:
0x1
- Reset mask:
0x1
Name | Offset |
IBUS_REGWEN_0 | 0xc |
IBUS_REGWEN_1 | 0x10 |
Bits | Type | Reset | Name |
31:1 | | | Reserved |
0 | rw0c | 0x1 | EN |
Ibus address controls write enable. Once set to 0, it can longer be configured to 1
Value | Name | Description |
0x0 | locked | Address controls can no longer be configured until next reset. |
0x1 | enabled | Address controls can still be configured. |
Enable Ibus address matching
- Reset default:
0x0
- Reset mask:
0x1
Name | Offset |
IBUS_ADDR_EN_0 | 0x14 |
IBUS_ADDR_EN_1 | 0x18 |
Bits | Type | Reset | Name | Description |
31:1 | | | | Reserved |
0 | rw | 0x0 | EN | Enable ibus address matching. |
Matching region programming for ibus.
The value programmed is done at power-of-2 alignment.
For example, if the intended matching region is 0x8000_0000 to 0x8000_FFFF, the value programmed is 0x8000_7FFF.
The value programmed can be determined from the translation granule.
Assume the user wishes to translate a specific 64KB block to a different address:
64KB has a hex value of 0x10000.
Subtract 1 from this value and then right shift by one to obtain 0x7FFF.
This value is then logically OR’d with the upper address bits that would select which 64KB to translate.
In this example, the user wishes to translate the 0x8000-th 64KB block.
The value programmed is then 0x8000_7FFF.
If the user were to translate the 0x8001-th 64KB block, the value programmed would be 0x8001_7FFF.
- Reset default:
0x0
- Reset mask:
0xffffffff
Name | Offset |
IBUS_ADDR_MATCHING_0 | 0x1c |
IBUS_ADDR_MATCHING_1 | 0x20 |
Bits | Type | Reset | Name | Description |
31:0 | rw | 0x0 | VAL | Matching region value |
The remap address after a match has been made.
The remap bits apply only to top portion of address bits not covered by the matching region.
For example, if the translation region is 64KB, the remapped address applies only to the upper
address bits that select which 64KB to be translated.
- Reset default:
0x0
- Reset mask:
0xffffffff
Name | Offset |
IBUS_REMAP_ADDR_0 | 0x24 |
IBUS_REMAP_ADDR_1 | 0x28 |
Bits | Type | Reset | Name | Description |
31:0 | rw | 0x0 | VAL | Remap addr value |
Dbus address control regwen.
- Reset default:
0x1
- Reset mask:
0x1
Name | Offset |
DBUS_REGWEN_0 | 0x2c |
DBUS_REGWEN_1 | 0x30 |
Bits | Type | Reset | Name |
31:1 | | | Reserved |
0 | rw0c | 0x1 | EN |
Ibus address controls write enable. Once set to 0, it can longer be configured to 1
Value | Name | Description |
0x0 | locked | Address controls can no longer be configured until next reset. |
0x1 | enabled | Address controls can still be configured. |
Enable dbus address matching
- Reset default:
0x0
- Reset mask:
0x1
Name | Offset |
DBUS_ADDR_EN_0 | 0x34 |
DBUS_ADDR_EN_1 | 0x38 |
Bits | Type | Reset | Name | Description |
31:1 | | | | Reserved |
0 | rw | 0x0 | EN | Enable dbus address matching. |
See IBUS_ADDR_MATCHING_0
for detailed description.
- Reset default:
0x0
- Reset mask:
0xffffffff
Name | Offset |
DBUS_ADDR_MATCHING_0 | 0x3c |
DBUS_ADDR_MATCHING_1 | 0x40 |
Bits | Type | Reset | Name | Description |
31:0 | rw | 0x0 | VAL | Matching region value |
See IBUS_REMAP_ADDR_0
for a detailed description.
- Reset default:
0x0
- Reset mask:
0xffffffff
Name | Offset |
DBUS_REMAP_ADDR_0 | 0x44 |
DBUS_REMAP_ADDR_1 | 0x48 |
Bits | Type | Reset | Name | Description |
31:0 | rw | 0x0 | VAL | Remap addr value |
Enable mask for NMI.
Once an enable mask is set, it cannot be disabled.
- Offset:
0x4c
- Reset default:
0x0
- Reset mask:
0x3
Bits | Type | Reset | Name | Description |
31:2 | | | | Reserved |
1 | rw1s | 0x0 | WDOG_EN | Enable mask for watchdog NMI |
0 | rw1s | 0x0 | ALERT_EN | Enable mask for alert NMI |
Current NMI state
- Offset:
0x50
- Reset default:
0x0
- Reset mask:
0x3
Bits | Type | Reset | Name | Description |
31:2 | | | | Reserved |
1 | rw1c | 0x0 | WDOG | Current state for watchdog NMI |
0 | rw1c | 0x0 | ALERT | Current state for alert NMI |
error status
- Offset:
0x54
- Reset default:
0x0
- Reset mask:
0x701
Bits | Type | Reset | Name | Description |
31:11 | | | | Reserved |
10 | rw1c | 0x0 | RECOV_CORE_ERR | rv_core_ibex detected a recoverable internal error (alert_minor from Ibex seen) |
9 | rw1c | 0x0 | FATAL_CORE_ERR | rv_core_ibex detected a fatal internal error (alert_major_internal_o from Ibex seen) |
8 | rw1c | 0x0 | FATAL_INTG_ERR | rv_core_ibex detected a response integrity error |
7:1 | | | | Reserved |
0 | rw1c | 0x0 | REG_INTG_ERR | rv_core_ibex_peri detected a register transmission integrity error |
Random data from EDN
- Offset:
0x58
- Reset default:
0x0
- Reset mask:
0xffffffff
Bits | Type | Reset | Name |
31:0 | ro | 0x0 | DATA |
Random bits taken from the EDN. RND_STATUS.RND_DATA_VALID
indicates if this data is valid. When valid, reading from this
register invalidates the data and requests new data from the EDN.
The register becomes valid again when the EDN provides new data.
When invalid the register value will read as 0x0 with an EDN
request for new data pending. Upon reset the data will be invalid
with a new EDN request pending.
Status of random data in RND_DATA
- Offset:
0x5c
- Reset default:
0x0
- Reset mask:
0x3
FPGA build timestamp info.
This register only contains valid data for fpga, for all other variants it is simply 0.
- Offset:
0x60
- Reset default:
0x0
- Reset mask:
0xffffffff
Bits | Type | Reset | Name | Description |
31:0 | ro | 0x0 | VAL | FPGA build timestamp information. |
Exposed tlul window for DV only purposes.
- Word Aligned Offset Range:
0x80
to0x9c
- Size (words):
8
- Access:
rw
- Byte writes are supported.