Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module uart has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin name	direction	Description
rx	input	Serial receive bit
tx	output	Serial transmit bit

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width	Description
tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts:

Interrupt Name	Type	Description
tx_watermark	Event	raised if the transmit FIFO is past the high-water mark.
rx_watermark	Event	raised if the receive FIFO is past the high-water mark.
tx_empty	Event	raised if the transmit FIFO has emptied and no transmit is ongoing.
rx_overflow	Event	raised if the receive FIFO has overflowed.
rx_frame_err	Event	raised if a framing error has been detected on receive.
rx_break_err	Event	raised if break condition has been detected on receive.
rx_timeout	Event	raised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.
rx_parity_err	Event	raised if the receiver has detected a parity error.

Security Alerts:

Alert Name	Description
fatal_fault	This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure ID	Description
UART.BUS.INTEGRITY	End-to-end bus integrity scheme.

Registers

Summary
Name	Offset	Length	Description
uart.INTR_STATE	0x0	4	Interrupt State Register
uart.INTR_ENABLE	0x4	4	Interrupt Enable Register
uart.INTR_TEST	0x8	4	Interrupt Test Register
uart.ALERT_TEST	0xc	4	Alert Test Register
uart.CTRL	0x10	4	UART control register
uart.STATUS	0x14	4	UART live status register
uart.RDATA	0x18	4	UART read data
uart.WDATA	0x1c	4	UART write data
uart.FIFO_CTRL	0x20	4	UART FIFO control register
uart.FIFO_STATUS	0x24	4	UART FIFO status register
uart.OVRD	0x28	4	TX pin override control. Gives direct SW control over TX pin state
uart.VAL	0x2c	4	UART oversampled values
uart.TIMEOUT_CTRL	0x30	4	UART RX timeout control

uart.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								rx_parity_err	rx_timeout	rx_break_err	rx_frame_err	rx_overflow	tx_empty	rx_watermark	tx_watermark

Bits

Type

Reset

Name

Description

rw1c

0x0

tx_watermark

raised if the transmit FIFO is past the high-water mark.

rw1c

0x0

rx_watermark

raised if the receive FIFO is past the high-water mark.

rw1c

0x0

tx_empty

raised if the transmit FIFO has emptied and no transmit is ongoing.

rw1c

0x0

rx_overflow

raised if the receive FIFO has overflowed.

rw1c

0x0

rx_frame_err

raised if a framing error has been detected on receive.

rw1c

0x0

rx_break_err

raised if break condition has been detected on receive.

rw1c

0x0

rx_timeout

raised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.

rw1c

0x0

rx_parity_err

raised if the receiver has detected a parity error.

uart.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								rx_parity_err	rx_timeout	rx_break_err	rx_frame_err	rx_overflow	tx_empty	rx_watermark	tx_watermark

Bits Type Reset Name Description

0x0

tx_watermark

Enable interrupt when INTR_STATE.tx_watermark is set.

0x0

rx_watermark

Enable interrupt when INTR_STATE.rx_watermark is set.

0x0

tx_empty

Enable interrupt when INTR_STATE.tx_empty is set.

0x0

rx_overflow

Enable interrupt when INTR_STATE.rx_overflow is set.

0x0

rx_frame_err

Enable interrupt when INTR_STATE.rx_frame_err is set.

0x0

rx_break_err

Enable interrupt when INTR_STATE.rx_break_err is set.

0x0

rx_timeout

Enable interrupt when INTR_STATE.rx_timeout is set.

0x0

rx_parity_err

Enable interrupt when INTR_STATE.rx_parity_err is set.

uart.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								rx_parity_err	rx_timeout	rx_break_err	rx_frame_err	rx_overflow	tx_empty	rx_watermark	tx_watermark

Bits Type Reset Name Description

0x0

tx_watermark

Write 1 to force INTR_STATE.tx_watermark to 1.

0x0

rx_watermark

Write 1 to force INTR_STATE.rx_watermark to 1.

0x0

tx_empty

Write 1 to force INTR_STATE.tx_empty to 1.

0x0

rx_overflow

Write 1 to force INTR_STATE.rx_overflow to 1.

0x0

rx_frame_err

Write 1 to force INTR_STATE.rx_frame_err to 1.

0x0

rx_break_err

Write 1 to force INTR_STATE.rx_break_err to 1.

0x0

rx_timeout

Write 1 to force INTR_STATE.rx_timeout to 1.

0x0

rx_parity_err

Write 1 to force INTR_STATE.rx_parity_err to 1.

uart.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															fatal_fault

Bits

Type

Reset

Name

Description

0x0

fatal_fault

Write 1 to trigger one alert event of this kind.

uart.CTRL @ 0x10

UART control register

Reset default = 0x0, mask 0xffff03f7

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NCO
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						RXBLVL		PARITY_ODD	PARITY_EN	LLPBK	SLPBK		NF	RX	TX

Bits

Type

Reset

Name

Description

0x0

TX enable

0x0

RX enable

0x0

RX noise filter enable. If the noise filter is enabled, RX line goes through the 3-tap repetition code. It ignores single IP clock period noise.

Reserved

0x0

SLPBK

System loopback enable.

If this bit is turned on, any outgoing bits to TX are received through RX. See Block Diagram. Note that the TX line goes 1 if System loopback is enabled.

0x0

LLPBK

Line loopback enable.

If this bit is turned on, incoming bits are forwarded to TX for testing purpose. See Block Diagram. Note that the internal design sees RX value as 1 always if line loopback is enabled.

0x0

PARITY_EN

If true, parity is enabled in both RX and TX directions.

0x0

PARITY_ODD

If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even.

9:8

0x0

RXBLVL

Trigger level for RX break detection. Sets the number of character times the line must be low to detect a break.

0x0	break2	2 characters
0x1	break4	4 characters
0x2	break8	8 characters
0x3	break16	16 characters

15:10

Reserved

31:16

0x0

NCO

BAUD clock rate control.

uart.STATUS @ 0x14

UART live status register

Reset default = 0x3c, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										RXEMPTY	RXIDLE	TXIDLE	TXEMPTY	RXFULL	TXFULL

Bits

Type

Reset

Name

Description

TXFULL

TX buffer is full

RXFULL

RX buffer is full

0x1

TXEMPTY

TX FIFO is empty

0x1

TXIDLE

TX FIFO is empty and all bits have been transmitted

0x1

RXIDLE

RX is idle

0x1

RXEMPTY

RX FIFO is empty

uart.RDATA @ 0x18

UART read data

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RDATA

Bits

Type

Reset

Name

Description

7:0

RDATA

uart.WDATA @ 0x1c

UART write data

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDATA

Bits

Type

Reset

Name

Description

7:0

0x0

WDATA

uart.FIFO_CTRL @ 0x20

UART FIFO control register

Reset default = 0x0, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TXILVL		RXILVL			TXRST	RXRST

Bits

Type

Reset

Name

Description

0x0

RXRST

RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0

0x0

TXRST

TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0

4:2

0x0

RXILVL

Trigger level for RX interrupts. If the FIFO depth is greater than or equal to the setting, it raises rx_watermark interrupt.

0x0	rxlvl1	1 character
0x1	rxlvl4	4 characters
0x2	rxlvl8	8 characters
0x3	rxlvl16	16 characters
0x4	rxlvl30	30 characters

Other values are reserved.

6:5

0x0

TXILVL

Trigger level for TX interrupts. If the FIFO depth is less than the setting, it raises tx_watermark interrupt.

0x0	txlvl1	2 characters
0x1	txlvl4	4 characters
0x2	txlvl8	8 characters
0x3	txlvl16	16 characters

uart.FIFO_STATUS @ 0x24

UART FIFO status register

Reset default = 0x0, mask 0x3f003f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										RXLVL
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TXLVL

Bits

Type

Reset

Name

Description

5:0

TXLVL

Current fill level of TX fifo

15:6

Reserved

21:16

RXLVL

Current fill level of RX fifo

uart.OVRD @ 0x28

TX pin override control. Gives direct SW control over TX pin state

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TXVAL	TXEN

Bits

Type

Reset

Name

Description

0x0

TXEN

Enable TX pin override control

0x0

TXVAL

Write to set the value of the TX pin

uart.VAL @ 0x2c

UART oversampled values

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RX

Bits

Type

Reset

Name

Description

15:0

Last 16 oversampled values of RX. Most recent bit is bit 0, oldest 15.

uart.TIMEOUT_CTRL @ 0x30

UART RX timeout control

Reset default = 0x0, mask 0x80ffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EN								VAL...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...VAL

Bits

Type

Reset

Name

Description

23:0

0x0

VAL

RX timeout value in UART bit times

30:24

Reserved

0x0

Enable RX timeout feature

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers