Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module uart has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
rxinput

Serial receive bit

txoutput

Serial transmit bit

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
tx_watermarkEvent

raised if the transmit FIFO is past the high-water mark.

rx_watermarkEvent

raised if the receive FIFO is past the high-water mark.

tx_emptyEvent

raised if the transmit FIFO has emptied and no transmit is ongoing.

rx_overflowEvent

raised if the receive FIFO has overflowed.

rx_frame_errEvent

raised if a framing error has been detected on receive.

rx_break_errEvent

raised if break condition has been detected on receive.

rx_timeoutEvent

raised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.

rx_parity_errEvent

raised if the receiver has detected a parity error.

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
UART.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
uart.INTR_STATE 0x0 4

Interrupt State Register

uart.INTR_ENABLE 0x4 4

Interrupt Enable Register

uart.INTR_TEST 0x8 4

Interrupt Test Register

uart.ALERT_TEST 0xc 4

Alert Test Register

uart.CTRL 0x10 4

UART control register

uart.STATUS 0x14 4

UART live status register

uart.RDATA 0x18 4

UART read data

uart.WDATA 0x1c 4

UART write data

uart.FIFO_CTRL 0x20 4

UART FIFO control register

uart.FIFO_STATUS 0x24 4

UART FIFO status register

uart.OVRD 0x28 4

TX pin override control. Gives direct SW control over TX pin state

uart.VAL 0x2c 4

UART oversampled values

uart.TIMEOUT_CTRL 0x30 4

UART RX timeout control

uart.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0xff
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  rx_parity_err rx_timeout rx_break_err rx_frame_err rx_overflow tx_empty rx_watermark tx_watermark
BitsTypeResetNameDescription
0rw1c0x0tx_watermark

raised if the transmit FIFO is past the high-water mark.

1rw1c0x0rx_watermark

raised if the receive FIFO is past the high-water mark.

2rw1c0x0tx_empty

raised if the transmit FIFO has emptied and no transmit is ongoing.

3rw1c0x0rx_overflow

raised if the receive FIFO has overflowed.

4rw1c0x0rx_frame_err

raised if a framing error has been detected on receive.

5rw1c0x0rx_break_err

raised if break condition has been detected on receive.

6rw1c0x0rx_timeout

raised if RX FIFO has characters remaining in the FIFO without being retrieved for the programmed time period.

7rw1c0x0rx_parity_err

raised if the receiver has detected a parity error.


uart.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0xff
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  rx_parity_err rx_timeout rx_break_err rx_frame_err rx_overflow tx_empty rx_watermark tx_watermark
BitsTypeResetNameDescription
0rw0x0tx_watermark

Enable interrupt when INTR_STATE.tx_watermark is set.

1rw0x0rx_watermark

Enable interrupt when INTR_STATE.rx_watermark is set.

2rw0x0tx_empty

Enable interrupt when INTR_STATE.tx_empty is set.

3rw0x0rx_overflow

Enable interrupt when INTR_STATE.rx_overflow is set.

4rw0x0rx_frame_err

Enable interrupt when INTR_STATE.rx_frame_err is set.

5rw0x0rx_break_err

Enable interrupt when INTR_STATE.rx_break_err is set.

6rw0x0rx_timeout

Enable interrupt when INTR_STATE.rx_timeout is set.

7rw0x0rx_parity_err

Enable interrupt when INTR_STATE.rx_parity_err is set.


uart.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0xff
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  rx_parity_err rx_timeout rx_break_err rx_frame_err rx_overflow tx_empty rx_watermark tx_watermark
BitsTypeResetNameDescription
0wo0x0tx_watermark

Write 1 to force INTR_STATE.tx_watermark to 1.

1wo0x0rx_watermark

Write 1 to force INTR_STATE.rx_watermark to 1.

2wo0x0tx_empty

Write 1 to force INTR_STATE.tx_empty to 1.

3wo0x0rx_overflow

Write 1 to force INTR_STATE.rx_overflow to 1.

4wo0x0rx_frame_err

Write 1 to force INTR_STATE.rx_frame_err to 1.

5wo0x0rx_break_err

Write 1 to force INTR_STATE.rx_break_err to 1.

6wo0x0rx_timeout

Write 1 to force INTR_STATE.rx_timeout to 1.

7wo0x0rx_parity_err

Write 1 to force INTR_STATE.rx_parity_err to 1.


uart.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


uart.CTRL @ 0x10

UART control register

Reset default = 0x0, mask 0xffff03f7
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NCO
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  RXBLVL PARITY_ODD PARITY_EN LLPBK SLPBK   NF RX TX
BitsTypeResetNameDescription
0rw0x0TX

TX enable

1rw0x0RX

RX enable

2rw0x0NF

RX noise filter enable. If the noise filter is enabled, RX line goes through the 3-tap repetition code. It ignores single IP clock period noise.

3Reserved
4rw0x0SLPBK

System loopback enable.

If this bit is turned on, any outgoing bits to TX are received through RX. See Block Diagram. Note that the TX line goes 1 if System loopback is enabled.

5rw0x0LLPBK

Line loopback enable.

If this bit is turned on, incoming bits are forwarded to TX for testing purpose. See Block Diagram. Note that the internal design sees RX value as 1 always if line loopback is enabled.

6rw0x0PARITY_EN

If true, parity is enabled in both RX and TX directions.

7rw0x0PARITY_ODD

If PARITY_EN is true, this determines the type, 1 for odd parity, 0 for even.

9:8rw0x0RXBLVL

Trigger level for RX break detection. Sets the number of character times the line must be low to detect a break.

0x0break2

2 characters

0x1break4

4 characters

0x2break8

8 characters

0x3break16

16 characters

15:10Reserved
31:16rw0x0NCO

BAUD clock rate control.


uart.STATUS @ 0x14

UART live status register

Reset default = 0x3c, mask 0x3f
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  RXEMPTY RXIDLE TXIDLE TXEMPTY RXFULL TXFULL
BitsTypeResetNameDescription
0roxTXFULL

TX buffer is full

1roxRXFULL

RX buffer is full

2ro0x1TXEMPTY

TX FIFO is empty

3ro0x1TXIDLE

TX FIFO is empty and all bits have been transmitted

4ro0x1RXIDLE

RX is idle

5ro0x1RXEMPTY

RX FIFO is empty


uart.RDATA @ 0x18

UART read data

Reset default = 0x0, mask 0xff
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  RDATA
BitsTypeResetNameDescription
7:0roxRDATA

uart.WDATA @ 0x1c

UART write data

Reset default = 0x0, mask 0xff
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  WDATA
BitsTypeResetNameDescription
7:0wo0x0WDATA

uart.FIFO_CTRL @ 0x20

UART FIFO control register

Reset default = 0x0, mask 0x7f
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  TXILVL RXILVL TXRST RXRST
BitsTypeResetNameDescription
0wo0x0RXRST

RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0

1wo0x0TXRST

TX fifo reset. Write 1 to the register resets TX_FIFO. Read returns 0

4:2rw0x0RXILVL

Trigger level for RX interrupts. If the FIFO depth is greater than or equal to the setting, it raises rx_watermark interrupt.

0x0rxlvl1

1 character

0x1rxlvl4

4 characters

0x2rxlvl8

8 characters

0x3rxlvl16

16 characters

0x4rxlvl30

30 characters

Other values are reserved.

6:5rw0x0TXILVL

Trigger level for TX interrupts. If the FIFO depth is less than the setting, it raises tx_watermark interrupt.

0x0txlvl1

2 characters

0x1txlvl4

4 characters

0x2txlvl8

8 characters

0x3txlvl16

16 characters


uart.FIFO_STATUS @ 0x24

UART FIFO status register

Reset default = 0x0, mask 0x3f003f
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  RXLVL
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  TXLVL
BitsTypeResetNameDescription
5:0roxTXLVL

Current fill level of TX fifo

15:6Reserved
21:16roxRXLVL

Current fill level of RX fifo


uart.OVRD @ 0x28

TX pin override control. Gives direct SW control over TX pin state

Reset default = 0x0, mask 0x3
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  TXVAL TXEN
BitsTypeResetNameDescription
0rw0x0TXEN

Enable TX pin override control

1rw0x0TXVAL

Write to set the value of the TX pin


uart.VAL @ 0x2c

UART oversampled values

Reset default = 0x0, mask 0xffff
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RX
BitsTypeResetNameDescription
15:0roxRX

Last 16 oversampled values of RX. Most recent bit is bit 0, oldest 15.


uart.TIMEOUT_CTRL @ 0x30

UART RX timeout control

Reset default = 0x0, mask 0x80ffffff
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EN   VAL...
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...VAL
BitsTypeResetNameDescription
23:0rw0x0VAL

RX timeout value in UART bit times

30:24Reserved
31rw0x0EN

Enable RX timeout feature