Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module sysrst_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin name	direction	Description
ac_present	input	A/C power is present
key0_in	input	VolUp button in tablet; column output from the EC in a laptop
key1_in	input	VolDown button in tablet; row input from keyboard matrix in a laptop
key2_in	input	TBD button in tablet; row input from keyboard matrix in a laptop
pwrb_in	input	Power button in both tablet and laptop
lid_open	input	Lid is open
bat_disable	output	Battery is disconnected
key0_out	output	Passthrough from key0_in, can be configured to invert
key1_out	output	Passthrough from key1_in, can be configured to invert
key2_out	output	Passthrough from key2_in, can be configured to invert
pwrb_out	output	Passthrough from pwrb_in, can be configured to invert
z3_wakeup	output	To enter Z3 mode and exit from Z4 sleep mode
ec_rst_l	inout	ec_rst_l as an inout to/from the open drain IO
flash_wp_l	inout	flash_wp_l as an inout to/from the open drain IO

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width
wkup_req	logic	uni	req	1
rst_req	logic	uni	req	1
tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts:

Interrupt Name	Type	Description
event_detected	Event	Common interrupt triggered by combo or keyboard events.

Security Alerts:

Alert Name	Description
fatal_fault	This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure ID	Description
SYSRST_CTRL.BUS.INTEGRITY	End-to-end bus integrity scheme.

Registers

Summary
Name	Offset	Length	Description
sysrst_ctrl.INTR_STATE	0x0	4	Interrupt State Register
sysrst_ctrl.INTR_ENABLE	0x4	4	Interrupt Enable Register
sysrst_ctrl.INTR_TEST	0x8	4	Interrupt Test Register
sysrst_ctrl.ALERT_TEST	0xc	4	Alert Test Register
sysrst_ctrl.REGWEN	0x10	4	Configuration write enable control register
sysrst_ctrl.EC_RST_CTL	0x14	4	EC reset control register
sysrst_ctrl.ULP_AC_DEBOUNCE_CTL	0x18	4	Ultra low power AC debounce control register
sysrst_ctrl.ULP_LID_DEBOUNCE_CTL	0x1c	4	Ultra low power lid debounce control register
sysrst_ctrl.ULP_PWRB_DEBOUNCE_CTL	0x20	4	Ultra low power pwrb debounce control register
sysrst_ctrl.ULP_CTL	0x24	4	Ultra low power control register
sysrst_ctrl.ULP_STATUS	0x28	4	Ultra low power status
sysrst_ctrl.WKUP_STATUS	0x2c	4	wakeup status
sysrst_ctrl.KEY_INVERT_CTL	0x30	4	configure key input output invert property
sysrst_ctrl.PIN_ALLOWED_CTL	0x34	4	This register determines which override values are allowed for a given output. If an override value programmed via `PIN_OUT_VALUE` is not configured as an allowed value, it will not have any effect.
sysrst_ctrl.PIN_OUT_CTL	0x38	4	Enables the override function for a specific pin.
sysrst_ctrl.PIN_OUT_VALUE	0x3c	4	Sets the pin override value. Note that only the values configured as 'allowed' in `PIN_ALLOWED_CTL` will have an effect. Otherwise the pin value will not be overridden.
sysrst_ctrl.PIN_IN_VALUE	0x40	4	For SW to read the sysrst_ctrl inputs like GPIO
sysrst_ctrl.KEY_INTR_CTL	0x44	4	Define the keys or inputs that can trigger the interrupt
sysrst_ctrl.KEY_INTR_DEBOUNCE_CTL	0x48	4	Debounce timer control register for key-triggered interrupt
sysrst_ctrl.AUTO_BLOCK_DEBOUNCE_CTL	0x4c	4	Debounce timer control register for pwrb_in H2L transition
sysrst_ctrl.AUTO_BLOCK_OUT_CTL	0x50	4	configure the key outputs to auto-override and their value
sysrst_ctrl.COM_PRE_SEL_CTL_0	0x54	4	To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by `COM_SEL_CTL` if this precondition is fulfilled.
sysrst_ctrl.COM_PRE_SEL_CTL_1	0x58	4	To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by `COM_SEL_CTL` if this precondition is fulfilled.
sysrst_ctrl.COM_PRE_SEL_CTL_2	0x5c	4	To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by `COM_SEL_CTL` if this precondition is fulfilled.
sysrst_ctrl.COM_PRE_SEL_CTL_3	0x60	4	To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by `COM_SEL_CTL` if this precondition is fulfilled.
sysrst_ctrl.COM_PRE_DET_CTL_0	0x64	4	To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)
sysrst_ctrl.COM_PRE_DET_CTL_1	0x68	4	To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)
sysrst_ctrl.COM_PRE_DET_CTL_2	0x6c	4	To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)
sysrst_ctrl.COM_PRE_DET_CTL_3	0x70	4	To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)
sysrst_ctrl.COM_SEL_CTL_0	0x74	4	To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.
sysrst_ctrl.COM_SEL_CTL_1	0x78	4	To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.
sysrst_ctrl.COM_SEL_CTL_2	0x7c	4	To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.
sysrst_ctrl.COM_SEL_CTL_3	0x80	4	To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.
sysrst_ctrl.COM_DET_CTL_0	0x84	4	To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)
sysrst_ctrl.COM_DET_CTL_1	0x88	4	To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)
sysrst_ctrl.COM_DET_CTL_2	0x8c	4	To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)
sysrst_ctrl.COM_DET_CTL_3	0x90	4	To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)
sysrst_ctrl.COM_OUT_CTL_0	0x94	4	To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)
sysrst_ctrl.COM_OUT_CTL_1	0x98	4	To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)
sysrst_ctrl.COM_OUT_CTL_2	0x9c	4	To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)
sysrst_ctrl.COM_OUT_CTL_3	0xa0	4	To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)
sysrst_ctrl.COMBO_INTR_STATUS	0xa4	4	Combo interrupt source. These registers will only be set if the interrupt action is configured in the corresponding `COM_OUT_CTL` register.
sysrst_ctrl.KEY_INTR_STATUS	0xa8	4	key interrupt source

sysrst_ctrl.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															event_detected

Bits

Type

Reset

Name

Description

rw1c

0x0

event_detected

Common interrupt triggered by combo or keyboard events.

sysrst_ctrl.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															event_detected

Bits Type Reset Name Description

0x0

event_detected

Enable interrupt when INTR_STATE.event_detected is set.

sysrst_ctrl.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															event_detected

Bits Type Reset Name Description

0x0

event_detected

Write 1 to force INTR_STATE.event_detected to 1.

sysrst_ctrl.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															fatal_fault

Bits

Type

Reset

Name

Description

0x0

fatal_fault

Write 1 to trigger one alert event of this kind.

sysrst_ctrl.REGWEN @ 0x10

Configuration write enable control register

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															write_en

Bits

Type

Reset

Name

Description

rw0c

0x1

write_en

config write enable. 0: cfg is locked(not writable); 1: cfg is not locked(writable)

sysrst_ctrl.EC_RST_CTL @ 0x14

EC reset control register

Reset default = 0x7d0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ec_rst_pulse

Bits

Type

Reset

Name

Description

15:0

0x7d0

ec_rst_pulse

Configure the debounce timer in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

sysrst_ctrl.ULP_AC_DEBOUNCE_CTL @ 0x18

Ultra low power AC debounce control register

Reset default = 0x1f40, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ulp_ac_debounce_timer

Bits

Type

Reset

Name

Description

15:0

0x1f40

ulp_ac_debounce_timer

Configure the debounce timer for the AC input in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

sysrst_ctrl.ULP_LID_DEBOUNCE_CTL @ 0x1c

Ultra low power lid debounce control register

Reset default = 0x1f40, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ulp_lid_debounce_timer

Bits

Type

Reset

Name

Description

15:0

0x1f40

ulp_lid_debounce_timer

Configure the debounce timer for the lid in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

sysrst_ctrl.ULP_PWRB_DEBOUNCE_CTL @ 0x20

Ultra low power pwrb debounce control register

Reset default = 0x1f40, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ulp_pwrb_debounce_timer

Bits

Type

Reset

Name

Description

15:0

0x1f40

ulp_pwrb_debounce_timer

Configure the debounce timer for the power button in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

sysrst_ctrl.ULP_CTL @ 0x24

Ultra low power control register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															ulp_enable

Bits

Type

Reset

Name

Description

0x0

ulp_enable

0: disable ULP wakeup feature and reset the ULP FSM; 1: enable ULP wakeup feature

sysrst_ctrl.ULP_STATUS @ 0x28

Ultra low power status

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															ulp_wakeup

Bits

Type

Reset

Name

Description

rw1c

0x0

ulp_wakeup

0: ULP wakeup not detected; 1: ULP wakeup event is detected

sysrst_ctrl.WKUP_STATUS @ 0x2c

wakeup status

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															wakeup_sts

Bits

Type

Reset

Name

Description

rw1c

0x0

wakeup_sts

0: wakeup event not detected; 1: wakeup event is detected

sysrst_ctrl.KEY_INVERT_CTL @ 0x30

configure key input output invert property

Reset default = 0x0, mask 0xfff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				z3_wakeup	lid_open	bat_disable	ac_present	pwrb_out	pwrb_in	key2_out	key2_in	key1_out	key1_in	key0_out	key0_in

Bits

Type

Reset

Name

Description

0x0

key0_in

0: don't invert; 1: invert

0x0

key0_out

0: don't invert; 1: invert

0x0

key1_in

0: don't invert; 1: invert

0x0

key1_out

0: don't invert; 1: invert

0x0

key2_in

0: don't invert; 1: invert

0x0

key2_out

0: don't invert; 1: invert

0x0

pwrb_in

0: don't invert; 1: invert

0x0

pwrb_out

0: don't invert; 1: invert

0x0

ac_present

0: don't invert; 1: invert

0x0

bat_disable

0: don't invert; 1: invert

0x0

lid_open

0: don't invert; 1: invert

0x0

z3_wakeup

0: don't invert; 1: invert

sysrst_ctrl.PIN_ALLOWED_CTL @ 0x34

This register determines which override values are allowed for a given output. If an override value programmed via PIN_OUT_VALUE is not configured as an allowed value, it will not have any effect.

Reset default = 0x82, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
flash_wp_l_1	z3_wakeup_1	key2_out_1	key1_out_1	key0_out_1	pwrb_out_1	ec_rst_l_1	bat_disable_1	flash_wp_l_0	z3_wakeup_0	key2_out_0	key1_out_0	key0_out_0	pwrb_out_0	ec_rst_l_0	bat_disable_0

Bits Type Reset Name Description

0x0

bat_disable_0

0: not allowed; 1: allowed

0x1

ec_rst_l_0

0: not allowed; 1: allowed

0x0

pwrb_out_0

0: not allowed; 1: allowed

0x0

key0_out_0

0: not allowed; 1: allowed

0x0

key1_out_0

0: not allowed; 1: allowed

0x0

key2_out_0

0: not allowed; 1: allowed

0x0

z3_wakeup_0

0: not allowed; 1: allowed

0x1

flash_wp_l_0

0: not allowed; 1: allowed

0x0

bat_disable_1

0: not allowed; 1: allowed

0x0

ec_rst_l_1

0: not allowed; 1: allowed

0x0

pwrb_out_1

0: not allowed; 1: allowed

0x0

key0_out_1

0: not allowed; 1: allowed

0x0

key1_out_1

0: not allowed; 1: allowed

0x0

key2_out_1

0: not allowed; 1: allowed

0x0

z3_wakeup_1

0: not allowed; 1: allowed

0x0

flash_wp_l_1

0: not allowed; 1: allowed

sysrst_ctrl.PIN_OUT_CTL @ 0x38

Enables the override function for a specific pin.

Reset default = 0x82, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								flash_wp_l	z3_wakeup	key2_out	key1_out	key0_out	pwrb_out	ec_rst_l	bat_disable

Bits

Type

Reset

Name

Description

0x0

bat_disable

0: disable override; 1: enable override

0x1

ec_rst_l

0: disable override; 1: enable override

0x0

pwrb_out

0: disable override; 1: enable override

0x0

key0_out

0: disable override; 1: enable override

0x0

key1_out

0: disable override; 1: enable override

0x0

key2_out

0: disable override; 1: enable override

0x0

z3_wakeup

0: disable override; 1: enable override

0x1

flash_wp_l

0: disable override; 1: enable override

sysrst_ctrl.PIN_OUT_VALUE @ 0x3c

Sets the pin override value. Note that only the values configured as 'allowed' in PIN_ALLOWED_CTL will have an effect. Otherwise the pin value will not be overridden.

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								flash_wp_l	z3_wakeup	key2_out	key1_out	key0_out	pwrb_out	ec_rst_l	bat_disable

Bits Type Reset Name Description

0x0

bat_disable

0: override to 1b0; 1: override to 1b1

0x0

ec_rst_l

0: override to 1b0; 1: override to 1b1

0x0

pwrb_out

0: override to 1b0; 1: override to 1b1

0x0

key0_out

0: override to 1b0; 1: override to 1b1

0x0

key1_out

0: override to 1b0; 1: override to 1b1

0x0

key2_out

0: override to 1b0; 1: override to 1b1

0x0

z3_wakeup

0: override to 1b0; 1: override to 1b1

0x0

flash_wp_l

0: override to 1b0; 1: override to 1b1

sysrst_ctrl.PIN_IN_VALUE @ 0x40

For SW to read the sysrst_ctrl inputs like GPIO

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								flash_wp_l	ec_rst_l	ac_present	lid_open	key2_in	key1_in	key0_in	pwrb_in

Bits

Type

Reset

Name

Description

0x0

pwrb_in

raw pwrb_in value; before the invert logic

0x0

key0_in

raw key0_in value; before the invert logic

0x0

key1_in

raw key1_in value; before the invert logic

0x0

key2_in

raw key2_in value; before the invert logic

0x0

lid_open

raw lid_open value; before the invert logic

0x0

ac_present

raw ac_present value; before the invert logic

0x0

ec_rst_l

raw ec_rst_l value; before the invert logic

0x0

flash_wp_l

raw flash_wp_l value; before the invert logic

sysrst_ctrl.KEY_INTR_CTL @ 0x44

Define the keys or inputs that can trigger the interrupt

Reset default = 0x0, mask 0x3fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		flash_wp_l_L2H	ec_rst_l_L2H	ac_present_L2H	key2_in_L2H	key1_in_L2H	key0_in_L2H	pwrb_in_L2H	flash_wp_l_H2L	ec_rst_l_H2L	ac_present_H2L	key2_in_H2L	key1_in_H2L	key0_in_H2L	pwrb_in_H2L

Bits

Type

Reset

Name

Description

0x0

pwrb_in_H2L

0: disable, 1: enable

0x0

key0_in_H2L

0: disable, 1: enable

0x0

key1_in_H2L

0: disable, 1: enable

0x0

key2_in_H2L

0: disable, 1: enable

0x0

ac_present_H2L

0: disable, 1: enable

0x0

ec_rst_l_H2L

0: disable, 1: enable

0x0

flash_wp_l_H2L

0: disable, 1: enable

0x0

pwrb_in_L2H

0: disable, 1: enable

0x0

key0_in_L2H

0: disable, 1: enable

0x0

key1_in_L2H

0: disable, 1: enable

0x0

key2_in_L2H

0: disable, 1: enable

0x0

ac_present_L2H

0: disable, 1: enable

0x0

ec_rst_l_L2H

0: disable, 1: enable

0x0

flash_wp_l_L2H

0: disable, 1: enable

sysrst_ctrl.KEY_INTR_DEBOUNCE_CTL @ 0x48

Debounce timer control register for key-triggered interrupt

Reset default = 0x7d0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
debounce_timer

Bits

Type

Reset

Name

Description

15:0

0x7d0

debounce_timer

Define the timer value so that the key or input is not oscillating in clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

sysrst_ctrl.AUTO_BLOCK_DEBOUNCE_CTL @ 0x4c

Debounce timer control register for pwrb_in H2L transition

Reset default = 0x7d0, mask 0x1ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															auto_block_enable
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
debounce_timer

Bits

Type

Reset

Name

Description

15:0

0x7d0

debounce_timer

Define the timer value so that the pwrb_in is not oscillating in clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

0x0

auto_block_enable

0: disable, 1: enable

sysrst_ctrl.AUTO_BLOCK_OUT_CTL @ 0x50

configure the key outputs to auto-override and their value

Reset default = 0x0, mask 0x77

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									key2_out_value	key1_out_value	key0_out_value		key2_out_sel	key1_out_sel	key0_out_sel

Bits

Type

Reset

Name

Description

0x0

key0_out_sel

0: disable auto-block; 1: enable auto-block

0x0

key1_out_sel

0: disable auto-block; 1: enable auto-block

0x0

key2_out_sel

0: disable auto-block; 1: enable auto-block

Reserved

0x0

key0_out_value

0: override to 1'b0; 1: override to 1'b1

0x0

key1_out_value

0: override to 1'b0; 1: override to 1'b1

0x0

key2_out_value

0: override to 1'b0; 1: override to 1'b1

sysrst_ctrl.COM_PRE_SEL_CTL_0 @ 0x54

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

Reset default = 0x0, mask 0x1f

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ac_present_sel_0	pwrb_in_sel_0	key2_in_sel_0	key1_in_sel_0	key0_in_sel_0

Bits Type Reset Name Description

0x0

key0_in_sel_0

0: disable, 1: enable

0x0

key1_in_sel_0

0: disable, 1: enable

0x0

key2_in_sel_0

0: disable, 1: enable

0x0

pwrb_in_sel_0

0: disable, 1: enable

0x0

ac_present_sel_0

0: disable, 1: enable

sysrst_ctrl.COM_PRE_SEL_CTL_1 @ 0x58

Reset default = 0x0, mask 0x1f

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ac_present_sel_1	pwrb_in_sel_1	key2_in_sel_1	key1_in_sel_1	key0_in_sel_1

Bits Type Reset Name Description

0x0

key0_in_sel_1

For sysrst_ctrl1

0x0

key1_in_sel_1

For sysrst_ctrl1

0x0

key2_in_sel_1

For sysrst_ctrl1

0x0

pwrb_in_sel_1

For sysrst_ctrl1

0x0

ac_present_sel_1

For sysrst_ctrl1

sysrst_ctrl.COM_PRE_SEL_CTL_2 @ 0x5c

Reset default = 0x0, mask 0x1f

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ac_present_sel_2	pwrb_in_sel_2	key2_in_sel_2	key1_in_sel_2	key0_in_sel_2

Bits Type Reset Name Description

0x0

key0_in_sel_2

For sysrst_ctrl2

0x0

key1_in_sel_2

For sysrst_ctrl2

0x0

key2_in_sel_2

For sysrst_ctrl2

0x0

pwrb_in_sel_2

For sysrst_ctrl2

0x0

ac_present_sel_2

For sysrst_ctrl2

sysrst_ctrl.COM_PRE_SEL_CTL_3 @ 0x60

Reset default = 0x0, mask 0x1f

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ac_present_sel_3	pwrb_in_sel_3	key2_in_sel_3	key1_in_sel_3	key0_in_sel_3

Bits Type Reset Name Description

0x0

key0_in_sel_3

For sysrst_ctrl3

0x0

key1_in_sel_3

For sysrst_ctrl3

0x0

key2_in_sel_3

For sysrst_ctrl3

0x0

pwrb_in_sel_3

For sysrst_ctrl3

0x0

ac_present_sel_3

For sysrst_ctrl3

sysrst_ctrl.COM_PRE_DET_CTL_0 @ 0x64

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
precondition_timer_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...precondition_timer_0

Bits

Type

Reset

Name

Description

31:0

0x0

precondition_timer_0

0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_PRE_DET_CTL_1 @ 0x68

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
precondition_timer_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...precondition_timer_1

Bits

Type

Reset

Name

Description

31:0

0x0

precondition_timer_1

For sysrst_ctrl1

sysrst_ctrl.COM_PRE_DET_CTL_2 @ 0x6c

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
precondition_timer_2...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...precondition_timer_2

Bits

Type

Reset

Name

Description

31:0

0x0

precondition_timer_2

For sysrst_ctrl2

sysrst_ctrl.COM_PRE_DET_CTL_3 @ 0x70

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
precondition_timer_3...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...precondition_timer_3

Bits

Type

Reset

Name

Description

31:0

0x0

precondition_timer_3

For sysrst_ctrl3

sysrst_ctrl.COM_SEL_CTL_0 @ 0x74

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Reset default = 0x0, mask 0x1f

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ac_present_sel_0	pwrb_in_sel_0	key2_in_sel_0	key1_in_sel_0	key0_in_sel_0

Bits Type Reset Name Description

0x0

key0_in_sel_0

0: disable, 1: enable

0x0

key1_in_sel_0

0: disable, 1: enable

0x0

key2_in_sel_0

0: disable, 1: enable

0x0

pwrb_in_sel_0

0: disable, 1: enable

0x0

ac_present_sel_0

0: disable, 1: enable

sysrst_ctrl.COM_SEL_CTL_1 @ 0x78

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Reset default = 0x0, mask 0x1f

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ac_present_sel_1	pwrb_in_sel_1	key2_in_sel_1	key1_in_sel_1	key0_in_sel_1

Bits Type Reset Name Description

0x0

key0_in_sel_1

For sysrst_ctrl1

0x0

key1_in_sel_1

For sysrst_ctrl1

0x0

key2_in_sel_1

For sysrst_ctrl1

0x0

pwrb_in_sel_1

For sysrst_ctrl1

0x0

ac_present_sel_1

For sysrst_ctrl1

sysrst_ctrl.COM_SEL_CTL_2 @ 0x7c

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Reset default = 0x0, mask 0x1f

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ac_present_sel_2	pwrb_in_sel_2	key2_in_sel_2	key1_in_sel_2	key0_in_sel_2

Bits Type Reset Name Description

0x0

key0_in_sel_2

For sysrst_ctrl2

0x0

key1_in_sel_2

For sysrst_ctrl2

0x0

key2_in_sel_2

For sysrst_ctrl2

0x0

pwrb_in_sel_2

For sysrst_ctrl2

0x0

ac_present_sel_2

For sysrst_ctrl2

sysrst_ctrl.COM_SEL_CTL_3 @ 0x80

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Reset default = 0x0, mask 0x1f

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ac_present_sel_3	pwrb_in_sel_3	key2_in_sel_3	key1_in_sel_3	key0_in_sel_3

Bits Type Reset Name Description

0x0

key0_in_sel_3

For sysrst_ctrl3

0x0

key1_in_sel_3

For sysrst_ctrl3

0x0

key2_in_sel_3

For sysrst_ctrl3

0x0

pwrb_in_sel_3

For sysrst_ctrl3

0x0

ac_present_sel_3

For sysrst_ctrl3

sysrst_ctrl.COM_DET_CTL_0 @ 0x84

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
detection_timer_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...detection_timer_0

Bits

Type

Reset

Name

Description

31:0

0x0

detection_timer_0

0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_DET_CTL_1 @ 0x88

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
detection_timer_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...detection_timer_1

Bits

Type

Reset

Name

Description

31:0

0x0

detection_timer_1

For sysrst_ctrl1

sysrst_ctrl.COM_DET_CTL_2 @ 0x8c

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
detection_timer_2...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...detection_timer_2

Bits

Type

Reset

Name

Description

31:0

0x0

detection_timer_2

For sysrst_ctrl2

sysrst_ctrl.COM_DET_CTL_3 @ 0x90

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
detection_timer_3...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...detection_timer_3

Bits

Type

Reset

Name

Description

31:0

0x0

detection_timer_3

For sysrst_ctrl3

sysrst_ctrl.COM_OUT_CTL_0 @ 0x94

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												rst_req_0	ec_rst_0	interrupt_0	bat_disable_0

Bits

Type

Reset

Name

Description

0x0

bat_disable_0

0: disable, 1: enable

0x0

interrupt_0

0: disable, 1: enable

0x0

ec_rst_0

0: disable, 1: enable

0x0

rst_req_0

0: disable, 1: enable

sysrst_ctrl.COM_OUT_CTL_1 @ 0x98

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												rst_req_1	ec_rst_1	interrupt_1	bat_disable_1

Bits

Type

Reset

Name

Description

0x0

bat_disable_1

For sysrst_ctrl1

0x0

interrupt_1

For sysrst_ctrl1

0x0

ec_rst_1

For sysrst_ctrl1

0x0

rst_req_1

For sysrst_ctrl1

sysrst_ctrl.COM_OUT_CTL_2 @ 0x9c

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												rst_req_2	ec_rst_2	interrupt_2	bat_disable_2

Bits

Type

Reset

Name

Description

0x0

bat_disable_2

For sysrst_ctrl2

0x0

interrupt_2

For sysrst_ctrl2

0x0

ec_rst_2

For sysrst_ctrl2

0x0

rst_req_2

For sysrst_ctrl2

sysrst_ctrl.COM_OUT_CTL_3 @ 0xa0

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												rst_req_3	ec_rst_3	interrupt_3	bat_disable_3

Bits

Type

Reset

Name

Description

0x0

bat_disable_3

For sysrst_ctrl3

0x0

interrupt_3

For sysrst_ctrl3

0x0

ec_rst_3

For sysrst_ctrl3

0x0

rst_req_3

For sysrst_ctrl3

sysrst_ctrl.COMBO_INTR_STATUS @ 0xa4

Combo interrupt source. These registers will only be set if the interrupt action is configured in the corresponding COM_OUT_CTL register.

Reset default = 0x0, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												combo3_H2L	combo2_H2L	combo1_H2L	combo0_H2L

Bits Type Reset Name Description

rw1c

0x0

combo0_H2L

0: case not detected;1: case detected

rw1c

0x0

combo1_H2L

0: case not detected;1: case detected

rw1c

0x0

combo2_H2L

0: case not detected;1: case detected

rw1c

0x0

combo3_H2L

0: case not detected;1: case detected

sysrst_ctrl.KEY_INTR_STATUS @ 0xa8

key interrupt source

Reset default = 0x0, mask 0x3fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		flash_wp_l_L2H	ec_rst_l_L2H	ac_present_L2H	key2_in_L2H	key1_in_L2H	key0_in_L2H	pwrb_L2H	flash_wp_l_H2L	ec_rst_l_H2L	ac_present_H2L	key2_in_H2L	key1_in_H2L	key0_in_H2L	pwrb_H2L

Bits

Type

Reset

Name

Description

rw1c

0x0

pwrb_H2L

0: case not detected;1: case detected

rw1c

0x0

key0_in_H2L

0: case not detected;1: case detected

rw1c

0x0

key1_in_H2L

0: case not detected;1: case detected

rw1c

0x0

key2_in_H2L

0: case not detected;1: case detected

rw1c

0x0

ac_present_H2L

0: case not detected;1: case detected

rw1c

0x0

ec_rst_l_H2L

0: case not detected;1: case detected

rw1c

0x0

flash_wp_l_H2L

0: case not detected;1: case detected

rw1c

0x0

pwrb_L2H

0: case not detected;1: case detected

rw1c

0x0

key0_in_L2H

0: case not detected;1: case detected

rw1c

0x0

key1_in_L2H

0: case not detected;1: case detected

rw1c

0x0

key2_in_L2H

0: case not detected;1: case detected

rw1c

0x0

ac_present_L2H

0: case not detected;1: case detected

rw1c

0x0

ec_rst_l_L2H

0: case not detected;1: case detected

rw1c

0x0

flash_wp_l_L2H

0: case not detected;1: case detected

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers