Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module sysrst_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
ac_presentinput

A/C power is present

key0_ininput

VolUp button in tablet; column output from the EC in a laptop

key1_ininput

VolDown button in tablet; row input from keyboard matrix in a laptop

key2_ininput

TBD button in tablet; row input from keyboard matrix in a laptop

pwrb_ininput

Power button in both tablet and laptop

lid_openinput

Lid is open

bat_disableoutput

Battery is disconnected

key0_outoutput

Passthrough from key0_in, can be configured to invert

key1_outoutput

Passthrough from key1_in, can be configured to invert

key2_outoutput

Passthrough from key2_in, can be configured to invert

pwrb_outoutput

Passthrough from pwrb_in, can be configured to invert

z3_wakeupoutput

To enter Z3 mode and exit from Z4 sleep mode

ec_rst_linout

ec_rst_l as an inout to/from the open drain IO

flash_wp_linout

flash_wp_l as an inout to/from the open drain IO

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
wkup_req logic uni req 1
rst_req logic uni req 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
event_detectedEvent

Common interrupt triggered by combo or keyboard events.

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
SYSRST_CTRL.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
sysrst_ctrl.INTR_STATE 0x0 4

Interrupt State Register

sysrst_ctrl.INTR_ENABLE 0x4 4

Interrupt Enable Register

sysrst_ctrl.INTR_TEST 0x8 4

Interrupt Test Register

sysrst_ctrl.ALERT_TEST 0xc 4

Alert Test Register

sysrst_ctrl.REGWEN 0x10 4

Configuration write enable control register

sysrst_ctrl.EC_RST_CTL 0x14 4

EC reset control register

sysrst_ctrl.ULP_AC_DEBOUNCE_CTL 0x18 4

Ultra low power AC debounce control register

sysrst_ctrl.ULP_LID_DEBOUNCE_CTL 0x1c 4

Ultra low power lid debounce control register

sysrst_ctrl.ULP_PWRB_DEBOUNCE_CTL 0x20 4

Ultra low power pwrb debounce control register

sysrst_ctrl.ULP_CTL 0x24 4

Ultra low power control register

sysrst_ctrl.ULP_STATUS 0x28 4

Ultra low power status

sysrst_ctrl.WKUP_STATUS 0x2c 4

wakeup status

sysrst_ctrl.KEY_INVERT_CTL 0x30 4

configure key input output invert property

sysrst_ctrl.PIN_ALLOWED_CTL 0x34 4

This register determines which override values are allowed for a given output. If an override value programmed via PIN_OUT_VALUE is not configured as an allowed value, it will not have any effect.

sysrst_ctrl.PIN_OUT_CTL 0x38 4

Enables the override function for a specific pin.

sysrst_ctrl.PIN_OUT_VALUE 0x3c 4

Sets the pin override value. Note that only the values configured as 'allowed' in PIN_ALLOWED_CTL will have an effect. Otherwise the pin value will not be overridden.

sysrst_ctrl.PIN_IN_VALUE 0x40 4

For SW to read the sysrst_ctrl inputs like GPIO

sysrst_ctrl.KEY_INTR_CTL 0x44 4

Define the keys or inputs that can trigger the interrupt

sysrst_ctrl.KEY_INTR_DEBOUNCE_CTL 0x48 4

Debounce timer control register for key-triggered interrupt

sysrst_ctrl.AUTO_BLOCK_DEBOUNCE_CTL 0x4c 4

Debounce timer control register for pwrb_in H2L transition

sysrst_ctrl.AUTO_BLOCK_OUT_CTL 0x50 4

configure the key outputs to auto-override and their value

sysrst_ctrl.COM_PRE_SEL_CTL_0 0x54 4

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

sysrst_ctrl.COM_PRE_SEL_CTL_1 0x58 4

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

sysrst_ctrl.COM_PRE_SEL_CTL_2 0x5c 4

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

sysrst_ctrl.COM_PRE_SEL_CTL_3 0x60 4

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

sysrst_ctrl.COM_PRE_DET_CTL_0 0x64 4

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_PRE_DET_CTL_1 0x68 4

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_PRE_DET_CTL_2 0x6c 4

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_PRE_DET_CTL_3 0x70 4

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_SEL_CTL_0 0x74 4

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

sysrst_ctrl.COM_SEL_CTL_1 0x78 4

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

sysrst_ctrl.COM_SEL_CTL_2 0x7c 4

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

sysrst_ctrl.COM_SEL_CTL_3 0x80 4

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

sysrst_ctrl.COM_DET_CTL_0 0x84 4

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_DET_CTL_1 0x88 4

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_DET_CTL_2 0x8c 4

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_DET_CTL_3 0x90 4

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

sysrst_ctrl.COM_OUT_CTL_0 0x94 4

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

sysrst_ctrl.COM_OUT_CTL_1 0x98 4

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

sysrst_ctrl.COM_OUT_CTL_2 0x9c 4

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

sysrst_ctrl.COM_OUT_CTL_3 0xa0 4

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

sysrst_ctrl.COMBO_INTR_STATUS 0xa4 4

Combo interrupt source. These registers will only be set if the interrupt action is configured in the corresponding COM_OUT_CTL register.

sysrst_ctrl.KEY_INTR_STATUS 0xa8 4

key interrupt source

sysrst_ctrl.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1
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  event_detected
BitsTypeResetNameDescription
0rw1c0x0event_detected

Common interrupt triggered by combo or keyboard events.


sysrst_ctrl.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1
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  event_detected
BitsTypeResetNameDescription
0rw0x0event_detected

Enable interrupt when INTR_STATE.event_detected is set.


sysrst_ctrl.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1
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  event_detected
BitsTypeResetNameDescription
0wo0x0event_detected

Write 1 to force INTR_STATE.event_detected to 1.


sysrst_ctrl.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


sysrst_ctrl.REGWEN @ 0x10

Configuration write enable control register

Reset default = 0x1, mask 0x1
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  write_en
BitsTypeResetNameDescription
0rw0c0x1write_en

config write enable. 0: cfg is locked(not writable); 1: cfg is not locked(writable)


sysrst_ctrl.EC_RST_CTL @ 0x14

EC reset control register

Reset default = 0x7d0, mask 0xffff
Register enable = REGWEN
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ec_rst_pulse
BitsTypeResetNameDescription
15:0rw0x7d0ec_rst_pulse

Configure the debounce timer in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.


sysrst_ctrl.ULP_AC_DEBOUNCE_CTL @ 0x18

Ultra low power AC debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_ac_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_ac_debounce_timer

Configure the debounce timer for the AC input in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.


sysrst_ctrl.ULP_LID_DEBOUNCE_CTL @ 0x1c

Ultra low power lid debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_lid_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_lid_debounce_timer

Configure the debounce timer for the lid in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.


sysrst_ctrl.ULP_PWRB_DEBOUNCE_CTL @ 0x20

Ultra low power pwrb debounce control register

Reset default = 0x1f40, mask 0xffff
Register enable = REGWEN
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ulp_pwrb_debounce_timer
BitsTypeResetNameDescription
15:0rw0x1f40ulp_pwrb_debounce_timer

Configure the debounce timer for the power button in number of clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.


sysrst_ctrl.ULP_CTL @ 0x24

Ultra low power control register

Reset default = 0x0, mask 0x1
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  ulp_enable
BitsTypeResetNameDescription
0rw0x0ulp_enable

0: disable ULP wakeup feature and reset the ULP FSM; 1: enable ULP wakeup feature


sysrst_ctrl.ULP_STATUS @ 0x28

Ultra low power status

Reset default = 0x0, mask 0x1
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  ulp_wakeup
BitsTypeResetNameDescription
0rw1c0x0ulp_wakeup

0: ULP wakeup not detected; 1: ULP wakeup event is detected


sysrst_ctrl.WKUP_STATUS @ 0x2c

wakeup status

Reset default = 0x0, mask 0x1
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  wakeup_sts
BitsTypeResetNameDescription
0rw1c0x0wakeup_sts

0: wakeup event not detected; 1: wakeup event is detected


sysrst_ctrl.KEY_INVERT_CTL @ 0x30

configure key input output invert property

Reset default = 0x0, mask 0xfff
Register enable = REGWEN
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  z3_wakeup lid_open bat_disable ac_present pwrb_out pwrb_in key2_out key2_in key1_out key1_in key0_out key0_in
BitsTypeResetNameDescription
0rw0x0key0_in

0: don't invert; 1: invert

1rw0x0key0_out

0: don't invert; 1: invert

2rw0x0key1_in

0: don't invert; 1: invert

3rw0x0key1_out

0: don't invert; 1: invert

4rw0x0key2_in

0: don't invert; 1: invert

5rw0x0key2_out

0: don't invert; 1: invert

6rw0x0pwrb_in

0: don't invert; 1: invert

7rw0x0pwrb_out

0: don't invert; 1: invert

8rw0x0ac_present

0: don't invert; 1: invert

9rw0x0bat_disable

0: don't invert; 1: invert

10rw0x0lid_open

0: don't invert; 1: invert

11rw0x0z3_wakeup

0: don't invert; 1: invert


sysrst_ctrl.PIN_ALLOWED_CTL @ 0x34

This register determines which override values are allowed for a given output. If an override value programmed via PIN_OUT_VALUE is not configured as an allowed value, it will not have any effect.

Reset default = 0x82, mask 0xffff
Register enable = REGWEN
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flash_wp_l_1 z3_wakeup_1 key2_out_1 key1_out_1 key0_out_1 pwrb_out_1 ec_rst_l_1 bat_disable_1 flash_wp_l_0 z3_wakeup_0 key2_out_0 key1_out_0 key0_out_0 pwrb_out_0 ec_rst_l_0 bat_disable_0
BitsTypeResetNameDescription
0rw0x0bat_disable_0

0: not allowed; 1: allowed

1rw0x1ec_rst_l_0

0: not allowed; 1: allowed

2rw0x0pwrb_out_0

0: not allowed; 1: allowed

3rw0x0key0_out_0

0: not allowed; 1: allowed

4rw0x0key1_out_0

0: not allowed; 1: allowed

5rw0x0key2_out_0

0: not allowed; 1: allowed

6rw0x0z3_wakeup_0

0: not allowed; 1: allowed

7rw0x1flash_wp_l_0

0: not allowed; 1: allowed

8rw0x0bat_disable_1

0: not allowed; 1: allowed

9rw0x0ec_rst_l_1

0: not allowed; 1: allowed

10rw0x0pwrb_out_1

0: not allowed; 1: allowed

11rw0x0key0_out_1

0: not allowed; 1: allowed

12rw0x0key1_out_1

0: not allowed; 1: allowed

13rw0x0key2_out_1

0: not allowed; 1: allowed

14rw0x0z3_wakeup_1

0: not allowed; 1: allowed

15rw0x0flash_wp_l_1

0: not allowed; 1: allowed


sysrst_ctrl.PIN_OUT_CTL @ 0x38

Enables the override function for a specific pin.

Reset default = 0x82, mask 0xff
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  flash_wp_l z3_wakeup key2_out key1_out key0_out pwrb_out ec_rst_l bat_disable
BitsTypeResetNameDescription
0rw0x0bat_disable

0: disable override; 1: enable override

1rw0x1ec_rst_l

0: disable override; 1: enable override

2rw0x0pwrb_out

0: disable override; 1: enable override

3rw0x0key0_out

0: disable override; 1: enable override

4rw0x0key1_out

0: disable override; 1: enable override

5rw0x0key2_out

0: disable override; 1: enable override

6rw0x0z3_wakeup

0: disable override; 1: enable override

7rw0x1flash_wp_l

0: disable override; 1: enable override


sysrst_ctrl.PIN_OUT_VALUE @ 0x3c

Sets the pin override value. Note that only the values configured as 'allowed' in PIN_ALLOWED_CTL will have an effect. Otherwise the pin value will not be overridden.

Reset default = 0x0, mask 0xff
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  flash_wp_l z3_wakeup key2_out key1_out key0_out pwrb_out ec_rst_l bat_disable
BitsTypeResetNameDescription
0rw0x0bat_disable

0: override to 1b0; 1: override to 1b1

1rw0x0ec_rst_l

0: override to 1b0; 1: override to 1b1

2rw0x0pwrb_out

0: override to 1b0; 1: override to 1b1

3rw0x0key0_out

0: override to 1b0; 1: override to 1b1

4rw0x0key1_out

0: override to 1b0; 1: override to 1b1

5rw0x0key2_out

0: override to 1b0; 1: override to 1b1

6rw0x0z3_wakeup

0: override to 1b0; 1: override to 1b1

7rw0x0flash_wp_l

0: override to 1b0; 1: override to 1b1


sysrst_ctrl.PIN_IN_VALUE @ 0x40

For SW to read the sysrst_ctrl inputs like GPIO

Reset default = 0x0, mask 0xff
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  flash_wp_l ec_rst_l ac_present lid_open key2_in key1_in key0_in pwrb_in
BitsTypeResetNameDescription
0ro0x0pwrb_in

raw pwrb_in value; before the invert logic

1ro0x0key0_in

raw key0_in value; before the invert logic

2ro0x0key1_in

raw key1_in value; before the invert logic

3ro0x0key2_in

raw key2_in value; before the invert logic

4ro0x0lid_open

raw lid_open value; before the invert logic

5ro0x0ac_present

raw ac_present value; before the invert logic

6ro0x0ec_rst_l

raw ec_rst_l value; before the invert logic

7ro0x0flash_wp_l

raw flash_wp_l value; before the invert logic


sysrst_ctrl.KEY_INTR_CTL @ 0x44

Define the keys or inputs that can trigger the interrupt

Reset default = 0x0, mask 0x3fff
Register enable = REGWEN
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  flash_wp_l_L2H ec_rst_l_L2H ac_present_L2H key2_in_L2H key1_in_L2H key0_in_L2H pwrb_in_L2H flash_wp_l_H2L ec_rst_l_H2L ac_present_H2L key2_in_H2L key1_in_H2L key0_in_H2L pwrb_in_H2L
BitsTypeResetNameDescription
0rw0x0pwrb_in_H2L

0: disable, 1: enable

1rw0x0key0_in_H2L

0: disable, 1: enable

2rw0x0key1_in_H2L

0: disable, 1: enable

3rw0x0key2_in_H2L

0: disable, 1: enable

4rw0x0ac_present_H2L

0: disable, 1: enable

5rw0x0ec_rst_l_H2L

0: disable, 1: enable

6rw0x0flash_wp_l_H2L

0: disable, 1: enable

7rw0x0pwrb_in_L2H

0: disable, 1: enable

8rw0x0key0_in_L2H

0: disable, 1: enable

9rw0x0key1_in_L2H

0: disable, 1: enable

10rw0x0key2_in_L2H

0: disable, 1: enable

11rw0x0ac_present_L2H

0: disable, 1: enable

12rw0x0ec_rst_l_L2H

0: disable, 1: enable

13rw0x0flash_wp_l_L2H

0: disable, 1: enable


sysrst_ctrl.KEY_INTR_DEBOUNCE_CTL @ 0x48

Debounce timer control register for key-triggered interrupt

Reset default = 0x7d0, mask 0xffff
Register enable = REGWEN
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debounce_timer
BitsTypeResetNameDescription
15:0rw0x7d0debounce_timer

Define the timer value so that the key or input is not oscillating in clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.


sysrst_ctrl.AUTO_BLOCK_DEBOUNCE_CTL @ 0x4c

Debounce timer control register for pwrb_in H2L transition

Reset default = 0x7d0, mask 0x1ffff
Register enable = REGWEN
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  auto_block_enable
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debounce_timer
BitsTypeResetNameDescription
15:0rw0x7d0debounce_timer

Define the timer value so that the pwrb_in is not oscillating in clock cycles. Each step is 5 us for a 200 kHz clock. The signal must exceed the debounce time by at least one clock cycle to be detected.

16rw0x0auto_block_enable

0: disable, 1: enable


sysrst_ctrl.AUTO_BLOCK_OUT_CTL @ 0x50

configure the key outputs to auto-override and their value

Reset default = 0x0, mask 0x77
Register enable = REGWEN
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  key2_out_value key1_out_value key0_out_value   key2_out_sel key1_out_sel key0_out_sel
BitsTypeResetNameDescription
0rw0x0key0_out_sel

0: disable auto-block; 1: enable auto-block

1rw0x0key1_out_sel

0: disable auto-block; 1: enable auto-block

2rw0x0key2_out_sel

0: disable auto-block; 1: enable auto-block

3Reserved
4rw0x0key0_out_value

0: override to 1'b0; 1: override to 1'b1

5rw0x0key1_out_value

0: override to 1'b0; 1: override to 1'b1

6rw0x0key2_out_value

0: override to 1'b0; 1: override to 1'b1


sysrst_ctrl.COM_PRE_SEL_CTL_0 @ 0x54

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

Reset default = 0x0, mask 0x1f
Register enable = REGWEN

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

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  ac_present_sel_0 pwrb_in_sel_0 key2_in_sel_0 key1_in_sel_0 key0_in_sel_0
BitsTypeResetNameDescription
0rw0x0key0_in_sel_0

0: disable, 1: enable

1rw0x0key1_in_sel_0

0: disable, 1: enable

2rw0x0key2_in_sel_0

0: disable, 1: enable

3rw0x0pwrb_in_sel_0

0: disable, 1: enable

4rw0x0ac_present_sel_0

0: disable, 1: enable


sysrst_ctrl.COM_PRE_SEL_CTL_1 @ 0x58

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

Reset default = 0x0, mask 0x1f
Register enable = REGWEN

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

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  ac_present_sel_1 pwrb_in_sel_1 key2_in_sel_1 key1_in_sel_1 key0_in_sel_1
BitsTypeResetNameDescription
0rw0x0key0_in_sel_1

For sysrst_ctrl1

1rw0x0key1_in_sel_1

For sysrst_ctrl1

2rw0x0key2_in_sel_1

For sysrst_ctrl1

3rw0x0pwrb_in_sel_1

For sysrst_ctrl1

4rw0x0ac_present_sel_1

For sysrst_ctrl1


sysrst_ctrl.COM_PRE_SEL_CTL_2 @ 0x5c

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

Reset default = 0x0, mask 0x1f
Register enable = REGWEN

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

31302928272625242322212019181716
 
1514131211109876543210
  ac_present_sel_2 pwrb_in_sel_2 key2_in_sel_2 key1_in_sel_2 key0_in_sel_2
BitsTypeResetNameDescription
0rw0x0key0_in_sel_2

For sysrst_ctrl2

1rw0x0key1_in_sel_2

For sysrst_ctrl2

2rw0x0key2_in_sel_2

For sysrst_ctrl2

3rw0x0pwrb_in_sel_2

For sysrst_ctrl2

4rw0x0ac_present_sel_2

For sysrst_ctrl2


sysrst_ctrl.COM_PRE_SEL_CTL_3 @ 0x60

To define the keys that define the pre-condition of the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will start matching the combo as defined by COM_SEL_CTL if this precondition is fulfilled.

Reset default = 0x0, mask 0x1f
Register enable = REGWEN

If no keys are configured for the pre-condition, the pre-condition always evaluates to true.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the pre-condition pressed timing is defined via COM_PRE_DET_CTL.

31302928272625242322212019181716
 
1514131211109876543210
  ac_present_sel_3 pwrb_in_sel_3 key2_in_sel_3 key1_in_sel_3 key0_in_sel_3
BitsTypeResetNameDescription
0rw0x0key0_in_sel_3

For sysrst_ctrl3

1rw0x0key1_in_sel_3

For sysrst_ctrl3

2rw0x0key2_in_sel_3

For sysrst_ctrl3

3rw0x0pwrb_in_sel_3

For sysrst_ctrl3

4rw0x0ac_present_sel_3

For sysrst_ctrl3


sysrst_ctrl.COM_PRE_DET_CTL_0 @ 0x64

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
precondition_timer_0...
1514131211109876543210
...precondition_timer_0
BitsTypeResetNameDescription
31:0rw0x0precondition_timer_0

0-60s, each step is 5us(200KHz clock)


sysrst_ctrl.COM_PRE_DET_CTL_1 @ 0x68

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
precondition_timer_1...
1514131211109876543210
...precondition_timer_1
BitsTypeResetNameDescription
31:0rw0x0precondition_timer_1

For sysrst_ctrl1


sysrst_ctrl.COM_PRE_DET_CTL_2 @ 0x6c

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
precondition_timer_2...
1514131211109876543210
...precondition_timer_2
BitsTypeResetNameDescription
31:0rw0x0precondition_timer_2

For sysrst_ctrl2


sysrst_ctrl.COM_PRE_DET_CTL_3 @ 0x70

To define the duration that the combo pre-condition should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
precondition_timer_3...
1514131211109876543210
...precondition_timer_3
BitsTypeResetNameDescription
31:0rw0x0precondition_timer_3

For sysrst_ctrl3


sysrst_ctrl.COM_SEL_CTL_0 @ 0x74

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Reset default = 0x0, mask 0x1f
Register enable = REGWEN

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

31302928272625242322212019181716
 
1514131211109876543210
  ac_present_sel_0 pwrb_in_sel_0 key2_in_sel_0 key1_in_sel_0 key0_in_sel_0
BitsTypeResetNameDescription
0rw0x0key0_in_sel_0

0: disable, 1: enable

1rw0x0key1_in_sel_0

0: disable, 1: enable

2rw0x0key2_in_sel_0

0: disable, 1: enable

3rw0x0pwrb_in_sel_0

0: disable, 1: enable

4rw0x0ac_present_sel_0

0: disable, 1: enable


sysrst_ctrl.COM_SEL_CTL_1 @ 0x78

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Reset default = 0x0, mask 0x1f
Register enable = REGWEN

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

31302928272625242322212019181716
 
1514131211109876543210
  ac_present_sel_1 pwrb_in_sel_1 key2_in_sel_1 key1_in_sel_1 key0_in_sel_1
BitsTypeResetNameDescription
0rw0x0key0_in_sel_1

For sysrst_ctrl1

1rw0x0key1_in_sel_1

For sysrst_ctrl1

2rw0x0key2_in_sel_1

For sysrst_ctrl1

3rw0x0pwrb_in_sel_1

For sysrst_ctrl1

4rw0x0ac_present_sel_1

For sysrst_ctrl1


sysrst_ctrl.COM_SEL_CTL_2 @ 0x7c

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Reset default = 0x0, mask 0x1f
Register enable = REGWEN

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

31302928272625242322212019181716
 
1514131211109876543210
  ac_present_sel_2 pwrb_in_sel_2 key2_in_sel_2 key1_in_sel_2 key0_in_sel_2
BitsTypeResetNameDescription
0rw0x0key0_in_sel_2

For sysrst_ctrl2

1rw0x0key1_in_sel_2

For sysrst_ctrl2

2rw0x0key2_in_sel_2

For sysrst_ctrl2

3rw0x0pwrb_in_sel_2

For sysrst_ctrl2

4rw0x0ac_present_sel_2

For sysrst_ctrl2


sysrst_ctrl.COM_SEL_CTL_3 @ 0x80

To define the keys that trigger the combo [0]: key0_in_sel [1]: key1_in_sel [2]: key2_in_sel [3]: pwrb_in_sel [4]: ac_present_sel HW will detect H2L transition in the combo use case.

Reset default = 0x0, mask 0x1f
Register enable = REGWEN

Optionally, a pre-condition can be configured for the combo detection via COM_PRE_SEL_CTL.

If no keys are configured for the combo, the combo detection is disabled.

The debounce timing is defined via KEY_INTR_DEBOUNCE_CTL whereas the key-pressed timing is defined via COM_DET_CTL.

31302928272625242322212019181716
 
1514131211109876543210
  ac_present_sel_3 pwrb_in_sel_3 key2_in_sel_3 key1_in_sel_3 key0_in_sel_3
BitsTypeResetNameDescription
0rw0x0key0_in_sel_3

For sysrst_ctrl3

1rw0x0key1_in_sel_3

For sysrst_ctrl3

2rw0x0key2_in_sel_3

For sysrst_ctrl3

3rw0x0pwrb_in_sel_3

For sysrst_ctrl3

4rw0x0ac_present_sel_3

For sysrst_ctrl3


sysrst_ctrl.COM_DET_CTL_0 @ 0x84

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
detection_timer_0...
1514131211109876543210
...detection_timer_0
BitsTypeResetNameDescription
31:0rw0x0detection_timer_0

0-60s, each step is 5us(200KHz clock)


sysrst_ctrl.COM_DET_CTL_1 @ 0x88

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
detection_timer_1...
1514131211109876543210
...detection_timer_1
BitsTypeResetNameDescription
31:0rw0x0detection_timer_1

For sysrst_ctrl1


sysrst_ctrl.COM_DET_CTL_2 @ 0x8c

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
detection_timer_2...
1514131211109876543210
...detection_timer_2
BitsTypeResetNameDescription
31:0rw0x0detection_timer_2

For sysrst_ctrl2


sysrst_ctrl.COM_DET_CTL_3 @ 0x90

To define the duration that the combo should be pressed 0-60s, each step is 5us(200KHz clock)

Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN
31302928272625242322212019181716
detection_timer_3...
1514131211109876543210
...detection_timer_3
BitsTypeResetNameDescription
31:0rw0x0detection_timer_3

For sysrst_ctrl3


sysrst_ctrl.COM_OUT_CTL_0 @ 0x94

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  rst_req_0 ec_rst_0 interrupt_0 bat_disable_0
BitsTypeResetNameDescription
0rw0x0bat_disable_0

0: disable, 1: enable

1rw0x0interrupt_0

0: disable, 1: enable

2rw0x0ec_rst_0

0: disable, 1: enable

3rw0x0rst_req_0

0: disable, 1: enable


sysrst_ctrl.COM_OUT_CTL_1 @ 0x98

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  rst_req_1 ec_rst_1 interrupt_1 bat_disable_1
BitsTypeResetNameDescription
0rw0x0bat_disable_1

For sysrst_ctrl1

1rw0x0interrupt_1

For sysrst_ctrl1

2rw0x0ec_rst_1

For sysrst_ctrl1

3rw0x0rst_req_1

For sysrst_ctrl1


sysrst_ctrl.COM_OUT_CTL_2 @ 0x9c

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  rst_req_2 ec_rst_2 interrupt_2 bat_disable_2
BitsTypeResetNameDescription
0rw0x0bat_disable_2

For sysrst_ctrl2

1rw0x0interrupt_2

For sysrst_ctrl2

2rw0x0ec_rst_2

For sysrst_ctrl2

3rw0x0rst_req_2

For sysrst_ctrl2


sysrst_ctrl.COM_OUT_CTL_3 @ 0xa0

To define the actions once the combo is detected [0]: bat_disable [1]: interrupt (to OpenTitan processor) [2]: ec_rst (for Embedded Controller) [3]: rst_req (to OpenTitan reset manager)

Reset default = 0x0, mask 0xf
Register enable = REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  rst_req_3 ec_rst_3 interrupt_3 bat_disable_3
BitsTypeResetNameDescription
0rw0x0bat_disable_3

For sysrst_ctrl3

1rw0x0interrupt_3

For sysrst_ctrl3

2rw0x0ec_rst_3

For sysrst_ctrl3

3rw0x0rst_req_3

For sysrst_ctrl3


sysrst_ctrl.COMBO_INTR_STATUS @ 0xa4

Combo interrupt source. These registers will only be set if the interrupt action is configured in the corresponding COM_OUT_CTL register.

Reset default = 0x0, mask 0xf
31302928272625242322212019181716
 
1514131211109876543210
  combo3_H2L combo2_H2L combo1_H2L combo0_H2L
BitsTypeResetNameDescription
0rw1c0x0combo0_H2L

0: case not detected;1: case detected

1rw1c0x0combo1_H2L

0: case not detected;1: case detected

2rw1c0x0combo2_H2L

0: case not detected;1: case detected

3rw1c0x0combo3_H2L

0: case not detected;1: case detected


sysrst_ctrl.KEY_INTR_STATUS @ 0xa8

key interrupt source

Reset default = 0x0, mask 0x3fff
31302928272625242322212019181716
 
1514131211109876543210
  flash_wp_l_L2H ec_rst_l_L2H ac_present_L2H key2_in_L2H key1_in_L2H key0_in_L2H pwrb_L2H flash_wp_l_H2L ec_rst_l_H2L ac_present_H2L key2_in_H2L key1_in_H2L key0_in_H2L pwrb_H2L
BitsTypeResetNameDescription
0rw1c0x0pwrb_H2L

0: case not detected;1: case detected

1rw1c0x0key0_in_H2L

0: case not detected;1: case detected

2rw1c0x0key1_in_H2L

0: case not detected;1: case detected

3rw1c0x0key2_in_H2L

0: case not detected;1: case detected

4rw1c0x0ac_present_H2L

0: case not detected;1: case detected

5rw1c0x0ec_rst_l_H2L

0: case not detected;1: case detected

6rw1c0x0flash_wp_l_H2L

0: case not detected;1: case detected

7rw1c0x0pwrb_L2H

0: case not detected;1: case detected

8rw1c0x0key0_in_L2H

0: case not detected;1: case detected

9rw1c0x0key1_in_L2H

0: case not detected;1: case detected

10rw1c0x0key2_in_L2H

0: case not detected;1: case detected

11rw1c0x0ac_present_L2H

0: case not detected;1: case detected

12rw1c0x0ec_rst_l_L2H

0: case not detected;1: case detected

13rw1c0x0flash_wp_l_L2H

0: case not detected;1: case detected