Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module gpio has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin name	direction	Description
gpio[31:0]	inout	GPIO inout to/from PAD

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width	Description
tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts:

Interrupt Name	Type	Description
gpio[31:0]	Event	raised if any of GPIO pin detects configured interrupt mode

Security Alerts:

Alert Name	Description
fatal_fault	This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure ID	Description
GPIO.BUS.INTEGRITY	End-to-end bus integrity scheme.

Registers

Summary
Name	Offset	Length	Description
gpio.INTR_STATE	0x0	4	Interrupt State Register
gpio.INTR_ENABLE	0x4	4	Interrupt Enable Register
gpio.INTR_TEST	0x8	4	Interrupt Test Register
gpio.ALERT_TEST	0xc	4	Alert Test Register
gpio.DATA_IN	0x10	4	GPIO Input data read value
gpio.DIRECT_OUT	0x14	4	GPIO direct output data write value
gpio.MASKED_OUT_LOWER	0x18	4	GPIO write data lower with mask.
gpio.MASKED_OUT_UPPER	0x1c	4	GPIO write data upper with mask.
gpio.DIRECT_OE	0x20	4	GPIO Output Enable.
gpio.MASKED_OE_LOWER	0x24	4	GPIO write Output Enable lower with mask.
gpio.MASKED_OE_UPPER	0x28	4	GPIO write Output Enable upper with mask.
gpio.INTR_CTRL_EN_RISING	0x2c	4	GPIO interrupt enable for GPIO, rising edge.
gpio.INTR_CTRL_EN_FALLING	0x30	4	GPIO interrupt enable for GPIO, falling edge.
gpio.INTR_CTRL_EN_LVLHIGH	0x34	4	GPIO interrupt enable for GPIO, level high.
gpio.INTR_CTRL_EN_LVLLOW	0x38	4	GPIO interrupt enable for GPIO, level low.
gpio.CTRL_EN_INPUT_FILTER	0x3c	4	filter enable for GPIO input bits.

gpio.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
gpio...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...gpio

Bits

Type

Reset

Name

Description

31:0

rw1c

0x0

gpio

raised if any of GPIO pin detects configured interrupt mode

gpio.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
gpio...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...gpio

Bits Type Reset Name Description

31:0

0x0

gpio

Enable interrupt when corresponding bit in INTR_STATE.gpio is set.

gpio.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
gpio...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...gpio

Bits Type Reset Name Description

31:0

0x0

gpio

Write 1 to force corresponding bit in INTR_STATE.gpio to 1.

gpio.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															fatal_fault

Bits

Type

Reset

Name

Description

0x0

fatal_fault

Write 1 to trigger one alert event of this kind.

gpio.DATA_IN @ 0x10

GPIO Input data read value

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA_IN...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...DATA_IN

Bits

Type

Reset

Name

Description

31:0

DATA_IN

gpio.DIRECT_OUT @ 0x14

GPIO direct output data write value

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DIRECT_OUT...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...DIRECT_OUT

Bits

Type

Reset

Name

Description

31:0

DIRECT_OUT

gpio.MASKED_OUT_LOWER @ 0x18

GPIO write data lower with mask.

Reset default = 0x0, mask 0xffffffff

Masked write for DATA_OUT[15:0].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OUT[15:0] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OUT[15:0].

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
mask
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
data

Bits

Type

Reset

Name

Description

15:0

data

Write data value[15:0].

Value to write into DATA_OUT[i], valid in the presence of mask[i]==1

31:16

mask

Write data mask[15:0].

A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15

gpio.MASKED_OUT_UPPER @ 0x1c

GPIO write data upper with mask.

Reset default = 0x0, mask 0xffffffff

Masked write for DATA_OUT[31:16].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OUT[31:16] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OUT[31:16].

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
mask
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
data

Bits

Type

Reset

Name

Description

15:0

data

Write data value[31:16].

Value to write into DATA_OUT[i], valid in the presence of mask[i]==1

31:16

mask

Write data mask[31:16].

A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31

gpio.DIRECT_OE @ 0x20

GPIO Output Enable.

Reset default = 0x0, mask 0xffffffff

Setting direct_oe[i] to 1 enables output mode for GPIO[i]

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DIRECT_OE...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...DIRECT_OE

Bits

Type

Reset

Name

Description

31:0

DIRECT_OE

gpio.MASKED_OE_LOWER @ 0x24

GPIO write Output Enable lower with mask.

Reset default = 0x0, mask 0xffffffff

Masked write for DATA_OE[15:0], the register that controls output mode for GPIO pins [15:0].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OE[15:0] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OE[15:0].

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
mask
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
data

Bits

Type

Reset

Name

Description

15:0

data

Write OE value[15:0].

Value to write into DATA_OE[i], valid in the presence of mask[i]==1

31:16

mask

Write OE mask[15:0].

A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15

gpio.MASKED_OE_UPPER @ 0x28

GPIO write Output Enable upper with mask.

Reset default = 0x0, mask 0xffffffff

Masked write for DATA_OE[31:16], the register that controls output mode for GPIO pins [31:16].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OE[31:16] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OE[31:16].

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
mask
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
data

Bits

Type

Reset

Name

Description

15:0

data

Write OE value[31:16].

Value to write into DATA_OE[i], valid in the presence of mask[i]==1

31:16

mask

Write OE mask[31:16].

A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31

gpio.INTR_CTRL_EN_RISING @ 0x2c

GPIO interrupt enable for GPIO, rising edge.

Reset default = 0x0, mask 0xffffffff

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_RISING[i] enables rising-edge interrupt detection on GPIO[i].

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INTR_CTRL_EN_RISING...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...INTR_CTRL_EN_RISING

Bits Type Reset Name Description

31:0 rw 0x0 INTR_CTRL_EN_RISING

gpio.INTR_CTRL_EN_FALLING @ 0x30

GPIO interrupt enable for GPIO, falling edge.

Reset default = 0x0, mask 0xffffffff

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_FALLING[i] enables falling-edge interrupt detection on GPIO[i].

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INTR_CTRL_EN_FALLING...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...INTR_CTRL_EN_FALLING

Bits Type Reset Name Description

31:0 rw 0x0 INTR_CTRL_EN_FALLING

gpio.INTR_CTRL_EN_LVLHIGH @ 0x34

GPIO interrupt enable for GPIO, level high.

Reset default = 0x0, mask 0xffffffff

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_LVLHIGH[i] enables level high interrupt detection on GPIO[i].

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INTR_CTRL_EN_LVLHIGH...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...INTR_CTRL_EN_LVLHIGH

Bits Type Reset Name Description

31:0 rw 0x0 INTR_CTRL_EN_LVLHIGH

gpio.INTR_CTRL_EN_LVLLOW @ 0x38

GPIO interrupt enable for GPIO, level low.

Reset default = 0x0, mask 0xffffffff

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_LVLLOW[i] enables level low interrupt detection on GPIO[i].

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
INTR_CTRL_EN_LVLLOW...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...INTR_CTRL_EN_LVLLOW

Bits Type Reset Name Description

31:0 rw 0x0 INTR_CTRL_EN_LVLLOW

gpio.CTRL_EN_INPUT_FILTER @ 0x3c

filter enable for GPIO input bits.

Reset default = 0x0, mask 0xffffffff

If CTRL_EN_INPUT_FILTER[i] is true, a value of input bit [i] must be stable for 16 cycles before transitioning.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTRL_EN_INPUT_FILTER...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...CTRL_EN_INPUT_FILTER

Bits Type Reset Name Description

31:0 rw 0x0 CTRL_EN_INPUT_FILTER

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers