Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module gpio has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
gpio[31:0]inout

GPIO inout to/from PAD

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
gpio[31:0]Event

raised if any of GPIO pin detects configured interrupt mode

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
GPIO.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
gpio.INTR_STATE 0x0 4

Interrupt State Register

gpio.INTR_ENABLE 0x4 4

Interrupt Enable Register

gpio.INTR_TEST 0x8 4

Interrupt Test Register

gpio.ALERT_TEST 0xc 4

Alert Test Register

gpio.DATA_IN 0x10 4

GPIO Input data read value

gpio.DIRECT_OUT 0x14 4

GPIO direct output data write value

gpio.MASKED_OUT_LOWER 0x18 4

GPIO write data lower with mask.

gpio.MASKED_OUT_UPPER 0x1c 4

GPIO write data upper with mask.

gpio.DIRECT_OE 0x20 4

GPIO Output Enable.

gpio.MASKED_OE_LOWER 0x24 4

GPIO write Output Enable lower with mask.

gpio.MASKED_OE_UPPER 0x28 4

GPIO write Output Enable upper with mask.

gpio.INTR_CTRL_EN_RISING 0x2c 4

GPIO interrupt enable for GPIO, rising edge.

gpio.INTR_CTRL_EN_FALLING 0x30 4

GPIO interrupt enable for GPIO, falling edge.

gpio.INTR_CTRL_EN_LVLHIGH 0x34 4

GPIO interrupt enable for GPIO, level high.

gpio.INTR_CTRL_EN_LVLLOW 0x38 4

GPIO interrupt enable for GPIO, level low.

gpio.CTRL_EN_INPUT_FILTER 0x3c 4

filter enable for GPIO input bits.

gpio.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0xffffffff
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gpio...
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...gpio
BitsTypeResetNameDescription
31:0rw1c0x0gpio

raised if any of GPIO pin detects configured interrupt mode


gpio.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0xffffffff
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gpio...
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...gpio
BitsTypeResetNameDescription
31:0rw0x0gpio

Enable interrupt when corresponding bit in INTR_STATE.gpio is set.


gpio.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0xffffffff
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gpio...
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...gpio
BitsTypeResetNameDescription
31:0wo0x0gpio

Write 1 to force corresponding bit in INTR_STATE.gpio to 1.


gpio.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


gpio.DATA_IN @ 0x10

GPIO Input data read value

Reset default = 0x0, mask 0xffffffff
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DATA_IN...
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...DATA_IN
BitsTypeResetNameDescription
31:0roxDATA_IN

gpio.DIRECT_OUT @ 0x14

GPIO direct output data write value

Reset default = 0x0, mask 0xffffffff
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DIRECT_OUT...
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...DIRECT_OUT
BitsTypeResetNameDescription
31:0rwxDIRECT_OUT

gpio.MASKED_OUT_LOWER @ 0x18

GPIO write data lower with mask.

Reset default = 0x0, mask 0xffffffff

Masked write for DATA_OUT[15:0].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OUT[15:0] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OUT[15:0].

31302928272625242322212019181716
mask
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data
BitsTypeResetNameDescription
15:0rwxdata

Write data value[15:0].

Value to write into DATA_OUT[i], valid in the presence of mask[i]==1

31:16woxmask

Write data mask[15:0].

A value of 1 in mask[i] allows the updating of DATA_OUT[i], 0 <= i <= 15


gpio.MASKED_OUT_UPPER @ 0x1c

GPIO write data upper with mask.

Reset default = 0x0, mask 0xffffffff

Masked write for DATA_OUT[31:16].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OUT[31:16] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OUT[31:16].

31302928272625242322212019181716
mask
1514131211109876543210
data
BitsTypeResetNameDescription
15:0rwxdata

Write data value[31:16].

Value to write into DATA_OUT[i], valid in the presence of mask[i]==1

31:16woxmask

Write data mask[31:16].

A value of 1 in mask[i] allows the updating of DATA_OUT[i], 16 <= i <= 31


gpio.DIRECT_OE @ 0x20

GPIO Output Enable.

Reset default = 0x0, mask 0xffffffff

Setting direct_oe[i] to 1 enables output mode for GPIO[i]

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DIRECT_OE...
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...DIRECT_OE
BitsTypeResetNameDescription
31:0rwxDIRECT_OE

gpio.MASKED_OE_LOWER @ 0x24

GPIO write Output Enable lower with mask.

Reset default = 0x0, mask 0xffffffff

Masked write for DATA_OE[15:0], the register that controls output mode for GPIO pins [15:0].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OE[15:0] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OE[15:0].

31302928272625242322212019181716
mask
1514131211109876543210
data
BitsTypeResetNameDescription
15:0rwxdata

Write OE value[15:0].

Value to write into DATA_OE[i], valid in the presence of mask[i]==1

31:16rwxmask

Write OE mask[15:0].

A value of 1 in mask[i] allows the updating of DATA_OE[i], 0 <= i <= 15


gpio.MASKED_OE_UPPER @ 0x28

GPIO write Output Enable upper with mask.

Reset default = 0x0, mask 0xffffffff

Masked write for DATA_OE[31:16], the register that controls output mode for GPIO pins [31:16].

Upper 16 bits of this register are used as mask. Writing lower 16 bits of the register changes DATA_OE[31:16] value if mask bits are set.

Read-back of this register returns upper 16 bits as zero and lower 16 bits as DATA_OE[31:16].

31302928272625242322212019181716
mask
1514131211109876543210
data
BitsTypeResetNameDescription
15:0rwxdata

Write OE value[31:16].

Value to write into DATA_OE[i], valid in the presence of mask[i]==1

31:16rwxmask

Write OE mask[31:16].

A value of 1 in mask[i] allows the updating of DATA_OE[i], 16 <= i <= 31


GPIO interrupt enable for GPIO, rising edge.

Reset default = 0x0, mask 0xffffffff

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_RISING[i] enables rising-edge interrupt detection on GPIO[i].

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INTR_CTRL_EN_RISING...
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...INTR_CTRL_EN_RISING
BitsTypeResetNameDescription
31:0rw0x0INTR_CTRL_EN_RISING

GPIO interrupt enable for GPIO, falling edge.

Reset default = 0x0, mask 0xffffffff

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_FALLING[i] enables falling-edge interrupt detection on GPIO[i].

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INTR_CTRL_EN_FALLING...
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...INTR_CTRL_EN_FALLING
BitsTypeResetNameDescription
31:0rw0x0INTR_CTRL_EN_FALLING

GPIO interrupt enable for GPIO, level high.

Reset default = 0x0, mask 0xffffffff

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_LVLHIGH[i] enables level high interrupt detection on GPIO[i].

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INTR_CTRL_EN_LVLHIGH...
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...INTR_CTRL_EN_LVLHIGH
BitsTypeResetNameDescription
31:0rw0x0INTR_CTRL_EN_LVLHIGH

GPIO interrupt enable for GPIO, level low.

Reset default = 0x0, mask 0xffffffff

If INTR_ENABLE[i] is true, a value of 1 on INTR_CTRL_EN_LVLLOW[i] enables level low interrupt detection on GPIO[i].

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INTR_CTRL_EN_LVLLOW...
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...INTR_CTRL_EN_LVLLOW
BitsTypeResetNameDescription
31:0rw0x0INTR_CTRL_EN_LVLLOW

filter enable for GPIO input bits.

Reset default = 0x0, mask 0xffffffff

If CTRL_EN_INPUT_FILTER[i] is true, a value of input bit [i] must be stable for 16 cycles before transitioning.

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CTRL_EN_INPUT_FILTER...
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...CTRL_EN_INPUT_FILTER
BitsTypeResetNameDescription
31:0rw0x0CTRL_EN_INPUT_FILTER