Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module clkmgr has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: clk_main_i, clk_io_i, clk_usb_i, clk_aon_i, clk_io_div2_i, clk_io_div4_i
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none
  • Interrupts: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
clocksclkmgr_pkg::clkmgr_outunireq1
cg_enclkmgr_pkg::clkmgr_cg_enunireq1
lc_hw_debug_enlc_ctrl_pkg::lc_txunircv1
io_clk_byp_reqprim_mubi_pkg::mubi4unireq1
io_clk_byp_ackprim_mubi_pkg::mubi4unircv1
all_clk_byp_reqprim_mubi_pkg::mubi4unireq1
all_clk_byp_ackprim_mubi_pkg::mubi4unircv1
hi_speed_selprim_mubi_pkg::mubi4unireq1
div_step_down_reqprim_mubi_pkg::mubi4unircv1
lc_clk_byp_reqlc_ctrl_pkg::lc_txunircv1
lc_clk_byp_acklc_ctrl_pkg::lc_txunireq1
jitter_enprim_mubi_pkg::mubi4unireq1
pwrpwr_clkreq_rsprsp1
idleprim_mubi_pkg::mubi4unircv4
calib_rdyprim_mubi_pkg::mubi4unircv1Indicates clocks are calibrated and frequencies accurate
tltlul_pkg::tlreq_rsprsp1

Security Alerts

Alert NameDescription
recov_faultThis recoverable alert is triggered when there are measurement errors.
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure IDDescription
CLKMGR.BUS.INTEGRITYEnd-to-end bus integrity scheme.
CLKMGR.TIMEOUT.CLK.BKGN_CHKBackground check for clock timeout.
CLKMGR.MEAS.CLK.BKGN_CHKBackground check for clock frequency.
CLKMGR.MEAS.CONFIG.SHADOWMeasurement configurations are shadowed.
CLKMGR.IDLE.INTERSIG.MUBIIdle inputs are multibit encoded.
CLKMGR.LC_CTRL.INTERSIG.MUBIThe life cycle control signals are multibit encoded.
CLKMGR.LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBIThe life cycle clock req/ack signals are multibit encoded.
CLKMGR.CLK_HANDSHAKE.INTERSIG.MUBIThe external clock req/ack signals are multibit encoded.
CLKMGR.DIV.INTERSIG.MUBIDivider step down request is multibit encoded.
CLKMGR.JITTER.CONFIG.MUBIThe jitter enable configuration is multibit encoded.
CLKMGR.IDLE.CTR.REDUNIdle counter is duplicated.
CLKMGR.MEAS.CONFIG.REGWENThe measurement controls protected with regwen.
CLKMGR.CLK_CTRL.CONFIG.REGWENSoftware controlled clock requests are proteced with regwen.

Registers

Summary

NameOffsetLengthDescription
clkmgr.ALERT_TEST0x04Alert Test Register
clkmgr.EXTCLK_CTRL_REGWEN0x44External clock control write enable
clkmgr.EXTCLK_CTRL0x84Select external clock
clkmgr.EXTCLK_STATUS0xc4Status of requested external clock switch
clkmgr.JITTER_REGWEN0x104Jitter write enable
clkmgr.JITTER_ENABLE0x144Enable jittery clock
clkmgr.CLK_ENABLES0x184Clock enable for software gateable clocks.
clkmgr.CLK_HINTS0x1c4Clock hint for software gateable transactional clocks during active mode.
clkmgr.CLK_HINTS_STATUS0x204Since the final state of !!CLK_HINTS is not always determined by software,
clkmgr.MEASURE_CTRL_REGWEN0x244Measurement control write enable
clkmgr.IO_MEAS_CTRL_EN0x284Enable for measurement control
clkmgr.IO_MEAS_CTRL_SHADOWED0x2c4Configuration controls for io measurement.
clkmgr.IO_DIV2_MEAS_CTRL_EN0x304Enable for measurement control
clkmgr.IO_DIV2_MEAS_CTRL_SHADOWED0x344Configuration controls for io_div2 measurement.
clkmgr.IO_DIV4_MEAS_CTRL_EN0x384Enable for measurement control
clkmgr.IO_DIV4_MEAS_CTRL_SHADOWED0x3c4Configuration controls for io_div4 measurement.
clkmgr.MAIN_MEAS_CTRL_EN0x404Enable for measurement control
clkmgr.MAIN_MEAS_CTRL_SHADOWED0x444Configuration controls for main measurement.
clkmgr.USB_MEAS_CTRL_EN0x484Enable for measurement control
clkmgr.USB_MEAS_CTRL_SHADOWED0x4c4Configuration controls for usb measurement.
clkmgr.RECOV_ERR_CODE0x504Recoverable Error code
clkmgr.FATAL_ERR_CODE0x544Error code

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.
0wo0x0recov_faultWrite 1 to trigger one alert event of this kind.

EXTCLK_CTRL_REGWEN

External clock control write enable

  • Offset: 0x4
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENWhen 1, the value of EXTCLK_CTRL can be set. When 0, writes to EXTCLK_CTRL have no effect.

EXTCLK_CTRL

Select external clock

Fields

BitsTypeResetName
31:8Reserved
7:4rw0x9HI_SPEED_SEL
3:0rw0x9SEL

EXTCLK_CTRL . HI_SPEED_SEL

A value of kMultiBitBool4True selects nominal speed external clock. All other values selects low speed clocks.

Note this field only has an effect when the EXTCLK_CTRL.SEL field is set to kMultiBitBool4True.

Nominal speed means the external clock is approximately the same frequency as the internal oscillator source. When this option is used, all clocks operate at roughly the nominal frequency.

Low speed means the external clock is approximately half the frequency of the internal oscillator source. When this option is used, the internal dividers are stepped down. As a result, previously undivided clocks now run at half frequency, while previously divided clocks run at roughly the nominal frequency.

See external clock switch support in documentation for more details.

EXTCLK_CTRL . SEL

When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True selects external clock as clock for the system. Writing any other value has no impact.

When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False selects internal clock as clock for the system. Writing any other value during this stage has no impact.

While this register can always be programmed, it only takes effect when debug functions are enabled in life cycle TEST, DEV or RMA states.

EXTCLK_STATUS

Status of requested external clock switch

  • Offset: 0xc
  • Reset default: 0x9
  • Reset mask: 0xf

Fields

BitsTypeResetName
31:4Reserved
3:0ro0x9ACK

EXTCLK_STATUS . ACK

When EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects whether the clock has been switched the external source.

kMultiBitBool4True indicates the switch is complete. kMultiBitBool4False indicates the switch is either not possible or still ongoing.

JITTER_REGWEN

Jitter write enable

  • Offset: 0x10
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENWhen 1, the value of JITTER_ENABLE can be changed. When 0, writes have no effect.

JITTER_ENABLE

Enable jittery clock

  • Offset: 0x14
  • Reset default: 0x9
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw0x9VALEnable jittery clock. A value of kMultiBitBool4False disables the jittery clock, while all other values enable jittery clock.

CLK_ENABLES

Clock enable for software gateable clocks. These clocks are directly controlled by software.

  • Offset: 0x18
  • Reset default: 0xf
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw0x1CLK_USB_PERI_EN0 CLK_USB_PERI is disabled. 1 CLK_USB_PERI is enabled.
2rw0x1CLK_IO_PERI_EN0 CLK_IO_PERI is disabled. 1 CLK_IO_PERI is enabled.
1rw0x1CLK_IO_DIV2_PERI_EN0 CLK_IO_DIV2_PERI is disabled. 1 CLK_IO_DIV2_PERI is enabled.
0rw0x1CLK_IO_DIV4_PERI_EN0 CLK_IO_DIV4_PERI is disabled. 1 CLK_IO_DIV4_PERI is enabled.

CLK_HINTS

Clock hint for software gateable transactional clocks during active mode. During low power mode, all clocks are gated off regardless of the software hint.

Transactional clocks are not fully controlled by software. Instead software provides only a disable hint.

When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. If the hardware block is idle, then the clock is disabled. If the hardware block is not idle, the clock is kept on.

For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any feedback in this case.

  • Offset: 0x1c
  • Reset default: 0xf
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw0x1CLK_MAIN_OTBN_HINT0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled.
2rw0x1CLK_MAIN_KMAC_HINT0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled.
1rw0x1CLK_MAIN_HMAC_HINT0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled.
0rw0x1CLK_MAIN_AES_HINT0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled.

CLK_HINTS_STATUS

Since the final state of CLK_HINTS is not always determined by software, this register provides read feedback for the current clock state.

  • Offset: 0x20
  • Reset default: 0xf
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3ro0x1CLK_MAIN_OTBN_VAL0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled.
2ro0x1CLK_MAIN_KMAC_VAL0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled.
1ro0x1CLK_MAIN_HMAC_VAL0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled.
0ro0x1CLK_MAIN_AES_VAL0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled.

MEASURE_CTRL_REGWEN

Measurement control write enable

  • Offset: 0x24
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ENWhen 1, the value of the measurement control can be set. When 0, writes have no effect.

IO_MEAS_CTRL_EN

Enable for measurement control

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw0x9ENEnable measurement for io

IO_MEAS_CTRL_SHADOWED

Configuration controls for io measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

Fields

BitsTypeResetNameDescription
31:20Reserved
19:10rw0x1d6LOMin threshold for io measurement
9:0rw0x1eaHIMax threshold for io measurement

IO_DIV2_MEAS_CTRL_EN

Enable for measurement control

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw0x9ENEnable measurement for io_div2

IO_DIV2_MEAS_CTRL_SHADOWED

Configuration controls for io_div2 measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

Fields

BitsTypeResetNameDescription
31:18Reserved
17:9rw0xe6LOMin threshold for io_div2 measurement
8:0rw0xfaHIMax threshold for io_div2 measurement

IO_DIV4_MEAS_CTRL_EN

Enable for measurement control

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw0x9ENEnable measurement for io_div4

IO_DIV4_MEAS_CTRL_SHADOWED

Configuration controls for io_div4 measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

Fields

BitsTypeResetNameDescription
31:16Reserved
15:8rw0x6eLOMin threshold for io_div4 measurement
7:0rw0x82HIMax threshold for io_div4 measurement

MAIN_MEAS_CTRL_EN

Enable for measurement control

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw0x9ENEnable measurement for main

MAIN_MEAS_CTRL_SHADOWED

Configuration controls for main measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

Fields

BitsTypeResetNameDescription
31:20Reserved
19:10rw0x1eaLOMin threshold for main measurement
9:0rw0x1feHIMax threshold for main measurement

USB_MEAS_CTRL_EN

Enable for measurement control

Fields

BitsTypeResetNameDescription
31:4Reserved
3:0rw0x9ENEnable measurement for usb

USB_MEAS_CTRL_SHADOWED

Configuration controls for usb measurement.

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

Fields

BitsTypeResetNameDescription
31:18Reserved
17:9rw0xe6LOMin threshold for usb measurement
8:0rw0xfaHIMax threshold for usb measurement

RECOV_ERR_CODE

Recoverable Error code

  • Offset: 0x50
  • Reset default: 0x0
  • Reset mask: 0x7ff

Fields

BitsTypeResetNameDescription
31:11Reserved
10rw1c0x0USB_TIMEOUT_ERRusb has timed out.
9rw1c0x0MAIN_TIMEOUT_ERRmain has timed out.
8rw1c0x0IO_DIV4_TIMEOUT_ERRio_div4 has timed out.
7rw1c0x0IO_DIV2_TIMEOUT_ERRio_div2 has timed out.
6rw1c0x0IO_TIMEOUT_ERRio has timed out.
5rw1c0x0USB_MEASURE_ERRusb has encountered a measurement error.
4rw1c0x0MAIN_MEASURE_ERRmain has encountered a measurement error.
3rw1c0x0IO_DIV4_MEASURE_ERRio_div4 has encountered a measurement error.
2rw1c0x0IO_DIV2_MEASURE_ERRio_div2 has encountered a measurement error.
1rw1c0x0IO_MEASURE_ERRio has encountered a measurement error.
0rw1c0x0SHADOW_UPDATE_ERROne of the shadow registers encountered an update error.

FATAL_ERR_CODE

Error code

  • Offset: 0x54
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

BitsTypeResetNameDescription
31:3Reserved
2ro0x0SHADOW_STORAGE_ERROne of the shadow registers encountered a storage error.
1ro0x0IDLE_CNTOne of the idle counts encountered a duplicate error.
0ro0x0REG_INTGRegister file has experienced a fatal integrity error.