Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module clkmgr has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_main_i, clk_io_i, clk_usb_i, clk_aon_i, clk_io_div2_i, clk_io_div4_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
clocks clkmgr_pkg::clkmgr_out uni req 1
cg_en clkmgr_pkg::clkmgr_cg_en uni req 1
lc_hw_debug_en lc_ctrl_pkg::lc_tx uni rcv 1
io_clk_byp_req prim_mubi_pkg::mubi4 uni req 1
io_clk_byp_ack prim_mubi_pkg::mubi4 uni rcv 1
all_clk_byp_req prim_mubi_pkg::mubi4 uni req 1
all_clk_byp_ack prim_mubi_pkg::mubi4 uni rcv 1
hi_speed_sel prim_mubi_pkg::mubi4 uni req 1
div_step_down_req prim_mubi_pkg::mubi4 uni rcv 1
lc_clk_byp_req lc_ctrl_pkg::lc_tx uni rcv 1
lc_clk_byp_ack lc_ctrl_pkg::lc_tx uni req 1
jitter_en prim_mubi_pkg::mubi4 uni req 1
pwr pwr_clk req_rsp rsp 1
idle prim_mubi_pkg::mubi4 uni rcv 4
calib_rdy prim_mubi_pkg::mubi4 uni rcv 1 Indicates clocks are calibrated and frequencies accurate
tl tlul_pkg::tl req_rsp rsp 1

Interrupts: none

Security Alerts:

Alert NameDescription
recov_fault

This recoverable alert is triggered when there are measurement errors.

fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
CLKMGR.BUS.INTEGRITY

End-to-end bus integrity scheme.

CLKMGR.TIMEOUT.CLK.BKGN_CHK

Background check for clock timeout.

CLKMGR.MEAS.CLK.BKGN_CHK

Background check for clock frequency.

CLKMGR.MEAS.CONFIG.SHADOW

Measurement configurations are shadowed.

CLKMGR.IDLE.INTERSIG.MUBI

Idle inputs are multibit encoded.

CLKMGR.LC_CTRL.INTERSIG.MUBI

The life cycle control signals are multibit encoded.

CLKMGR.LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI

The life cycle clock req/ack signals are multibit encoded.

CLKMGR.CLK_HANDSHAKE.INTERSIG.MUBI

The external clock req/ack signals are multibit encoded.

CLKMGR.DIV.INTERSIG.MUBI

Divider step down request is multibit encoded.

CLKMGR.JITTER.CONFIG.MUBI

The jitter enable configuration is multibit encoded.

CLKMGR.IDLE.CTR.REDUN

Idle counter is duplicated.

CLKMGR.MEAS.CONFIG.REGWEN

The measurement controls protected with regwen.

CLKMGR.CLK_CTRL.CONFIG.REGWEN

Software controlled clock requests are proteced with regwen.

Registers

Summary
Name Offset Length Description
clkmgr.ALERT_TEST 0x0 4

Alert Test Register

clkmgr.EXTCLK_CTRL_REGWEN 0x4 4

External clock control write enable

clkmgr.EXTCLK_CTRL 0x8 4

Select external clock

clkmgr.EXTCLK_STATUS 0xc 4

Status of requested external clock switch

clkmgr.JITTER_REGWEN 0x10 4

Jitter write enable

clkmgr.JITTER_ENABLE 0x14 4

Enable jittery clock

clkmgr.CLK_ENABLES 0x18 4

Clock enable for software gateable clocks. These clocks are directly controlled by software.

clkmgr.CLK_HINTS 0x1c 4

Clock hint for software gateable transactional clocks during active mode. During low power mode, all clocks are gated off regardless of the software hint.

clkmgr.CLK_HINTS_STATUS 0x20 4

Since the final state of CLK_HINTS is not always determined by software, this register provides read feedback for the current clock state.

clkmgr.MEASURE_CTRL_REGWEN 0x24 4

Measurement control write enable

clkmgr.IO_MEAS_CTRL_EN 0x28 4

Enable for measurement control

clkmgr.IO_MEAS_CTRL_SHADOWED 0x2c 4

Configuration controls for io measurement.

clkmgr.IO_DIV2_MEAS_CTRL_EN 0x30 4

Enable for measurement control

clkmgr.IO_DIV2_MEAS_CTRL_SHADOWED 0x34 4

Configuration controls for io_div2 measurement.

clkmgr.IO_DIV4_MEAS_CTRL_EN 0x38 4

Enable for measurement control

clkmgr.IO_DIV4_MEAS_CTRL_SHADOWED 0x3c 4

Configuration controls for io_div4 measurement.

clkmgr.MAIN_MEAS_CTRL_EN 0x40 4

Enable for measurement control

clkmgr.MAIN_MEAS_CTRL_SHADOWED 0x44 4

Configuration controls for main measurement.

clkmgr.USB_MEAS_CTRL_EN 0x48 4

Enable for measurement control

clkmgr.USB_MEAS_CTRL_SHADOWED 0x4c 4

Configuration controls for usb measurement.

clkmgr.RECOV_ERR_CODE 0x50 4

Recoverable Error code

clkmgr.FATAL_ERR_CODE 0x54 4

Error code

clkmgr.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x3
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  fatal_fault recov_fault
BitsTypeResetNameDescription
0wo0x0recov_fault

Write 1 to trigger one alert event of this kind.

1wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


clkmgr.EXTCLK_CTRL_REGWEN @ 0x4

External clock control write enable

Reset default = 0x1, mask 0x1
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BitsTypeResetNameDescription
0rw0c0x1EN

When 1, the value of EXTCLK_CTRL can be set. When 0, writes to EXTCLK_CTRL have no effect.


clkmgr.EXTCLK_CTRL @ 0x8

Select external clock

Reset default = 0x99, mask 0xff
Register enable = EXTCLK_CTRL_REGWEN
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  HI_SPEED_SEL SEL
BitsTypeResetNameDescription
3:0rw0x9SEL

When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True selects external clock as clock for the system. Writing any other value has no impact.

When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False selects internal clock as clock for the system. Writing any other value during this stage has no impact.

While this register can always be programmed, it only takes effect when debug functions are enabled in life cycle TEST, DEV or RMA states.

7:4rw0x9HI_SPEED_SEL

A value of kMultiBitBool4True selects nominal speed external clock. All other values selects low speed clocks.

Note this field only has an effect when the EXTCLK_CTRL.SEL field is set to kMultiBitBool4True.

Nominal speed means the external clock is approximately the same frequency as the internal oscillator source. When this option is used, all clocks operate at roughly the nominal frequency.

Low speed means the external clock is approximately half the frequency of the internal oscillator source. When this option is used, the internal dividers are stepped down. As a result, previously undivided clocks now run at half frequency, while previously divided clocks run at roughly the nominal frequency.

See external clock switch support in documentation for more details.


clkmgr.EXTCLK_STATUS @ 0xc

Status of requested external clock switch

Reset default = 0x9, mask 0xf
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  ACK
BitsTypeResetNameDescription
3:0ro0x9ACK

When EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects whether the clock has been switched the external source.

kMultiBitBool4True indicates the switch is complete. kMultiBitBool4False indicates the switch is either not possible or still ongoing.


clkmgr.JITTER_REGWEN @ 0x10

Jitter write enable

Reset default = 0x1, mask 0x1
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BitsTypeResetNameDescription
0rw0c0x1EN

When 1, the value of JITTER_ENABLE can be changed. When 0, writes have no effect.


clkmgr.JITTER_ENABLE @ 0x14

Enable jittery clock

Reset default = 0x9, mask 0xf
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  VAL
BitsTypeResetNameDescription
3:0rw0x9VAL

Enable jittery clock. A value of kMultiBitBool4False disables the jittery clock, while all other values enable jittery clock.


clkmgr.CLK_ENABLES @ 0x18

Clock enable for software gateable clocks. These clocks are directly controlled by software.

Reset default = 0xf, mask 0xf
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  CLK_USB_PERI_EN CLK_IO_PERI_EN CLK_IO_DIV2_PERI_EN CLK_IO_DIV4_PERI_EN
BitsTypeResetNameDescription
0rw0x1CLK_IO_DIV4_PERI_EN

0 CLK_IO_DIV4_PERI is disabled. 1 CLK_IO_DIV4_PERI is enabled.

1rw0x1CLK_IO_DIV2_PERI_EN

0 CLK_IO_DIV2_PERI is disabled. 1 CLK_IO_DIV2_PERI is enabled.

2rw0x1CLK_IO_PERI_EN

0 CLK_IO_PERI is disabled. 1 CLK_IO_PERI is enabled.

3rw0x1CLK_USB_PERI_EN

0 CLK_USB_PERI is disabled. 1 CLK_USB_PERI is enabled.


clkmgr.CLK_HINTS @ 0x1c

Clock hint for software gateable transactional clocks during active mode. During low power mode, all clocks are gated off regardless of the software hint.

Reset default = 0xf, mask 0xf

Transactional clocks are not fully controlled by software. Instead software provides only a disable hint.

When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. If the hardware block is idle, then the clock is disabled. If the hardware block is not idle, the clock is kept on.

For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any feedback in this case.

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  CLK_MAIN_OTBN_HINT CLK_MAIN_KMAC_HINT CLK_MAIN_HMAC_HINT CLK_MAIN_AES_HINT
BitsTypeResetNameDescription
0rw0x1CLK_MAIN_AES_HINT

0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled.

1rw0x1CLK_MAIN_HMAC_HINT

0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled.

2rw0x1CLK_MAIN_KMAC_HINT

0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled.

3rw0x1CLK_MAIN_OTBN_HINT

0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled.


clkmgr.CLK_HINTS_STATUS @ 0x20

Since the final state of CLK_HINTS is not always determined by software, this register provides read feedback for the current clock state.

Reset default = 0xf, mask 0xf
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  CLK_MAIN_OTBN_VAL CLK_MAIN_KMAC_VAL CLK_MAIN_HMAC_VAL CLK_MAIN_AES_VAL
BitsTypeResetNameDescription
0ro0x1CLK_MAIN_AES_VAL

0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled.

1ro0x1CLK_MAIN_HMAC_VAL

0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled.

2ro0x1CLK_MAIN_KMAC_VAL

0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled.

3ro0x1CLK_MAIN_OTBN_VAL

0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled.


clkmgr.MEASURE_CTRL_REGWEN @ 0x24

Measurement control write enable

Reset default = 0x1, mask 0x1
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BitsTypeResetNameDescription
0rw0c0x1EN

When 1, the value of the measurement control can be set. When 0, writes have no effect.


clkmgr.IO_MEAS_CTRL_EN @ 0x28

Enable for measurement control

Reset default = 0x9, mask 0xf
Register enable = MEASURE_CTRL_REGWEN
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BitsTypeResetNameDescription
3:0rw0x9EN

Enable measurement for io


clkmgr.IO_MEAS_CTRL_SHADOWED @ 0x2c

Configuration controls for io measurement.

Reset default = 0x759ea, mask 0xfffff
Register enable = MEASURE_CTRL_REGWEN

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

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BitsTypeResetNameDescription
9:0rw0x1eaHI

Max threshold for io measurement

19:10rw0x1d6LO

Min threshold for io measurement


clkmgr.IO_DIV2_MEAS_CTRL_EN @ 0x30

Enable for measurement control

Reset default = 0x9, mask 0xf
Register enable = MEASURE_CTRL_REGWEN
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BitsTypeResetNameDescription
3:0rw0x9EN

Enable measurement for io_div2


Configuration controls for io_div2 measurement.

Reset default = 0x1ccfa, mask 0x3ffff
Register enable = MEASURE_CTRL_REGWEN

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

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...LO HI
BitsTypeResetNameDescription
8:0rw0xfaHI

Max threshold for io_div2 measurement

17:9rw0xe6LO

Min threshold for io_div2 measurement


clkmgr.IO_DIV4_MEAS_CTRL_EN @ 0x38

Enable for measurement control

Reset default = 0x9, mask 0xf
Register enable = MEASURE_CTRL_REGWEN
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BitsTypeResetNameDescription
3:0rw0x9EN

Enable measurement for io_div4


Configuration controls for io_div4 measurement.

Reset default = 0x6e82, mask 0xffff
Register enable = MEASURE_CTRL_REGWEN

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

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LO HI
BitsTypeResetNameDescription
7:0rw0x82HI

Max threshold for io_div4 measurement

15:8rw0x6eLO

Min threshold for io_div4 measurement


clkmgr.MAIN_MEAS_CTRL_EN @ 0x40

Enable for measurement control

Reset default = 0x9, mask 0xf
Register enable = MEASURE_CTRL_REGWEN
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BitsTypeResetNameDescription
3:0rw0x9EN

Enable measurement for main


Configuration controls for main measurement.

Reset default = 0x7a9fe, mask 0xfffff
Register enable = MEASURE_CTRL_REGWEN

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

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BitsTypeResetNameDescription
9:0rw0x1feHI

Max threshold for main measurement

19:10rw0x1eaLO

Min threshold for main measurement


clkmgr.USB_MEAS_CTRL_EN @ 0x48

Enable for measurement control

Reset default = 0x9, mask 0xf
Register enable = MEASURE_CTRL_REGWEN
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BitsTypeResetNameDescription
3:0rw0x9EN

Enable measurement for usb


Configuration controls for usb measurement.

Reset default = 0x1ccfa, mask 0x3ffff
Register enable = MEASURE_CTRL_REGWEN

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

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...LO HI
BitsTypeResetNameDescription
8:0rw0xfaHI

Max threshold for usb measurement

17:9rw0xe6LO

Min threshold for usb measurement


clkmgr.RECOV_ERR_CODE @ 0x50

Recoverable Error code

Reset default = 0x0, mask 0x7ff
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  USB_TIMEOUT_ERR MAIN_TIMEOUT_ERR IO_DIV4_TIMEOUT_ERR IO_DIV2_TIMEOUT_ERR IO_TIMEOUT_ERR USB_MEASURE_ERR MAIN_MEASURE_ERR IO_DIV4_MEASURE_ERR IO_DIV2_MEASURE_ERR IO_MEASURE_ERR SHADOW_UPDATE_ERR
BitsTypeResetNameDescription
0rw1c0x0SHADOW_UPDATE_ERR

One of the shadow registers encountered an update error.

1rw1c0x0IO_MEASURE_ERR

io has encountered a measurement error.

2rw1c0x0IO_DIV2_MEASURE_ERR

io_div2 has encountered a measurement error.

3rw1c0x0IO_DIV4_MEASURE_ERR

io_div4 has encountered a measurement error.

4rw1c0x0MAIN_MEASURE_ERR

main has encountered a measurement error.

5rw1c0x0USB_MEASURE_ERR

usb has encountered a measurement error.

6rw1c0x0IO_TIMEOUT_ERR

io has timed out.

7rw1c0x0IO_DIV2_TIMEOUT_ERR

io_div2 has timed out.

8rw1c0x0IO_DIV4_TIMEOUT_ERR

io_div4 has timed out.

9rw1c0x0MAIN_TIMEOUT_ERR

main has timed out.

10rw1c0x0USB_TIMEOUT_ERR

usb has timed out.


clkmgr.FATAL_ERR_CODE @ 0x54

Error code

Reset default = 0x0, mask 0x7
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  SHADOW_STORAGE_ERR IDLE_CNT REG_INTG
BitsTypeResetNameDescription
0ro0x0REG_INTG

Register file has experienced a fatal integrity error.

1ro0x0IDLE_CNT

One of the idle counts encountered a duplicate error.

2ro0x0SHADOW_STORAGE_ERR

One of the shadow registers encountered a storage error.