Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module clkmgr has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_main_i, clk_io_i, clk_usb_i, clk_aon_i, clk_io_div2_i, clk_io_div4_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width	Description
clocks	clkmgr_pkg::clkmgr_out	uni	req	1
cg_en	clkmgr_pkg::clkmgr_cg_en	uni	req	1
lc_hw_debug_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
io_clk_byp_req	prim_mubi_pkg::mubi4	uni	req	1
io_clk_byp_ack	prim_mubi_pkg::mubi4	uni	rcv	1
all_clk_byp_req	prim_mubi_pkg::mubi4	uni	req	1
all_clk_byp_ack	prim_mubi_pkg::mubi4	uni	rcv	1
hi_speed_sel	prim_mubi_pkg::mubi4	uni	req	1
div_step_down_req	prim_mubi_pkg::mubi4	uni	rcv	1
lc_clk_byp_req	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_clk_byp_ack	lc_ctrl_pkg::lc_tx	uni	req	1
jitter_en	prim_mubi_pkg::mubi4	uni	req	1
pwr	pwr_clk	req_rsp	rsp	1
idle	prim_mubi_pkg::mubi4	uni	rcv	4
calib_rdy	prim_mubi_pkg::mubi4	uni	rcv	1	Indicates clocks are calibrated and frequencies accurate
tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts: none

Security Alerts:

Alert Name	Description
recov_fault	This recoverable alert is triggered when there are measurement errors.
fatal_fault	This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure ID	Description
CLKMGR.BUS.INTEGRITY	End-to-end bus integrity scheme.
CLKMGR.TIMEOUT.CLK.BKGN_CHK	Background check for clock timeout.
CLKMGR.MEAS.CLK.BKGN_CHK	Background check for clock frequency.
CLKMGR.MEAS.CONFIG.SHADOW	Measurement configurations are shadowed.
CLKMGR.IDLE.INTERSIG.MUBI	Idle inputs are multibit encoded.
CLKMGR.LC_CTRL.INTERSIG.MUBI	The life cycle control signals are multibit encoded.
CLKMGR.LC_CTRL_CLK_HANDSHAKE.INTERSIG.MUBI	The life cycle clock req/ack signals are multibit encoded.
CLKMGR.CLK_HANDSHAKE.INTERSIG.MUBI	The external clock req/ack signals are multibit encoded.
CLKMGR.DIV.INTERSIG.MUBI	Divider step down request is multibit encoded.
CLKMGR.JITTER.CONFIG.MUBI	The jitter enable configuration is multibit encoded.
CLKMGR.IDLE.CTR.REDUN	Idle counter is duplicated.
CLKMGR.MEAS.CONFIG.REGWEN	The measurement controls protected with regwen.
CLKMGR.CLK_CTRL.CONFIG.REGWEN	Software controlled clock requests are proteced with regwen.

Registers

Summary
Name	Offset	Length	Description
clkmgr.ALERT_TEST	0x0	4	Alert Test Register
clkmgr.EXTCLK_CTRL_REGWEN	0x4	4	External clock control write enable
clkmgr.EXTCLK_CTRL	0x8	4	Select external clock
clkmgr.EXTCLK_STATUS	0xc	4	Status of requested external clock switch
clkmgr.JITTER_REGWEN	0x10	4	Jitter write enable
clkmgr.JITTER_ENABLE	0x14	4	Enable jittery clock
clkmgr.CLK_ENABLES	0x18	4	Clock enable for software gateable clocks. These clocks are directly controlled by software.
clkmgr.CLK_HINTS	0x1c	4	Clock hint for software gateable transactional clocks during active mode. During low power mode, all clocks are gated off regardless of the software hint.
clkmgr.CLK_HINTS_STATUS	0x20	4	Since the final state of `CLK_HINTS` is not always determined by software, this register provides read feedback for the current clock state.
clkmgr.MEASURE_CTRL_REGWEN	0x24	4	Measurement control write enable
clkmgr.IO_MEAS_CTRL_EN	0x28	4	Enable for measurement control
clkmgr.IO_MEAS_CTRL_SHADOWED	0x2c	4	Configuration controls for io measurement.
clkmgr.IO_DIV2_MEAS_CTRL_EN	0x30	4	Enable for measurement control
clkmgr.IO_DIV2_MEAS_CTRL_SHADOWED	0x34	4	Configuration controls for io_div2 measurement.
clkmgr.IO_DIV4_MEAS_CTRL_EN	0x38	4	Enable for measurement control
clkmgr.IO_DIV4_MEAS_CTRL_SHADOWED	0x3c	4	Configuration controls for io_div4 measurement.
clkmgr.MAIN_MEAS_CTRL_EN	0x40	4	Enable for measurement control
clkmgr.MAIN_MEAS_CTRL_SHADOWED	0x44	4	Configuration controls for main measurement.
clkmgr.USB_MEAS_CTRL_EN	0x48	4	Enable for measurement control
clkmgr.USB_MEAS_CTRL_SHADOWED	0x4c	4	Configuration controls for usb measurement.
clkmgr.RECOV_ERR_CODE	0x50	4	Recoverable Error code
clkmgr.FATAL_ERR_CODE	0x54	4	Error code

clkmgr.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														fatal_fault	recov_fault

Bits

Type

Reset

Name

Description

0x0

recov_fault

Write 1 to trigger one alert event of this kind.

0x0

fatal_fault

Write 1 to trigger one alert event of this kind.

clkmgr.EXTCLK_CTRL_REGWEN @ 0x4

External clock control write enable

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN

Bits Type Reset Name Description

rw0c

0x1

When 1, the value of EXTCLK_CTRL can be set. When 0, writes to EXTCLK_CTRL have no effect.

clkmgr.EXTCLK_CTRL @ 0x8

Select external clock

Reset default = 0x99, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								HI_SPEED_SEL				SEL

Bits Type Reset Name Description

3:0

0x9

SEL

When the current value is not kMultiBitBool4True, writing a value of kMultiBitBool4True selects external clock as clock for the system. Writing any other value has no impact.

When the current value is kMultiBitBool4True, writing a value of kMultiBitBool4False selects internal clock as clock for the system. Writing any other value during this stage has no impact.

While this register can always be programmed, it only takes effect when debug functions are enabled in life cycle TEST, DEV or RMA states.

7:4

0x9

HI_SPEED_SEL

A value of kMultiBitBool4True selects nominal speed external clock. All other values selects low speed clocks.

Note this field only has an effect when the EXTCLK_CTRL.SEL field is set to kMultiBitBool4True.

Nominal speed means the external clock is approximately the same frequency as the internal oscillator source. When this option is used, all clocks operate at roughly the nominal frequency.

Low speed means the external clock is approximately half the frequency of the internal oscillator source. When this option is used, the internal dividers are stepped down. As a result, previously undivided clocks now run at half frequency, while previously divided clocks run at roughly the nominal frequency.

See external clock switch support in documentation for more details.

clkmgr.EXTCLK_STATUS @ 0xc

Status of requested external clock switch

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ACK

Bits Type Reset Name Description

3:0

0x9

ACK

When EXTCLK_CTRL.SEL is set to kMultiBitBool4True, this field reflects whether the clock has been switched the external source.

kMultiBitBool4True indicates the switch is complete. kMultiBitBool4False indicates the switch is either not possible or still ongoing.

clkmgr.JITTER_REGWEN @ 0x10

Jitter write enable

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN

Bits Type Reset Name Description

rw0c

0x1

When 1, the value of JITTER_ENABLE can be changed. When 0, writes have no effect.

clkmgr.JITTER_ENABLE @ 0x14

Enable jittery clock

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VAL

Bits

Type

Reset

Name

Description

3:0

0x9

VAL

Enable jittery clock. A value of kMultiBitBool4False disables the jittery clock, while all other values enable jittery clock.

clkmgr.CLK_ENABLES @ 0x18

Clock enable for software gateable clocks. These clocks are directly controlled by software.

Reset default = 0xf, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CLK_USB_PERI_EN	CLK_IO_PERI_EN	CLK_IO_DIV2_PERI_EN	CLK_IO_DIV4_PERI_EN

Bits

Type

Reset

Name

Description

0x1

CLK_IO_DIV4_PERI_EN

0 CLK_IO_DIV4_PERI is disabled. 1 CLK_IO_DIV4_PERI is enabled.

0x1

CLK_IO_DIV2_PERI_EN

0 CLK_IO_DIV2_PERI is disabled. 1 CLK_IO_DIV2_PERI is enabled.

0x1

CLK_IO_PERI_EN

0 CLK_IO_PERI is disabled. 1 CLK_IO_PERI is enabled.

0x1

CLK_USB_PERI_EN

0 CLK_USB_PERI is disabled. 1 CLK_USB_PERI is enabled.

clkmgr.CLK_HINTS @ 0x1c

Clock hint for software gateable transactional clocks during active mode. During low power mode, all clocks are gated off regardless of the software hint.

Reset default = 0xf, mask 0xf

Transactional clocks are not fully controlled by software. Instead software provides only a disable hint.

When software provides a disable hint, the clock manager checks to see if the associated hardware block is idle. If the hardware block is idle, then the clock is disabled. If the hardware block is not idle, the clock is kept on.

For the enable case, the software hint is immediately honored and the clock turned on. Hardware does not provide any feedback in this case.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CLK_MAIN_OTBN_HINT	CLK_MAIN_KMAC_HINT	CLK_MAIN_HMAC_HINT	CLK_MAIN_AES_HINT

Bits

Type

Reset

Name

Description

0x1

CLK_MAIN_AES_HINT

0 CLK_MAIN_AES can be disabled. 1 CLK_MAIN_AES is enabled.

0x1

CLK_MAIN_HMAC_HINT

0 CLK_MAIN_HMAC can be disabled. 1 CLK_MAIN_HMAC is enabled.

0x1

CLK_MAIN_KMAC_HINT

0 CLK_MAIN_KMAC can be disabled. 1 CLK_MAIN_KMAC is enabled.

0x1

CLK_MAIN_OTBN_HINT

0 CLK_MAIN_OTBN can be disabled. 1 CLK_MAIN_OTBN is enabled.

clkmgr.CLK_HINTS_STATUS @ 0x20

Since the final state of CLK_HINTS is not always determined by software, this register provides read feedback for the current clock state.

Reset default = 0xf, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CLK_MAIN_OTBN_VAL	CLK_MAIN_KMAC_VAL	CLK_MAIN_HMAC_VAL	CLK_MAIN_AES_VAL

Bits Type Reset Name Description

0x1

CLK_MAIN_AES_VAL

0 CLK_MAIN_AES is disabled. 1 CLK_MAIN_AES is enabled.

0x1

CLK_MAIN_HMAC_VAL

0 CLK_MAIN_HMAC is disabled. 1 CLK_MAIN_HMAC is enabled.

0x1

CLK_MAIN_KMAC_VAL

0 CLK_MAIN_KMAC is disabled. 1 CLK_MAIN_KMAC is enabled.

0x1

CLK_MAIN_OTBN_VAL

0 CLK_MAIN_OTBN is disabled. 1 CLK_MAIN_OTBN is enabled.

clkmgr.MEASURE_CTRL_REGWEN @ 0x24

Measurement control write enable

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN

Bits

Type

Reset

Name

Description

rw0c

0x1

When 1, the value of the measurement control can be set. When 0, writes have no effect.

clkmgr.IO_MEAS_CTRL_EN @ 0x28

Enable for measurement control

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												EN

Bits

Type

Reset

Name

Description

3:0

0x9

Enable measurement for io

clkmgr.IO_MEAS_CTRL_SHADOWED @ 0x2c

Configuration controls for io measurement.

Reset default = 0x759ea, mask 0xfffff

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												LO...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...LO						HI

Bits

Type

Reset

Name

Description

9:0

0x1ea

Max threshold for io measurement

19:10

0x1d6

Min threshold for io measurement

clkmgr.IO_DIV2_MEAS_CTRL_EN @ 0x30

Enable for measurement control

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												EN

Bits

Type

Reset

Name

Description

3:0

0x9

Enable measurement for io_div2

clkmgr.IO_DIV2_MEAS_CTRL_SHADOWED @ 0x34

Configuration controls for io_div2 measurement.

Reset default = 0x1ccfa, mask 0x3ffff

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														LO...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...LO							HI

Bits

Type

Reset

Name

Description

8:0

0xfa

Max threshold for io_div2 measurement

17:9

0xe6

Min threshold for io_div2 measurement

clkmgr.IO_DIV4_MEAS_CTRL_EN @ 0x38

Enable for measurement control

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												EN

Bits

Type

Reset

Name

Description

3:0

0x9

Enable measurement for io_div4

clkmgr.IO_DIV4_MEAS_CTRL_SHADOWED @ 0x3c

Configuration controls for io_div4 measurement.

Reset default = 0x6e82, mask 0xffff

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LO								HI

Bits

Type

Reset

Name

Description

7:0

0x82

Max threshold for io_div4 measurement

15:8

0x6e

Min threshold for io_div4 measurement

clkmgr.MAIN_MEAS_CTRL_EN @ 0x40

Enable for measurement control

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												EN

Bits

Type

Reset

Name

Description

3:0

0x9

Enable measurement for main

clkmgr.MAIN_MEAS_CTRL_SHADOWED @ 0x44

Configuration controls for main measurement.

Reset default = 0x7a9fe, mask 0xfffff

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												LO...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...LO						HI

Bits

Type

Reset

Name

Description

9:0

0x1fe

Max threshold for main measurement

19:10

0x1ea

Min threshold for main measurement

clkmgr.USB_MEAS_CTRL_EN @ 0x48

Enable for measurement control

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												EN

Bits

Type

Reset

Name

Description

3:0

0x9

Enable measurement for usb

clkmgr.USB_MEAS_CTRL_SHADOWED @ 0x4c

Configuration controls for usb measurement.

Reset default = 0x1ccfa, mask 0x3ffff

The threshold fields are made wider than required (by 1 bit) to ensure there is room to adjust for measurement inaccuracies.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														LO...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...LO							HI

Bits

Type

Reset

Name

Description

8:0

0xfa

Max threshold for usb measurement

17:9

0xe6

Min threshold for usb measurement

clkmgr.RECOV_ERR_CODE @ 0x50

Recoverable Error code

Reset default = 0x0, mask 0x7ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					USB_TIMEOUT_ERR	MAIN_TIMEOUT_ERR	IO_DIV4_TIMEOUT_ERR	IO_DIV2_TIMEOUT_ERR	IO_TIMEOUT_ERR	USB_MEASURE_ERR	MAIN_MEASURE_ERR	IO_DIV4_MEASURE_ERR	IO_DIV2_MEASURE_ERR	IO_MEASURE_ERR	SHADOW_UPDATE_ERR

Bits

Type

Reset

Name

Description

rw1c

0x0

SHADOW_UPDATE_ERR

One of the shadow registers encountered an update error.

rw1c

0x0

IO_MEASURE_ERR

io has encountered a measurement error.

rw1c

0x0

IO_DIV2_MEASURE_ERR

io_div2 has encountered a measurement error.

rw1c

0x0

IO_DIV4_MEASURE_ERR

io_div4 has encountered a measurement error.

rw1c

0x0

MAIN_MEASURE_ERR

main has encountered a measurement error.

rw1c

0x0

USB_MEASURE_ERR

usb has encountered a measurement error.

rw1c

0x0

IO_TIMEOUT_ERR

io has timed out.

rw1c

0x0

IO_DIV2_TIMEOUT_ERR

io_div2 has timed out.

rw1c

0x0

IO_DIV4_TIMEOUT_ERR

io_div4 has timed out.

rw1c

0x0

MAIN_TIMEOUT_ERR

main has timed out.

rw1c

0x0

USB_TIMEOUT_ERR

usb has timed out.

clkmgr.FATAL_ERR_CODE @ 0x54

Error code

Reset default = 0x0, mask 0x7

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													SHADOW_STORAGE_ERR	IDLE_CNT	REG_INTG

Bits

Type

Reset

Name

Description

0x0

REG_INTG

0x0

IDLE_CNT

One of the idle counts encountered a duplicate error.

0x0

SHADOW_STORAGE_ERR

One of the shadow registers encountered a storage error.

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers