Referring to the Comportable guideline for peripheral device functionality, the module rv_timer has the following hardware interfaces defined
- Primary Clock:
clk_i
- Other Clocks: none
- Bus Device Interfaces (TL-UL):
tl
- Bus Host Interfaces (TL-UL): none
- Peripheral Pins for Chip IO: none
| Port Name | Package::Struct | Type | Act | Width | Description |
|---|
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Interrupt Name | Type | Description |
|---|
| timer_expired_hart0_timer0 | Event | raised if hart0’s timer0 expired (mtimecmp >= mtime) |
| Alert Name | Description |
|---|
| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the RV_TIMER unit. |
| Countermeasure ID | Description |
|---|
| RV_TIMER.BUS.INTEGRITY | End-to-end bus integrity scheme. |
Alert Test Register
- Offset:
0x0
- Reset default:
0x0
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. |
Control register
- Offset:
0x4
- Reset default:
0x0
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw | 0x0 | active_0 | If 1, timer operates |
Interrupt Enable
- Offset:
0x100
- Reset default:
0x0
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw | 0x0 | IE_0 | Interrupt Enable for timer |
Interrupt Status
- Offset:
0x104
- Reset default:
0x0
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw1c | 0x0 | IS_0 | Interrupt status for timer |
Interrupt test register
- Offset:
0x108
- Reset default:
0x0
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | wo | x | T_0 | Interrupt test for timer |
Configuration for Hart 0
- Offset:
0x10c
- Reset default:
0x10000
- Reset mask:
0xff0fff
| Bits | Type | Reset | Name | Description |
|---|
| 31:24 | | | | Reserved |
| 23:16 | rw | 0x1 | step | Incremental value for each tick |
| 15:12 | | | | Reserved |
| 11:0 | rw | 0x0 | prescale | Prescaler to generate tick |
Timer value Lower
- Offset:
0x110
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0x0 | v | Timer value [31:0] |
Timer value Upper
- Offset:
0x114
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0x0 | v | Timer value [63:32] |
Timer value Lower
- Offset:
0x118
- Reset default:
0xffffffff
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0xffffffff | v | Timer compare value [31:0] |
Timer value Upper
- Offset:
0x11c
- Reset default:
0xffffffff
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0xffffffff | v | Timer compare value [63:32] |