Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module rv_timer has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
timer_expired_hart0_timer0Event

raised if hart0's timer0 expired (mtimecmp >= mtime)

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the RV_TIMER unit.

Security Countermeasures:

Countermeasure IDDescription
RV_TIMER.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
rv_timer.ALERT_TEST 0x0 4

Alert Test Register

rv_timer.CTRL 0x4 4

Control register

rv_timer.INTR_ENABLE0 0x100 4

Interrupt Enable

rv_timer.INTR_STATE0 0x104 4

Interrupt Status

rv_timer.INTR_TEST0 0x108 4

Interrupt test register

rv_timer.CFG0 0x10c 4

Configuration for Hart 0

rv_timer.TIMER_V_LOWER0 0x110 4

Timer value Lower

rv_timer.TIMER_V_UPPER0 0x114 4

Timer value Upper

rv_timer.COMPARE_LOWER0_0 0x118 4

Timer value Lower

rv_timer.COMPARE_UPPER0_0 0x11c 4

Timer value Upper

rv_timer.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


rv_timer.CTRL @ 0x4

Control register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  active_0
BitsTypeResetNameDescription
0rw0x0active_0

If 1, timer operates


rv_timer.INTR_ENABLE0 @ 0x100

Interrupt Enable

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  IE_0
BitsTypeResetNameDescription
0rw0x0IE_0

Interrupt Enable for timer


rv_timer.INTR_STATE0 @ 0x104

Interrupt Status

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  IS_0
BitsTypeResetNameDescription
0rw1c0x0IS_0

Interrupt status for timer


rv_timer.INTR_TEST0 @ 0x108

Interrupt test register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  T_0
BitsTypeResetNameDescription
0woxT_0

Interrupt test for timer


rv_timer.CFG0 @ 0x10c

Configuration for Hart 0

Reset default = 0x10000, mask 0xff0fff
31302928272625242322212019181716
  step
1514131211109876543210
  prescale
BitsTypeResetNameDescription
11:0rw0x0prescale

Prescaler to generate tick

15:12Reserved
23:16rw0x1step

Incremental value for each tick


rv_timer.TIMER_V_LOWER0 @ 0x110

Timer value Lower

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
v...
1514131211109876543210
...v
BitsTypeResetNameDescription
31:0rw0x0v

Timer value [31:0]


rv_timer.TIMER_V_UPPER0 @ 0x114

Timer value Upper

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
v...
1514131211109876543210
...v
BitsTypeResetNameDescription
31:0rw0x0v

Timer value [63:32]


rv_timer.COMPARE_LOWER0_0 @ 0x118

Timer value Lower

Reset default = 0xffffffff, mask 0xffffffff
31302928272625242322212019181716
v...
1514131211109876543210
...v
BitsTypeResetNameDescription
31:0rw0xffffffffv

Timer compare value [31:0]


rv_timer.COMPARE_UPPER0_0 @ 0x11c

Timer value Upper

Reset default = 0xffffffff, mask 0xffffffff
31302928272625242322212019181716
v...
1514131211109876543210
...v
BitsTypeResetNameDescription
31:0rw0xffffffffv

Timer compare value [63:32]