Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module rv_timer has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
timer_expired_hart0_timer0Eventraised if hart0’s timer0 expired (mtimecmp >= mtime)

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected inside the RV_TIMER unit.

Security Countermeasures

Countermeasure IDDescription
RV_TIMER.BUS.INTEGRITYEnd-to-end bus integrity scheme.

Registers

Summary

NameOffsetLengthDescription
rv_timer.ALERT_TEST0x04Alert Test Register
rv_timer.CTRL0x44Control register
rv_timer.INTR_ENABLE00x1004Interrupt Enable
rv_timer.INTR_STATE00x1044Interrupt Status
rv_timer.INTR_TEST00x1084Interrupt test register
rv_timer.CFG00x10c4Configuration for Hart 0
rv_timer.TIMER_V_LOWER00x1104Timer value Lower
rv_timer.TIMER_V_UPPER00x1144Timer value Upper
rv_timer.COMPARE_LOWER0_00x1184Timer value Lower
rv_timer.COMPARE_UPPER0_00x11c4Timer value Upper

ALERT_TEST

Alert Test Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

CTRL

Control register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0active_0If 1, timer operates

INTR_ENABLE0

Interrupt Enable

  • Offset: 0x100
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0IE_0Interrupt Enable for timer

INTR_STATE0

Interrupt Status

  • Offset: 0x104
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0IS_0Interrupt status for timer

INTR_TEST0

Interrupt test register

  • Offset: 0x108
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0woxT_0Interrupt test for timer

CFG0

Configuration for Hart 0

  • Offset: 0x10c
  • Reset default: 0x10000
  • Reset mask: 0xff0fff

Fields

BitsTypeResetNameDescription
31:24Reserved
23:16rw0x1stepIncremental value for each tick
15:12Reserved
11:0rw0x0prescalePrescaler to generate tick

TIMER_V_LOWER0

Timer value Lower

  • Offset: 0x110
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0vTimer value [31:0]

TIMER_V_UPPER0

Timer value Upper

  • Offset: 0x114
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0vTimer value [63:32]

COMPARE_LOWER0_0

Timer value Lower

  • Offset: 0x118
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0xffffffffvTimer compare value [31:0]

COMPARE_UPPER0_0

Timer value Upper

  • Offset: 0x11c
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0xffffffffvTimer compare value [63:32]