Hardware Interfaces and Registers
Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module kmac
has the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: clk_edn_i
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO: none
Inter-Module Signals: Reference
Port Name | Package::Struct | Type | Act | Width | Description |
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keymgr_key | keymgr_pkg::hw_key_req | uni | rcv | 1 | |
app | kmac_pkg::app | req_rsp | rsp | 3 | |
entropy | edn_pkg::edn | req_rsp | req | 1 | |
idle | prim_mubi_pkg::mubi4 | uni | req | 1 | |
en_masking | logic | uni | req | 1 | |
lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts:
Interrupt Name | Type | Description |
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kmac_done | Event | KMAC/SHA3 absorbing has been completed |
fifo_empty | Event | Message FIFO empty condition |
kmac_err | Event | KMAC/SHA3 error occurred. ERR_CODE register shows the details |
Security Alerts:
Alert Name | Description |
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recov_operation_err | Alert for KMAC operation error. It occurs when the shadow registers have update errors. |
fatal_fault_err | This fatal alert is triggered when a fatal error is detected inside the KMAC unit. Examples for such faults include: i) TL-UL bus integrity fault. ii) Storage errors in the shadow registers. iii) Errors in the message, round, or key counter. iv) Any internal FSM entering an invalid state. v) An error in the redundant lfsr. The KMAC unit cannot recover from such an error and needs to be reset. |
Security Countermeasures:
Countermeasure ID | Description |
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KMAC.BUS.INTEGRITY | End-to-end bus integrity scheme. |
KMAC.LC_ESCALATE_EN.INTERSIG.MUBI | The global escalation input signal from the life cycle is multibit encoded |
KMAC.SW_KEY.KEY.MASKING | Data storage and secret key are two share to guard against 1st order attack. |
KMAC.KEY.SIDELOAD | Key from KeyMgr is sideloaded. |
KMAC.CFG_SHADOWED.CONFIG.SHADOW | Shadowed CFG register. |
KMAC.FSM.SPARSE | FSMs in KMAC are sparsely encoded. |
KMAC.CTR.REDUN | Round counter, key index counter, sentmsg counter and hash counter use prim_count for redundancy |
KMAC.PACKER.CTR.REDUN | Packer Position counter uses prim_count for redundancy |
KMAC.CFG_SHADOWED.CONFIG.REGWEN | CFG_SHADOWED is protected by REGWEN |
KMAC.FSM.GLOBAL_ESC | Escalation moves all sparse FSMs into an invalid state. |
KMAC.FSM.LOCAL_ESC | Local fatal faults move all sparse FSMs into an invalid state. |
KMAC.LOGIC.INTEGRITY | The reset net for the internal state register and critical nets around the output register are buried. |
KMAC.ABSORBED.CTRL.MUBI |
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KMAC.SW_CMD.CTRL.SPARSE |
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Registers
Summary | |||
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Name | Offset | Length | Description |
kmac.INTR_STATE | 0x0 | 4 | Interrupt State Register |
kmac.INTR_ENABLE | 0x4 | 4 | Interrupt Enable Register |
kmac.INTR_TEST | 0x8 | 4 | Interrupt Test Register |
kmac.ALERT_TEST | 0xc | 4 | Alert Test Register |
kmac.CFG_REGWEN | 0x10 | 4 | Controls the configurability of |
kmac.CFG_SHADOWED | 0x14 | 4 | KMAC Configuration register. |
kmac.CMD | 0x18 | 4 | KMAC/ SHA3 command register. |
kmac.STATUS | 0x1c | 4 | KMAC/SHA3 Status register. |
kmac.ENTROPY_PERIOD | 0x20 | 4 | Entropy Timer Periods. |
kmac.ENTROPY_REFRESH_HASH_CNT | 0x24 | 4 | Entropy Refresh Counter |
kmac.ENTROPY_REFRESH_THRESHOLD_SHADOWED | 0x28 | 4 | Entropy Refresh Threshold |
kmac.ENTROPY_SEED_0 | 0x2c | 4 | Entropy Seed |
kmac.ENTROPY_SEED_1 | 0x30 | 4 | Entropy Seed |
kmac.ENTROPY_SEED_2 | 0x34 | 4 | Entropy Seed |
kmac.ENTROPY_SEED_3 | 0x38 | 4 | Entropy Seed |
kmac.ENTROPY_SEED_4 | 0x3c | 4 | Entropy Seed |
kmac.KEY_SHARE0_0 | 0x40 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_1 | 0x44 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_2 | 0x48 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_3 | 0x4c | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_4 | 0x50 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_5 | 0x54 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_6 | 0x58 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_7 | 0x5c | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_8 | 0x60 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_9 | 0x64 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_10 | 0x68 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_11 | 0x6c | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_12 | 0x70 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_13 | 0x74 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_14 | 0x78 | 4 | KMAC Secret Key |
kmac.KEY_SHARE0_15 | 0x7c | 4 | KMAC Secret Key |
kmac.KEY_SHARE1_0 | 0x80 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_1 | 0x84 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_2 | 0x88 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_3 | 0x8c | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_4 | 0x90 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_5 | 0x94 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_6 | 0x98 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_7 | 0x9c | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_8 | 0xa0 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_9 | 0xa4 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_10 | 0xa8 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_11 | 0xac | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_12 | 0xb0 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_13 | 0xb4 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_14 | 0xb8 | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_SHARE1_15 | 0xbc | 4 | KMAC Secret Key, 2nd share. |
kmac.KEY_LEN | 0xc0 | 4 | Secret Key length in bit. |
kmac.PREFIX_0 | 0xc4 | 4 | cSHAKE Prefix register. |
kmac.PREFIX_1 | 0xc8 | 4 | cSHAKE Prefix register. |
kmac.PREFIX_2 | 0xcc | 4 | cSHAKE Prefix register. |
kmac.PREFIX_3 | 0xd0 | 4 | cSHAKE Prefix register. |
kmac.PREFIX_4 | 0xd4 | 4 | cSHAKE Prefix register. |
kmac.PREFIX_5 | 0xd8 | 4 | cSHAKE Prefix register. |
kmac.PREFIX_6 | 0xdc | 4 | cSHAKE Prefix register. |
kmac.PREFIX_7 | 0xe0 | 4 | cSHAKE Prefix register. |
kmac.PREFIX_8 | 0xe4 | 4 | cSHAKE Prefix register. |
kmac.PREFIX_9 | 0xe8 | 4 | cSHAKE Prefix register. |
kmac.PREFIX_10 | 0xec | 4 | cSHAKE Prefix register. |
kmac.ERR_CODE | 0xf0 | 4 | KMAC/SHA3 Error Code |
kmac.STATE | 0x400 | 512 | Keccak State (1600 bit) memory. |
kmac.MSG_FIFO | 0x800 | 2048 | Message FIFO. |
kmac.INTR_STATE @ 0x0
Interrupt State Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x0 | kmac_done | KMAC/SHA3 absorbing has been completed | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | fifo_empty | Message FIFO empty condition | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw1c | 0x0 | kmac_err | KMAC/SHA3 error occurred. ERR_CODE register shows the details |
kmac.INTR_ENABLE @ 0x4
Interrupt Enable Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | kmac_done | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | fifo_empty | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | kmac_err | Enable interrupt when |
kmac.INTR_TEST @ 0x8
Interrupt Test Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | kmac_done | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | fifo_empty | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | wo | 0x0 | kmac_err | Write 1 to force |
kmac.ALERT_TEST @ 0xc
Alert Test Register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | recov_operation_err | Write 1 to trigger one alert event of this kind. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | fatal_fault_err | Write 1 to trigger one alert event of this kind. |
kmac.CFG_REGWEN @ 0x10
Controls the configurability of Reset default = 0x1, mask 0x1
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This register ensures the contents of | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x1 | en | Configuration enable. |
kmac.CFG_SHADOWED @ 0x14
KMAC Configuration register. Reset default = 0x0, mask 0x71b133f
Register enable = CFG_REGWEN |
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This register is updated when the hashing engine is in Idle. If the software updates the register while the engine computes, the updated value will be discarded. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | kmac_en | KMAC datapath enable. If this bit is 1, the incoming message is processed in KMAC with the secret key. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:1 | rw | 0x0 | kstrength | Hashing Strength 3 bit field to select the security strength of SHA3 hashing engine. If mode field is set to SHAKE or cSHAKE, only 128 and 256 strength can be selected. Other value will result error when hashing starts.
Other values are reserved. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:4 | rw | 0x0 | mode | Keccak hashing mode. This module supports SHA3 main hashing algorithm and the part of its derived functions, SHAKE and cSHAKE with limitations. This field is to select the mode.
Other values are reserved. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:6 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | msg_endianness | Message Endianness. If 1 then each individual multi-byte value, regardless of its
alignment, written to | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | state_endianness | State Endianness. If 1 then each individual word in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:10 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | rw | 0x0 | sideload | Sideloaded Key. If 1, KMAC uses KeyMgr sideloaded key for SW initiated KMAC operation. KMAC uses the sideloaded key regardless of this configuration when KeyMgr initiates the KMAC operation for Key Derivation Function (KDF). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:13 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
17:16 | rw | 0x0 | entropy_mode | Entropy Mode Using this field, software can configure mode of operation of the internal pseudo-random number generator (PRNG).
For the hardware to actually switch to an entropy mode other than the default idle_mode, software further needs to set the
Other values are reserved. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
18 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19 | rw | 0x0 | entropy_fast_process | Entropy Fast process mode. If 1, entropy logic uses garbage data while not processing the KMAC key block. It will re-use previous entropy value and will not expand the entropy when it is consumed. Only it refreshes the entropy while processing the secret key block. This process should not be used if SCA resistance is required because it may cause side channel leakage. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
20 | rw | 0x0 | msg_mask | Message Masking with PRNG. If 1, KMAC applies PRNG to the input messages to the Keccak module when KMAC mode is on. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:21 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
24 | rw | 0x0 | entropy_ready | Entropy Ready status. Software sets this field to allow the entropy generator in KMAC to fetch the entropy and run. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
25 | rw | 0x0 | err_processed | When error occurs and one of the state machine stays at Error handling state, SW may process the error based on ERR_CODE, then let FSM back to the reset state | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
26 | rw | 0x0 | en_unsupported_modestrength | Enable Unsupported Mode and Strength configs. SW may set this field for KMAC to move forward with unsupported Keccak Mode and Strength configurations, such as cSHAKE512. If not set, KMAC won't propagate the SW command (CmdStart) to the rest of the blocks (AppIntf, KMAC Core, SHA3). |
kmac.CMD @ 0x18
KMAC/ SHA3 command register. Reset default = 0x0, mask 0x33f
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This register is to control the KMAC to start accepting message, to process the message, and to manually run additional keccak rounds at the end. Only at certain stage, the CMD affects to the control logic. It follows the sequence of
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:0 | r0w1c | x | cmd | Issue a command to the KMAC/SHA3 IP. The command is sparse encoded. To prevent sw from writing multiple commands at once, the field is defined as enum.
Other values are reserved. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:6 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | r0w1c | x | entropy_req | SW triggered Entropy Request If writes 1 to this field | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | r0w1c | x | hash_cnt_clr | If writes 1, it clears the hash (KMAC) counter in the entropy module |
kmac.STATUS @ 0x1c
KMAC/SHA3 Status register. Reset default = 0x4001, mask 0x3df07
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x1 | sha3_idle | If 1, SHA3 hashing engine is in idle state. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | x | sha3_absorb | If 1, SHA3 is receiving message stream and processing it | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | ro | x | sha3_squeeze | If 1, SHA3 completes sponge absorbing stage. In this stage, SW can manually run the hashing engine. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:3 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12:8 | ro | x | fifo_depth | Count of occupied entries in the message FIFO. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14 | ro | 0x1 | fifo_empty | Message FIFO Empty indicator. The FIFO's In this case, See the "Message FIFO" section in the spec for the reason. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | ro | x | fifo_full | Message FIFO Full indicator | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | ro | 0x0 | ALERT_FATAL_FAULT | No fatal fault has occurred inside the KMAC unit (0). A fatal fault has occured and the KMAC unit needs to be reset (1), Examples for such faults include i) TL-UL bus integrity fault ii) storage errors in the shadow registers iii) errors in the message, round, or key counter iv) any internal FSM entering an invalid state v) an error in the redundant lfsr | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
17 | ro | 0x0 | ALERT_RECOV_CTRL_UPDATE_ERR | An update error has not occurred (0) or has occured (1) in the shadowed Control Register. KMAC operation needs to be restarted by re-writing the Control Register. |
kmac.ENTROPY_PERIOD @ 0x20
Entropy Timer Periods. Reset default = 0x0, mask 0xffff03ff
Register enable = CFG_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9:0 | rw | 0x0 | prescaler | EDN Wait timer prescaler. EDN Wait timer has 16 bit value. The timer value is increased when the timer pulse is generated. Timer pulse is raises when the number of the clock cycles hit this prescaler value. The exact period of the timer pulse is unknown as the KMAC input clock may contain jitters. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:10 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x0 | wait_timer | EDN request wait timer. The entropy module in KMAC waits up to this field in the timer pulse after it sends request to EDN module. If the timer expires, the entropy module moves to an error state and notifies to the system. If 0, the entropy module waits the EDN response always. If EDN does not respond in this configuration, the software shall reset the IP. |
kmac.ENTROPY_REFRESH_HASH_CNT @ 0x24
Entropy Refresh Counter Reset default = 0x0, mask 0x3ff
Register enable = CFG_REGWEN |
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KMAC entropy can be refreshed after the given threshold KMAC operations
run. If the KMAC hash counter If the threshold is 0, the refresh by the counter does not work. And the counter is only reset by the CMD.hash_cnt_clr CSR bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9:0 | ro | 0x0 | hash_cnt | Hash (KMAC) counter |
kmac.ENTROPY_REFRESH_THRESHOLD_SHADOWED @ 0x28
Entropy Refresh Threshold Reset default = 0x0, mask 0x3ff
Register enable = CFG_REGWEN |
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC entropy can be refreshed after the given threshold KMAC operations
run. If the KMAC hash counter If the threshold is 0, the refresh by the counter does not work. And the counter is only reset by the CMD.hash_cnt_clr CSR bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9:0 | rw | 0x0 | threshold | Hash Threshold |
kmac.ENTROPY_SEED_0 @ 0x2c
Entropy Seed Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Entropy seed registers for the integrated entropy generator. If After writing all | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | seed_0 | 32-bit chunk of the entropy generator seed |
kmac.ENTROPY_SEED_1 @ 0x30
Entropy Seed Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Entropy seed registers for the integrated entropy generator. If After writing all | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | seed_1 | For KMAC1 |
kmac.ENTROPY_SEED_2 @ 0x34
Entropy Seed Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Entropy seed registers for the integrated entropy generator. If After writing all | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | seed_2 | For KMAC2 |
kmac.ENTROPY_SEED_3 @ 0x38
Entropy Seed Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Entropy seed registers for the integrated entropy generator. If After writing all | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | seed_3 | For KMAC3 |
kmac.ENTROPY_SEED_4 @ 0x3c
Entropy Seed Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Entropy seed registers for the integrated entropy generator. If After writing all | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | seed_4 | For KMAC4 |
kmac.KEY_SHARE0_0 @ 0x40
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_0 | 32-bit chunk of up-to 512-bit Secret Key |
kmac.KEY_SHARE0_1 @ 0x44
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_1 | For KMAC1 |
kmac.KEY_SHARE0_2 @ 0x48
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_2 | For KMAC2 |
kmac.KEY_SHARE0_3 @ 0x4c
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_3 | For KMAC3 |
kmac.KEY_SHARE0_4 @ 0x50
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_4 | For KMAC4 |
kmac.KEY_SHARE0_5 @ 0x54
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_5 | For KMAC5 |
kmac.KEY_SHARE0_6 @ 0x58
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_6 | For KMAC6 |
kmac.KEY_SHARE0_7 @ 0x5c
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_7 | For KMAC7 |
kmac.KEY_SHARE0_8 @ 0x60
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_8 | For KMAC8 |
kmac.KEY_SHARE0_9 @ 0x64
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_9 | For KMAC9 |
kmac.KEY_SHARE0_10 @ 0x68
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_10 | For KMAC10 |
kmac.KEY_SHARE0_11 @ 0x6c
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_11 | For KMAC11 |
kmac.KEY_SHARE0_12 @ 0x70
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_12 | For KMAC12 |
kmac.KEY_SHARE0_13 @ 0x74
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_13 | For KMAC13 |
kmac.KEY_SHARE0_14 @ 0x78
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_14 | For KMAC14 |
kmac.KEY_SHARE0_15 @ 0x7c
KMAC Secret Key Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_15 | For KMAC15 |
kmac.KEY_SHARE1_0 @ 0x80
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_0 | 32-bit chunk of up-to 512-bit Secret Key |
kmac.KEY_SHARE1_1 @ 0x84
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_1 | For KMAC1 |
kmac.KEY_SHARE1_2 @ 0x88
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_2 | For KMAC2 |
kmac.KEY_SHARE1_3 @ 0x8c
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_3 | For KMAC3 |
kmac.KEY_SHARE1_4 @ 0x90
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_4 | For KMAC4 |
kmac.KEY_SHARE1_5 @ 0x94
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_5 | For KMAC5 |
kmac.KEY_SHARE1_6 @ 0x98
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_6 | For KMAC6 |
kmac.KEY_SHARE1_7 @ 0x9c
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_7 | For KMAC7 |
kmac.KEY_SHARE1_8 @ 0xa0
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_8 | For KMAC8 |
kmac.KEY_SHARE1_9 @ 0xa4
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_9 | For KMAC9 |
kmac.KEY_SHARE1_10 @ 0xa8
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_10 | For KMAC10 |
kmac.KEY_SHARE1_11 @ 0xac
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_11 | For KMAC11 |
kmac.KEY_SHARE1_12 @ 0xb0
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_12 | For KMAC12 |
kmac.KEY_SHARE1_13 @ 0xb4
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_13 | For KMAC13 |
kmac.KEY_SHARE1_14 @ 0xb8
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_14 | For KMAC14 |
kmac.KEY_SHARE1_15 @ 0xbc
KMAC Secret Key, 2nd share. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
KMAC secret key can be up to 512 bit. Order of the secret key is: key[512:0] = {KEY15, KEY14, ... , KEY0}; The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. Current KMAC supports up to 512 bit secret key. It is the sw responsibility to keep upper bits of the secret key to 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | key_15 | For KMAC15 |
kmac.KEY_LEN @ 0xc0
Secret Key length in bit. Reset default = 0x0, mask 0x7
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
This value is used to make encoded secret key in KMAC. KMAC supports certain lengths of the secret key. Currently it supports 128b, 192b, 256b, 384b, and 512b secret keys. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2:0 | wo | 0x0 | len | Key length choice
Other values are reserved. |
kmac.PREFIX_0 @ 0xc4
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_0 | 32-bit chunk of Encoded NS Prefix |
kmac.PREFIX_1 @ 0xc8
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_1 | For KMAC1 |
kmac.PREFIX_2 @ 0xcc
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_2 | For KMAC2 |
kmac.PREFIX_3 @ 0xd0
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_3 | For KMAC3 |
kmac.PREFIX_4 @ 0xd4
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_4 | For KMAC4 |
kmac.PREFIX_5 @ 0xd8
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
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Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_5 | For KMAC5 |
kmac.PREFIX_6 @ 0xdc
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
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Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_6 | For KMAC6 |
kmac.PREFIX_7 @ 0xe0
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_7 | For KMAC7 |
kmac.PREFIX_8 @ 0xe4
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_8 | For KMAC8 |
kmac.PREFIX_9 @ 0xe8
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_9 | For KMAC9 |
kmac.PREFIX_10 @ 0xec
cSHAKE Prefix register. Reset default = 0x0, mask 0xffffffff
Register enable = CFG_REGWEN |
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Prefix including Function Name N and Customization String S.
The SHA3 assumes this register value is encoded as:
It is SW responsibility to fill the register with encoded value that is described at Section 2.3.2 String Encoding in NIST SP 800-185 specification. Order of Prefix is: prefix[end:0] := {PREFIX(N-1), ..., PREFIX(1), PREFIX(0) } The registers are allowed to be updated when the engine is in Idle state. If the engine computes the hash, it discards any attempts to update the secret keys and report an error. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | prefix_10 | For KMAC10 |
kmac.ERR_CODE @ 0xf0
KMAC/SHA3 Error Code Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | 0x0 | err_code | If error interrupt occurs, this register has information of error cause. Please take a look at `hw/ip/kmac/rtl/kmac_pkg.sv:err_code_e enum type. |
kmac.STATE @ + 0x400
128 item ro window
Byte writes are not supported
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Keccak State (1600 bit) memory. The software can get the processed digest by reading this memory region. Unlike MSG_FIFO, STATE memory space sees the addr[9:0]. If Masking feature is enabled, the software reads two shares from this memory space. 0x400 - 0x4C7: State share 0x500 - 0x5C7: Mask share of the state, 0 if EnMasking = 0 |
kmac.MSG_FIFO @ + 0x800
512 item wo window
Byte writes are supported
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Message FIFO. Any write to this window will be appended to the FIFO. Only lower
2 bits |