Hardware Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module pwrmgr has the following hardware interfaces defined
- Primary Clock:
clk_i - Other Clocks:
clk_slow_i,clk_lc_i,clk_esc_i - Bus Device Interfaces (TL-UL):
tl - Bus Host Interfaces (TL-UL): none
- Peripheral Pins for Chip IO: none
Inter-Module Signals
| Port Name | Package::Struct | Type | Act | Width | Description |
|---|---|---|---|---|---|
| pwr_ast | pwrmgr_pkg::pwr_ast | req_rsp | req | 1 | |
| pwr_rst | pwrmgr_pkg::pwr_rst | req_rsp | req | 1 | |
| pwr_clk | pwrmgr_pkg::pwr_clk | req_rsp | req | 1 | |
| pwr_otp | pwrmgr_pkg::pwr_otp | req_rsp | req | 1 | |
| pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | req | 1 | |
| pwr_flash | pwrmgr_pkg::pwr_flash | uni | rcv | 1 | |
| esc_rst_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | |
| esc_rst_rx | prim_esc_pkg::esc_rx | uni | req | 1 | |
| pwr_cpu | pwrmgr_pkg::pwr_cpu | uni | rcv | 1 | |
| wakeups | logic | uni | rcv | 6 | |
| rstreqs | logic | uni | rcv | 2 | |
| ndmreset_req | logic | uni | rcv | 1 | |
| strap | logic | uni | req | 1 | |
| low_power | logic | uni | req | 1 | |
| rom_ctrl | rom_ctrl_pkg::pwrmgr_data | uni | rcv | 1 | |
| fetch_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
| lc_dft_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| sw_rst_req | prim_mubi_pkg::mubi4 | uni | rcv | 1 | |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts
| Interrupt Name | Type | Description |
|---|---|---|
| wakeup | Event | Wake from low power state. See wake info for more details |
Security Alerts
| Alert Name | Description |
|---|---|
| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
Security Countermeasures
| Countermeasure ID | Description |
|---|---|
| PWRMGR.BUS.INTEGRITY | End-to-end bus integrity scheme. |
| PWRMGR.LC_CTRL.INTERSIG.MUBI | life cycle control / debug signals are multibit. |
| PWRMGR.ROM_CTRL.INTERSIG.MUBI | rom control done/good signals are multibit. |
| PWRMGR.RSTMGR.INTERSIG.MUBI | reset manager software request is multibit. |
| PWRMGR.ESC_RX.CLK.BKGN_CHK | Escalation receiver has a background timeout check |
| PWRMGR.ESC_RX.CLK.LOCAL_ESC | Escalation receiver clock timeout has a local reset escalation |
| PWRMGR.FSM.SPARSE | Sparse encoding for slow and fast state machines. |
| PWRMGR.FSM.TERMINAL | When FSMs reach a bad state, go into a terminate state that does not recover without user or external host intervention. |
| PWRMGR.CTRL_FLOW.GLOBAL_ESC | When global escalation is received, proceed directly to reset. |
| PWRMGR.MAIN_PD.RST.LOCAL_ESC | When main power domain reset glitches, proceed directly to reset. |
| PWRMGR.CTRL.CONFIG.REGWEN | Main control protected by regwen. |
| PWRMGR.WAKEUP.CONFIG.REGWEN | Wakeup configuration protected by regwen. |
| PWRMGR.RESET.CONFIG.REGWEN | Reset configuration protected by regwen. |
Registers
Summary
| Name | Offset | Length | Description |
|---|---|---|---|
pwrmgr.INTR_STATE | 0x0 | 4 | Interrupt State Register |
pwrmgr.INTR_ENABLE | 0x4 | 4 | Interrupt Enable Register |
pwrmgr.INTR_TEST | 0x8 | 4 | Interrupt Test Register |
pwrmgr.ALERT_TEST | 0xc | 4 | Alert Test Register |
pwrmgr.CTRL_CFG_REGWEN | 0x10 | 4 | Controls the configurability of the !!CONTROL register. |
pwrmgr.CONTROL | 0x14 | 4 | Control register |
pwrmgr.CFG_CDC_SYNC | 0x18 | 4 | The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the |
pwrmgr.WAKEUP_EN_REGWEN | 0x1c | 4 | Configuration enable for wakeup_en register |
pwrmgr.WAKEUP_EN | 0x20 | 4 | Bit mask for enabled wakeups |
pwrmgr.WAKE_STATUS | 0x24 | 4 | A read only register of all current wake requests post enable mask |
pwrmgr.RESET_EN_REGWEN | 0x28 | 4 | Configuration enable for reset_en register |
pwrmgr.RESET_EN | 0x2c | 4 | Bit mask for enabled reset requests |
pwrmgr.RESET_STATUS | 0x30 | 4 | A read only register of all current reset requests post enable mask |
pwrmgr.ESCALATE_RESET_STATUS | 0x34 | 4 | A read only register of escalation reset request |
pwrmgr.WAKE_INFO_CAPTURE_DIS | 0x38 | 4 | Indicates which functions caused the chip to wakeup |
pwrmgr.WAKE_INFO | 0x3c | 4 | Indicates which functions caused the chip to wakeup. |
pwrmgr.FAULT_STATUS | 0x40 | 4 | A read only register that shows the existing faults |
INTR_STATE
Interrupt State Register
- Offset:
0x0 - Reset default:
0x0 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | rw1c | 0x0 | wakeup | Wake from low power state. See wake info for more details |
INTR_ENABLE
Interrupt Enable Register
- Offset:
0x4 - Reset default:
0x0 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | rw | 0x0 | wakeup | Enable interrupt when INTR_STATE.wakeup is set. |
INTR_TEST
Interrupt Test Register
- Offset:
0x8 - Reset default:
0x0 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | wo | 0x0 | wakeup | Write 1 to force INTR_STATE.wakeup to 1. |
ALERT_TEST
Alert Test Register
- Offset:
0xc - Reset default:
0x0 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. |
CTRL_CFG_REGWEN
Controls the configurability of the CONTROL register.
This register ensures the contents do not change once a low power hint and WFI has occurred.
It unlocks whenever a low power transition has completed (transition back to the ACTIVE state) for any reason.
- Offset:
0x10 - Reset default:
0x1 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | ro | 0x1 | EN | Configuration enable. This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. When the device transitions back from low power state to active state, this bit is set back to 1 to allow software configuration of CONTROL |
CONTROL
Control register
- Offset:
0x14 - Reset default:
0x180 - Reset mask:
0x1f1 - Register enable:
CTRL_CFG_REGWEN
Fields
| Bits | Type | Reset | Name |
|---|---|---|---|
| 31:9 | Reserved | ||
| 8 | rw | 0x1 | MAIN_PD_N |
| 7 | rw | 0x1 | USB_CLK_EN_ACTIVE |
| 6 | rw | 0x0 | USB_CLK_EN_LP |
| 5 | rw | 0x0 | IO_CLK_EN |
| 4 | rw | 0x0 | CORE_CLK_EN |
| 3:1 | Reserved | ||
| 0 | rw | 0x0 | LOW_POWER_HINT |
CONTROL . MAIN_PD_N
Active low, main power domain power down
| Value | Name | Description |
|---|---|---|
| 0x0 | Power down | Main power domain is powered down during low power state. |
| 0x1 | Power up | Main power domain is kept powered during low power state |
CONTROL . USB_CLK_EN_ACTIVE
USB clock enable during active power state
| Value | Name | Description |
|---|---|---|
| 0x0 | Disabled | USB clock disabled during active power state |
| 0x1 | Enabled | USB clock enabled during active power state |
CONTROL . USB_CLK_EN_LP
USB clock enable during low power state
| Value | Name | Description |
|---|---|---|
| 0x0 | Disabled | USB clock disabled during low power state |
| 0x1 | Enabled | USB clock enabled during low power state. However, if !!CONTROL.MAIN_PD_N is 0, USB clock is disabled during low power state. |
CONTROL . IO_CLK_EN
IO clock enable during low power state
| Value | Name | Description |
|---|---|---|
| 0x0 | Disabled | IO clock disabled during low power state |
| 0x1 | Enabled | IO clock enabled during low power state |
CONTROL . CORE_CLK_EN
core clock enable during low power state
| Value | Name | Description |
|---|---|---|
| 0x0 | Disabled | Core clock disabled during low power state |
| 0x1 | Enabled | Core clock enabled during low power state |
CONTROL . LOW_POWER_HINT
The low power hint to power manager. The hint is an indication for how the manager should treat the next WFI. Once the power manager begins a low power transition, or if a valid reset request is registered, this bit is automatically cleared by HW.
| Value | Name | Description |
|---|---|---|
| 0x0 | None | No low power intent |
| 0x1 | Low Power | Next WFI should trigger low power entry |
CFG_CDC_SYNC
The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the fast clock domain but used in the slow clock domain.
The configuration are not propagated across the clock boundary until this register is triggered and read. See fields below for more details
- Offset:
0x18 - Reset default:
0x0 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name |
|---|---|---|---|
| 31:1 | Reserved | ||
| 0 | rw | 0x0 | SYNC |
CFG_CDC_SYNC . SYNC
Configuration sync. When this bit is written to 1, a sync pulse is generated. When the sync completes, this bit then self clears.
Software should write this bit to 1, wait for it to clear, before assuming the slow clock domain has accepted the programmed values.
WAKEUP_EN_REGWEN
Configuration enable for wakeup_en register
- Offset:
0x1c - Reset default:
0x1 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | rw0c | 0x1 | EN | When 1, WAKEUP_EN register can be configured. When 0, WAKEUP_EN register cannot be configured. |
WAKEUP_EN
Bit mask for enabled wakeups
- Offset:
0x20 - Reset default:
0x0 - Reset mask:
0x3f - Register enable:
WAKEUP_EN_REGWEN
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:6 | Reserved | |||
| 5 | rw | 0x0 | EN_5 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. |
| 4 | rw | 0x0 | EN_4 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. |
| 3 | rw | 0x0 | EN_3 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. |
| 2 | rw | 0x0 | EN_2 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. |
| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. |
| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power. |
WAKE_STATUS
A read only register of all current wake requests post enable mask
- Offset:
0x24 - Reset default:
0x0 - Reset mask:
0x3f
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:6 | Reserved | |||
| 5 | ro | 0x0 | VAL_5 | Current value of wake requests |
| 4 | ro | 0x0 | VAL_4 | Current value of wake requests |
| 3 | ro | 0x0 | VAL_3 | Current value of wake requests |
| 2 | ro | 0x0 | VAL_2 | Current value of wake requests |
| 1 | ro | 0x0 | VAL_1 | Current value of wake requests |
| 0 | ro | 0x0 | VAL_0 | Current value of wake requests |
RESET_EN_REGWEN
Configuration enable for reset_en register
- Offset:
0x28 - Reset default:
0x1 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | rw0c | 0x1 | EN | When 1, RESET_EN register can be configured. When 0, RESET_EN register cannot be configured. |
RESET_EN
Bit mask for enabled reset requests
- Offset:
0x2c - Reset default:
0x0 - Reset mask:
0x3 - Register enable:
RESET_EN_REGWEN
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:2 | Reserved | |||
| 1 | rw | 0x0 | EN_1 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. |
| 0 | rw | 0x0 | EN_0 | Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device. |
RESET_STATUS
A read only register of all current reset requests post enable mask
- Offset:
0x30 - Reset default:
0x0 - Reset mask:
0x3
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:2 | Reserved | |||
| 1 | ro | 0x0 | VAL_1 | Current value of reset request |
| 0 | ro | 0x0 | VAL_0 | Current value of reset request |
ESCALATE_RESET_STATUS
A read only register of escalation reset request
- Offset:
0x34 - Reset default:
0x0 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | ro | 0x0 | VAL | When 1, an escalation reset has been seen. When 0, there is no escalation reset. |
WAKE_INFO_CAPTURE_DIS
Indicates which functions caused the chip to wakeup
- Offset:
0x38 - Reset default:
0x0 - Reset mask:
0x1
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:1 | Reserved | |||
| 0 | rw | 0x0 | VAL | When written to 1, this actively suppresses the wakeup info capture. When written to 0, wakeup info capture timing is controlled by HW. |
WAKE_INFO
Indicates which functions caused the chip to wakeup. The wake info recording begins whenever the device begins a valid low power entry.
This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. This means it is possible to capture multiple wakeup reasons.
- Offset:
0x3c - Reset default:
0x0 - Reset mask:
0xff
Fields
| Bits | Type | Reset | Name |
|---|---|---|---|
| 31:8 | Reserved | ||
| 7 | rw1c | 0x0 | ABORT |
| 6 | rw1c | 0x0 | FALL_THROUGH |
| 5:0 | rw1c | 0x0 | REASONS |
WAKE_INFO . ABORT
The abort wakeup reason indicates that despite setting a WFI and providing a low power hint, an active flash / lifecycle / otp transaction was ongoing when the power controller attempted to initiate low power entry.
The power manager detects this condition, halts low power entry and reports as a wakeup reason
WAKE_INFO . FALL_THROUGH
The fall through wakeup reason indicates that despite setting a WFI and providing a low power hint, an interrupt arrived at just the right time to break the executing core out of WFI.
The power manager detects this condition, halts low power entry and reports as a wakeup reason
WAKE_INFO . REASONS
Various peripheral wake reasons
FAULT_STATUS
A read only register that shows the existing faults
- Offset:
0x40 - Reset default:
0x0 - Reset mask:
0x7
Fields
| Bits | Type | Reset | Name | Description |
|---|---|---|---|---|
| 31:3 | Reserved | |||
| 2 | ro | 0x0 | MAIN_PD_GLITCH | When 1, unexpected power glitch was observed on main PD. |
| 1 | ro | 0x0 | ESC_TIMEOUT | When 1, an escalation clock / reset timeout has occurred. |
| 0 | ro | 0x0 | REG_INTG_ERR | When 1, an integrity error has occurred. |