Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pwrmgr has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_slow_i, clk_lc_i, clk_esc_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
pwr_ast pwrmgr_pkg::pwr_ast req_rsp req 1
pwr_rst pwrmgr_pkg::pwr_rst req_rsp req 1
pwr_clk pwrmgr_pkg::pwr_clk req_rsp req 1
pwr_otp pwrmgr_pkg::pwr_otp req_rsp req 1
pwr_lc pwrmgr_pkg::pwr_lc req_rsp req 1
pwr_flash pwrmgr_pkg::pwr_flash uni rcv 1
esc_rst_tx prim_esc_pkg::esc_tx uni rcv 1
esc_rst_rx prim_esc_pkg::esc_rx uni req 1
pwr_cpu pwrmgr_pkg::pwr_cpu uni rcv 1
wakeups logic uni rcv 6
rstreqs logic uni rcv 2
ndmreset_req logic uni rcv 1
strap logic uni req 1
low_power logic uni req 1
rom_ctrl rom_ctrl_pkg::pwrmgr_data uni rcv 1
fetch_en lc_ctrl_pkg::lc_tx uni req 1
lc_dft_en lc_ctrl_pkg::lc_tx uni rcv 1
lc_hw_debug_en lc_ctrl_pkg::lc_tx uni rcv 1
sw_rst_req prim_mubi_pkg::mubi4 uni rcv 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
wakeupEvent

Wake from low power state. See wake info for more details

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
PWRMGR.BUS.INTEGRITY

End-to-end bus integrity scheme.

PWRMGR.LC_CTRL.INTERSIG.MUBI

life cycle control / debug signals are multibit.

PWRMGR.ROM_CTRL.INTERSIG.MUBI

rom control done/good signals are multibit.

PWRMGR.RSTMGR.INTERSIG.MUBI

reset manager software request is multibit.

PWRMGR.ESC_RX.CLK.BKGN_CHK

Escalation receiver has a background timeout check

PWRMGR.ESC_RX.CLK.LOCAL_ESC

Escalation receiver clock timeout has a local reset escalation

PWRMGR.FSM.SPARSE

Sparse encoding for slow and fast state machines.

PWRMGR.FSM.TERMINAL

When FSMs reach a bad state, go into a terminate state that does not recover without user or external host intervention.

PWRMGR.CTRL_FLOW.GLOBAL_ESC

When global escalation is received, proceed directly to reset.

PWRMGR.MAIN_PD.RST.LOCAL_ESC

When main power domain reset glitches, proceed directly to reset.

PWRMGR.CTRL.CONFIG.REGWEN

Main control protected by regwen.

PWRMGR.WAKEUP.CONFIG.REGWEN

Wakeup configuration protected by regwen.

PWRMGR.RESET.CONFIG.REGWEN

Reset configuration protected by regwen.

Registers

Summary
Name Offset Length Description
pwrmgr.INTR_STATE 0x0 4

Interrupt State Register
pwrmgr.INTR_ENABLE 0x4 4

Interrupt Enable Register
pwrmgr.INTR_TEST 0x8 4

Interrupt Test Register
pwrmgr.ALERT_TEST 0xc 4

Alert Test Register
pwrmgr.CTRL_CFG_REGWEN 0x10 4

Controls the configurability of the CONTROL register.
pwrmgr.CONTROL 0x14 4

Control register
pwrmgr.CFG_CDC_SYNC 0x18 4

The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the fast clock domain but used in the slow clock domain.
pwrmgr.WAKEUP_EN_REGWEN 0x1c 4

Configuration enable for wakeup_en register
pwrmgr.WAKEUP_EN 0x20 4

Bit mask for enabled wakeups
pwrmgr.WAKE_STATUS 0x24 4

A read only register of all current wake requests post enable mask
pwrmgr.RESET_EN_REGWEN 0x28 4

Configuration enable for reset_en register
pwrmgr.RESET_EN 0x2c 4

Bit mask for enabled reset requests
pwrmgr.RESET_STATUS 0x30 4

A read only register of all current reset requests post enable mask
pwrmgr.ESCALATE_RESET_STATUS 0x34 4

A read only register of escalation reset request
pwrmgr.WAKE_INFO_CAPTURE_DIS 0x38 4

Indicates which functions caused the chip to wakeup
pwrmgr.WAKE_INFO 0x3c 4

Indicates which functions caused the chip to wakeup. The wake info recording begins whenever the device begins a valid low power entry.
pwrmgr.FAULT_STATUS 0x40 4

A read only register that shows the existing faults
pwrmgr.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1
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  wakeup
BitsTypeResetNameDescription
0rw1c0x0wakeup

Wake from low power state. See wake info for more details


pwrmgr.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1
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  wakeup
BitsTypeResetNameDescription
0rw0x0wakeup

Enable interrupt when INTR_STATE.wakeup is set.


pwrmgr.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1
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  wakeup
BitsTypeResetNameDescription
0wo0x0wakeup

Write 1 to force INTR_STATE.wakeup to 1.


pwrmgr.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


pwrmgr.CTRL_CFG_REGWEN @ 0x10

Controls the configurability of the CONTROL register.

Reset default = 0x1, mask 0x1

This register ensures the contents do not change once a low power hint and WFI has occurred.

It unlocks whenever a low power transition has completed (transition back to the ACTIVE state) for any reason.

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  EN
BitsTypeResetNameDescription
0ro0x1EN

Configuration enable.

This bit defaults to 1 and is set to 0 by hardware when low power entry is initiated. When the device transitions back from low power state to active state, this bit is set back to 1 to allow software configuration of CONTROL


pwrmgr.CONTROL @ 0x14

Control register

Reset default = 0x180, mask 0x1f1
Register enable = CTRL_CFG_REGWEN
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  MAIN_PD_N USB_CLK_EN_ACTIVE USB_CLK_EN_LP IO_CLK_EN CORE_CLK_EN   LOW_POWER_HINT
BitsTypeResetNameDescription
0rw0x0LOW_POWER_HINT

The low power hint to power manager. The hint is an indication for how the manager should treat the next WFI. Once the power manager begins a low power transition, or if a valid reset request is registered, this bit is automatically cleared by HW.

0x0None

No low power intent

0x1Low Power

Next WFI should trigger low power entry

3:1Reserved
4rw0x0CORE_CLK_EN

core clock enable during low power state

0x0Disabled

Core clock disabled during low power state

0x1Enabled

Core clock enabled during low power state

5rw0x0IO_CLK_EN

IO clock enable during low power state

0x0Disabled

IO clock disabled during low power state

0x1Enabled

IO clock enabled during low power state

6rw0x0USB_CLK_EN_LP

USB clock enable during low power state

0x0Disabled

USB clock disabled during low power state

0x1Enabled

USB clock enabled during low power state.

However, if CONTROL.MAIN_PD_N is 0, USB clock is disabled during low power state.

7rw0x1USB_CLK_EN_ACTIVE

USB clock enable during active power state

0x0Disabled

USB clock disabled during active power state

0x1Enabled

USB clock enabled during active power state

8rw0x1MAIN_PD_N

Active low, main power domain power down

0x0Power down

Main power domain is powered down during low power state.

0x1Power up

Main power domain is kept powered during low power state


pwrmgr.CFG_CDC_SYNC @ 0x18

The configuration registers CONTROL, WAKEUP_EN, RESET_EN are all written in the fast clock domain but used in the slow clock domain.

Reset default = 0x0, mask 0x1

The configuration are not propagated across the clock boundary until this register is triggered and read. See fields below for more details

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  SYNC
BitsTypeResetNameDescription
0rw0x0SYNC

Configuration sync. When this bit is written to 1, a sync pulse is generated. When the sync completes, this bit then self clears.

Software should write this bit to 1, wait for it to clear, before assuming the slow clock domain has accepted the programmed values.


pwrmgr.WAKEUP_EN_REGWEN @ 0x1c

Configuration enable for wakeup_en register

Reset default = 0x1, mask 0x1
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  EN
BitsTypeResetNameDescription
0rw0c0x1EN

When 1, WAKEUP_EN register can be configured. When 0, WAKEUP_EN register cannot be configured.


pwrmgr.WAKEUP_EN @ 0x20

Bit mask for enabled wakeups

Reset default = 0x0, mask 0x3f
Register enable = WAKEUP_EN_REGWEN
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  EN_5 EN_4 EN_3 EN_2 EN_1 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.

1rw0x0EN_1

Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.

2rw0x0EN_2

Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.

3rw0x0EN_3

Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.

4rw0x0EN_4

Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.

5rw0x0EN_5

Whenever a particular bit is set to 1, that wakeup is also enabled. Whenever a particular bit is set to 0, that wakeup cannot wake the device from low power.


pwrmgr.WAKE_STATUS @ 0x24

A read only register of all current wake requests post enable mask

Reset default = 0x0, mask 0x3f
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  VAL_5 VAL_4 VAL_3 VAL_2 VAL_1 VAL_0
BitsTypeResetNameDescription
0ro0x0VAL_0

Current value of wake requests

1ro0x0VAL_1

Current value of wake requests

2ro0x0VAL_2

Current value of wake requests

3ro0x0VAL_3

Current value of wake requests

4ro0x0VAL_4

Current value of wake requests

5ro0x0VAL_5

Current value of wake requests


pwrmgr.RESET_EN_REGWEN @ 0x28

Configuration enable for reset_en register

Reset default = 0x1, mask 0x1
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  EN
BitsTypeResetNameDescription
0rw0c0x1EN

When 1, RESET_EN register can be configured. When 0, RESET_EN register cannot be configured.


pwrmgr.RESET_EN @ 0x2c

Bit mask for enabled reset requests

Reset default = 0x0, mask 0x3
Register enable = RESET_EN_REGWEN
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  EN_1 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device.

1rw0x0EN_1

Whenever a particular bit is set to 1, that reset request is enabled. Whenever a particular bit is set to 0, that reset request cannot reset the device.


pwrmgr.RESET_STATUS @ 0x30

A read only register of all current reset requests post enable mask

Reset default = 0x0, mask 0x3
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  VAL_1 VAL_0
BitsTypeResetNameDescription
0ro0x0VAL_0

Current value of reset request

1ro0x0VAL_1

Current value of reset request


pwrmgr.ESCALATE_RESET_STATUS @ 0x34

A read only register of escalation reset request

Reset default = 0x0, mask 0x1
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  VAL
BitsTypeResetNameDescription
0ro0x0VAL

When 1, an escalation reset has been seen. When 0, there is no escalation reset.


pwrmgr.WAKE_INFO_CAPTURE_DIS @ 0x38

Indicates which functions caused the chip to wakeup

Reset default = 0x0, mask 0x1
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  VAL
BitsTypeResetNameDescription
0rw0x0VAL

When written to 1, this actively suppresses the wakeup info capture. When written to 0, wakeup info capture timing is controlled by HW.


pwrmgr.WAKE_INFO @ 0x3c

Indicates which functions caused the chip to wakeup. The wake info recording begins whenever the device begins a valid low power entry.

Reset default = 0x0, mask 0xff

This capture is continued until it is explicitly disabled through WAKE_INFO_CAPTURE_DIS. This means it is possible to capture multiple wakeup reasons.

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  ABORT FALL_THROUGH REASONS
BitsTypeResetNameDescription
5:0rw1c0x0REASONS

Various peripheral wake reasons

6rw1c0x0FALL_THROUGH

The fall through wakeup reason indicates that despite setting a WFI and providing a low power hint, an interrupt arrived at just the right time to break the executing core out of WFI.

The power manager detects this condition, halts low power entry and reports as a wakeup reason

7rw1c0x0ABORT

The abort wakeup reason indicates that despite setting a WFI and providing a low power hint, an active flash / lifecycle / otp transaction was ongoing when the power controller attempted to initiate low power entry.

The power manager detects this condition, halts low power entry and reports as a wakeup reason


pwrmgr.FAULT_STATUS @ 0x40

A read only register that shows the existing faults

Reset default = 0x0, mask 0x7
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  MAIN_PD_GLITCH ESC_TIMEOUT REG_INTG_ERR
BitsTypeResetNameDescription
0ro0x0REG_INTG_ERR

When 1, an integrity error has occurred.

1ro0x0ESC_TIMEOUT

When 1, an escalation clock / reset timeout has occurred.

2ro0x0MAIN_PD_GLITCH

When 1, unexpected power glitch was observed on main PD.