Hardware Interfaces and Registers
Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module usbdev
has the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: clk_aon_i
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO:
Pin name | direction | Description |
---|---|---|
sense | input | USB host VBUS sense |
usb_dp | inout | USB data D+ |
usb_dn | inout | USB data D- |
Inter-Module Signals: Reference
Port Name | Package::Struct | Type | Act | Width | Description |
---|---|---|---|---|---|
usb_rx_d | logic | uni | rcv | 1 | USB RX data from an external differential receiver, if available |
usb_tx_d | logic | uni | req | 1 | USB transmit data value (not used if usb_tx_se0 is set) |
usb_tx_se0 | logic | uni | req | 1 | Force transmission of a USB single-ended zero (i.e. both D+ and D- are low) regardless of usb_tx_d |
usb_tx_use_d_se0 | logic | uni | req | 1 | Use the usb_tx_d and usb_tx_se0 TX interface, instead of usb_dp_o and usb_dn_o |
usb_dp_pullup | logic | uni | req | 1 | USB D+ pullup control |
usb_dn_pullup | logic | uni | req | 1 | USB D- pullup control |
usb_rx_enable | logic | uni | req | 1 | USB differential receiver enable |
usb_ref_val | logic | uni | req | 1 | |
usb_ref_pulse | logic | uni | req | 1 | |
usb_aon_suspend_req | logic | uni | req | 1 | |
usb_aon_wake_ack | logic | uni | req | 1 | |
usb_aon_bus_reset | logic | uni | rcv | 1 | |
usb_aon_sense_lost | logic | uni | rcv | 1 | |
usb_aon_wake_detect_active | logic | uni | rcv | 1 | |
ram_cfg | prim_ram_2p_pkg::ram_2p_cfg | uni | rcv | 1 | |
tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts:
Interrupt Name | Type | Description |
---|---|---|
pkt_received | Event | Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry. |
pkt_sent | Event | Raised if a packet was sent as part of an IN transaction.
This interrupt is directly tied to whether a sent packet has not been acknowledged in the |
disconnected | Event | Raised if VBUS is lost thus the link is disconnected. |
host_lost | Event | Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms. |
link_reset | Event | Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us). |
link_suspend | Event | Raised if the line has signaled J for longer than 3ms and is therefore in suspend state. |
link_resume | Event | Raised when the link becomes active again after being suspended. |
av_empty | Event | Raised when the AV FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the AV FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert. |
rx_full | Event | Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert. |
av_overflow | Event | Raised if a write was done to the Available Buffer FIFO when the FIFO was full. |
link_in_err | Event | Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received. |
rx_crc_err | Event | Raised if a CRC error occured. |
rx_pid_err | Event | Raised if an invalid packed identifier (PID) was received. |
rx_bitstuff_err | Event | Raised if an invalid bitstuffing was received. |
frame | Event | Raised when the USB frame number is updated with a valid SOF. |
powered | Event | Raised if VBUS is applied. |
link_out_err | Event | Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO. |
Security Alerts:
Alert Name | Description |
---|---|
fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
Security Countermeasures:
Countermeasure ID | Description |
---|---|
USBDEV.BUS.INTEGRITY | End-to-end bus integrity scheme. |
Registers
Summary | |||
---|---|---|---|
Name | Offset | Length | Description |
usbdev.INTR_STATE | 0x0 | 4 | Interrupt State Register |
usbdev.INTR_ENABLE | 0x4 | 4 | Interrupt Enable Register |
usbdev.INTR_TEST | 0x8 | 4 | Interrupt Test Register |
usbdev.ALERT_TEST | 0xc | 4 | Alert Test Register |
usbdev.usbctrl | 0x10 | 4 | USB Control |
usbdev.ep_out_enable | 0x14 | 4 | Enable an endpoint to respond to transactions in the downstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect. |
usbdev.ep_in_enable | 0x18 | 4 | Enable an endpoint to respond to transactions in the upstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect. |
usbdev.usbstat | 0x1c | 4 | USB Status |
usbdev.avbuffer | 0x20 | 4 | Available Buffer FIFO |
usbdev.rxfifo | 0x24 | 4 | Received Buffer FIFO |
usbdev.rxenable_setup | 0x28 | 4 | Receive SETUP transaction enable |
usbdev.rxenable_out | 0x2c | 4 | Receive OUT transaction enable |
usbdev.set_nak_out | 0x30 | 4 | Set NAK after OUT transactions |
usbdev.in_sent | 0x34 | 4 | IN Transaction Sent |
usbdev.out_stall | 0x38 | 4 | OUT Endpoint STALL control |
usbdev.in_stall | 0x3c | 4 | IN Endpoint STALL control |
usbdev.configin_0 | 0x40 | 4 | Configure IN Transaction |
usbdev.configin_1 | 0x44 | 4 | Configure IN Transaction |
usbdev.configin_2 | 0x48 | 4 | Configure IN Transaction |
usbdev.configin_3 | 0x4c | 4 | Configure IN Transaction |
usbdev.configin_4 | 0x50 | 4 | Configure IN Transaction |
usbdev.configin_5 | 0x54 | 4 | Configure IN Transaction |
usbdev.configin_6 | 0x58 | 4 | Configure IN Transaction |
usbdev.configin_7 | 0x5c | 4 | Configure IN Transaction |
usbdev.configin_8 | 0x60 | 4 | Configure IN Transaction |
usbdev.configin_9 | 0x64 | 4 | Configure IN Transaction |
usbdev.configin_10 | 0x68 | 4 | Configure IN Transaction |
usbdev.configin_11 | 0x6c | 4 | Configure IN Transaction |
usbdev.out_iso | 0x70 | 4 | OUT Endpoint isochronous setting |
usbdev.in_iso | 0x74 | 4 | IN Endpoint isochronous setting |
usbdev.data_toggle_clear | 0x78 | 4 | Clear the data toggle flag |
usbdev.phy_pins_sense | 0x7c | 4 | USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing. |
usbdev.phy_pins_drive | 0x80 | 4 | USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing. |
usbdev.phy_config | 0x84 | 4 | USB PHY Configuration |
usbdev.wake_control | 0x88 | 4 | USB wake module control for suspend / resume |
usbdev.wake_events | 0x8c | 4 | USB wake module events and debug |
usbdev.buffer | 0x800 | 2048 | 2 kB packet buffer. Divided into 32 64-byte buffers. |
usbdev.INTR_STATE @ 0x0
Interrupt State Register Reset default = 0x0, mask 0x1ffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x0 | pkt_received | Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | pkt_sent | Raised if a packet was sent as part of an IN transaction.
This interrupt is directly tied to whether a sent packet has not been acknowledged in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw1c | 0x0 | disconnected | Raised if VBUS is lost thus the link is disconnected. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw1c | 0x0 | host_lost | Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw1c | 0x0 | link_reset | Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw1c | 0x0 | link_suspend | Raised if the line has signaled J for longer than 3ms and is therefore in suspend state. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw1c | 0x0 | link_resume | Raised when the link becomes active again after being suspended. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw1c | 0x0 | av_empty | Raised when the AV FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the AV FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw1c | 0x0 | rx_full | Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw1c | 0x0 | av_overflow | Raised if a write was done to the Available Buffer FIFO when the FIFO was full. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw1c | 0x0 | link_in_err | Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw1c | 0x0 | rx_crc_err | Raised if a CRC error occured. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | rw1c | 0x0 | rx_pid_err | Raised if an invalid packed identifier (PID) was received. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 | rw1c | 0x0 | rx_bitstuff_err | Raised if an invalid bitstuffing was received. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14 | rw1c | 0x0 | frame | Raised when the USB frame number is updated with a valid SOF. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | rw1c | 0x0 | powered | Raised if VBUS is applied. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | rw1c | 0x0 | link_out_err | Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO. |
usbdev.INTR_ENABLE @ 0x4
Interrupt Enable Register Reset default = 0x0, mask 0x1ffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | pkt_received | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | pkt_sent | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | disconnected | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | host_lost | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | link_reset | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | link_suspend | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | link_resume | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | av_empty | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | rx_full | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | av_overflow | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | link_in_err | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | rx_crc_err | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | rw | 0x0 | rx_pid_err | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 | rw | 0x0 | rx_bitstuff_err | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14 | rw | 0x0 | frame | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | rw | 0x0 | powered | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | rw | 0x0 | link_out_err | Enable interrupt when |
usbdev.INTR_TEST @ 0x8
Interrupt Test Register Reset default = 0x0, mask 0x1ffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | pkt_received | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | pkt_sent | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | wo | 0x0 | disconnected | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | wo | 0x0 | host_lost | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | wo | 0x0 | link_reset | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | wo | 0x0 | link_suspend | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | wo | 0x0 | link_resume | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | wo | 0x0 | av_empty | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | wo | 0x0 | rx_full | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | wo | 0x0 | av_overflow | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | wo | 0x0 | link_in_err | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | wo | 0x0 | rx_crc_err | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | wo | 0x0 | rx_pid_err | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 | wo | 0x0 | rx_bitstuff_err | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14 | wo | 0x0 | frame | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | wo | 0x0 | powered | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | wo | 0x0 | link_out_err | Write 1 to force |
usbdev.ALERT_TEST @ 0xc
Alert Test Register Reset default = 0x0, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. |
usbdev.usbctrl @ 0x10
USB Control Reset default = 0x0, mask 0x7f0003
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | enable | Set to connect the USB interface (i.e. assert the pullup). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | resume_link_active | Write a 1 to this bit to instruct usbdev to jump to the LinkResuming state. The write will only have an effect when the device is in the LinkPowered state. Its intention is to handle a resume-from-suspend event after the IP has been powered down. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:2 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
22:16 | rw | 0x0 | device_address | Device address set by host (this should be copied from the Set Device ID SETUP packet). This will be zeroed by the hardware when the link resets. |
usbdev.ep_out_enable @ 0x14
Enable an endpoint to respond to transactions in the downstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect. Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | enable_0 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | enable_1 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | enable_2 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | enable_3 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | enable_4 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | enable_5 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | enable_6 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | enable_7 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | enable_8 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | enable_9 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | enable_10 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | enable_11 | This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored. |
usbdev.ep_in_enable @ 0x18
Enable an endpoint to respond to transactions in the upstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect. Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | enable_0 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | enable_1 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | enable_2 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | enable_3 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | enable_4 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | enable_5 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | enable_6 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | enable_7 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | enable_8 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | enable_9 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | enable_10 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | enable_11 | This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored. |
usbdev.usbstat @ 0x1c
USB Status Reset default = 0x80000000, mask 0x8787ffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10:0 | ro | x | frame | Frame index received from host. On an active link, this will increment every milisecond. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | ro | x | host_lost | Start of frame not received from host for 4.096 ms and the line is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:12 | ro | x | link_state | State of USB link, decoded from line.
Other values are reserved. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | ro | x | sense | Reflects the state of the sense pin. 1 indicates that the host is providing VBUS. Note that this bit always shows the state of the actual pin and does not take account of the override control. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
18:16 | ro | x | av_depth | Number of buffers in the Available Buffer FIFO. These buffers are available for receiving packets. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
22:19 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23 | ro | x | av_full | Available Buffer FIFO is full. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
26:24 | ro | x | rx_depth | Number of buffers in the Received Buffer FIFO. These buffers have packets that have been received and should be popped from the FIFO and processed. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30:27 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | ro | 0x1 | rx_empty | Received Buffer FIFO is empty. |
usbdev.avbuffer @ 0x20
Available Buffer FIFO Reset default = 0x0, mask 0x1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | wo | 0x0 | buffer | This field contains the buffer ID being passed to the USB receive engine. If the Available Buffer FIFO is full, any write operations are discarded. |
usbdev.rxfifo @ 0x24
Received Buffer FIFO Reset default = 0x0, mask 0xf87f1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | ro | x | buffer | This field contains the buffer ID that data was received into. On read the buffer ID is popped from the Received Buffer FIFO and returned to software. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | ro | x | size | This field contains the data length in bytes of the packet written to the buffer. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
18:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19 | ro | x | setup | This bit indicates if the received transaction is of type SETUP (1) or OUT (0). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:20 | ro | x | ep | This field contains the endpoint ID to which the packet was directed. |
usbdev.rxenable_setup @ 0x28
Receive SETUP transaction enable Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | setup_0 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | setup_1 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | setup_2 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | setup_3 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | setup_4 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | setup_5 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | setup_6 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | setup_7 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | setup_8 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | setup_9 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | setup_10 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | setup_11 | This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints). |
usbdev.rxenable_out @ 0x2c
Receive OUT transaction enable Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | out_0 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | out_1 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | out_2 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | out_3 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | out_4 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | out_5 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | out_6 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | out_7 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | out_8 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | out_9 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | out_10 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | out_11 | This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint. |
usbdev.set_nak_out @ 0x30
Set NAK after OUT transactions Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | enable_0 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | enable_1 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | enable_2 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | enable_3 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | enable_4 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | enable_5 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | enable_6 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | enable_7 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | enable_8 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | enable_9 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | enable_10 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | enable_11 | When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active. |
usbdev.in_sent @ 0x34
IN Transaction Sent Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x0 | sent_0 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | sent_1 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw1c | 0x0 | sent_2 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw1c | 0x0 | sent_3 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw1c | 0x0 | sent_4 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw1c | 0x0 | sent_5 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw1c | 0x0 | sent_6 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw1c | 0x0 | sent_7 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw1c | 0x0 | sent_8 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw1c | 0x0 | sent_9 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw1c | 0x0 | sent_10 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw1c | 0x0 | sent_11 | This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction. |
usbdev.out_stall @ 0x38
OUT Endpoint STALL control Reset default = 0x0, mask 0xfff
|
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | endpoint_0 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | endpoint_1 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | endpoint_2 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | endpoint_3 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | endpoint_4 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | endpoint_5 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | endpoint_6 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | endpoint_7 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | endpoint_8 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | endpoint_9 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | endpoint_10 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | endpoint_11 | If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. |
usbdev.in_stall @ 0x3c
IN Endpoint STALL control Reset default = 0x0, mask 0xfff
|
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | endpoint_0 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | endpoint_1 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | endpoint_2 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | endpoint_3 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | endpoint_4 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | endpoint_5 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | endpoint_6 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | endpoint_7 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | endpoint_8 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | endpoint_9 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | endpoint_10 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | endpoint_11 | If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority. Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions. |
usbdev.configin_0 @ 0x40
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
|
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_0 | The buffer ID containing the data to send when an IN transaction is received on the endpoint. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_0 | The number of bytes to send from the buffer. If this is 0 then a CRC only packet is sent. If this is greater than 64 then 64 bytes are sent. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_0 | This bit indicates a pending transaction was canceled by the hardware. The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected. The bit remains set until cleared by being written with a 1. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_0 | This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data. This bit will also be cleared if an enabled SETUP transaction is received on the endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit. |
usbdev.configin_1 @ 0x44
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_1 | For Endpoint1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_1 | For Endpoint1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_1 | For Endpoint1 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_1 | For Endpoint1 |
usbdev.configin_2 @ 0x48
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_2 | For Endpoint2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_2 | For Endpoint2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_2 | For Endpoint2 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_2 | For Endpoint2 |
usbdev.configin_3 @ 0x4c
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_3 | For Endpoint3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_3 | For Endpoint3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_3 | For Endpoint3 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_3 | For Endpoint3 |
usbdev.configin_4 @ 0x50
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
|
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_4 | For Endpoint4 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_4 | For Endpoint4 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_4 | For Endpoint4 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_4 | For Endpoint4 |
usbdev.configin_5 @ 0x54
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
|
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_5 | For Endpoint5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_5 | For Endpoint5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_5 | For Endpoint5 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_5 | For Endpoint5 |
usbdev.configin_6 @ 0x58
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
|
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---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_6 | For Endpoint6 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_6 | For Endpoint6 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_6 | For Endpoint6 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_6 | For Endpoint6 |
usbdev.configin_7 @ 0x5c
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
|
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_7 | For Endpoint7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_7 | For Endpoint7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_7 | For Endpoint7 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_7 | For Endpoint7 |
usbdev.configin_8 @ 0x60
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_8 | For Endpoint8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_8 | For Endpoint8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_8 | For Endpoint8 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_8 | For Endpoint8 |
usbdev.configin_9 @ 0x64
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_9 | For Endpoint9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_9 | For Endpoint9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_9 | For Endpoint9 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_9 | For Endpoint9 |
usbdev.configin_10 @ 0x68
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_10 | For Endpoint10 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_10 | For Endpoint10 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_10 | For Endpoint10 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_10 | For Endpoint10 |
usbdev.configin_11 @ 0x6c
Configure IN Transaction Reset default = 0x0, mask 0xc0007f1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | buffer_11 | For Endpoint11 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:5 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14:8 | rw | 0x0 | size_11 | For Endpoint11 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:15 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | rw1c | 0x0 | pend_11 | For Endpoint11 | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31 | rw | 0x0 | rdy_11 | For Endpoint11 |
usbdev.out_iso @ 0x70
OUT Endpoint isochronous setting Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | iso_0 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | iso_1 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | iso_2 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | iso_3 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | iso_4 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | iso_5 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | iso_6 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | iso_7 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | iso_8 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | iso_9 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | iso_10 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | iso_11 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. |
usbdev.in_iso @ 0x74
IN Endpoint isochronous setting Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | iso_0 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | iso_1 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | iso_2 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | iso_3 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | iso_4 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | iso_5 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | iso_6 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | iso_7 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw | 0x0 | iso_8 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw | 0x0 | iso_9 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw | 0x0 | iso_10 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw | 0x0 | iso_11 | If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration. |
usbdev.data_toggle_clear @ 0x78
Clear the data toggle flag Reset default = 0x0, mask 0xfff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | clear_0 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | clear_1 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | wo | 0x0 | clear_2 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | wo | 0x0 | clear_3 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | wo | 0x0 | clear_4 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | wo | 0x0 | clear_5 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | wo | 0x0 | clear_6 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | wo | 0x0 | clear_7 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | wo | 0x0 | clear_8 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | wo | 0x0 | clear_9 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | wo | 0x0 | clear_10 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | wo | 0x0 | clear_11 | Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns. |
usbdev.phy_pins_sense @ 0x7c
USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing. Reset default = 0x0, mask 0x11f07
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | x | rx_dp_i | USB D+ input. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | x | rx_dn_i | USB D- input. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | ro | x | rx_d_i | USB data input from an external differential receiver, if available. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:3 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | ro | x | tx_dp_o | USB transmit D+ output (readback). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | ro | x | tx_dn_o | USB transmit D- output (readback). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | ro | x | tx_d_o | USB transmit data value (readback). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | ro | x | tx_se0_o | USB single-ended zero output (readback). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | ro | x | tx_oe_o | USB OE output (readback). | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:13 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | ro | x | pwr_sense | USB power sense signal. |
usbdev.phy_pins_drive @ 0x80
USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing. Reset default = 0x0, mask 0x100ff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | dp_o | USB transmit D+ output, used with dn_o. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | dn_o | USB transmit D- output, used with dp_o. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | d_o | USB transmit data output, encoding K and J when se0_o is 0. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | se0_o | USB single-ended zero output. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | rw | 0x0 | oe_o | USB OE output. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | rx_enable_o | Enable differential receiver. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | dp_pullup_en_o | USB D+ pullup enable output. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | dn_pullup_en_o | USB D- pullup enable output. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:8 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | rw | 0x0 | en | 0: Outputs are controlled by the hardware block. 1: Outputs are controlled with this register. |
usbdev.phy_config @ 0x84
USB PHY Configuration Reset default = 0x4, mask 0xe7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | use_diff_rcvr | Detect received K and J symbols from the usb_rx_d signal, which must be driven from an external differential receiver. If 1, make use of the usb_rx_d input. If 0, the usb_rx_d input is ignored and the usb_rx_dp and usb_rx_dn pair are used to detect K and J (useful for some environments, but will be unlikely to pass full USB compliance). Regardless of the state of this field usb_rx_dp and usb_rx_dn are always used to detect SE0. This bit also feeds the rx_enable pin, activating the receiver when the device is not suspended. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | tx_use_d_se0 | If 1, select the d and se0 TX interface. If 0, select the dp and dn TX interface. This directly controls the output pin of the same name. It is intended to be used to enable the use of a variety of external transceivers, to select an encoding that matches the transceiver. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x1 | eop_single_bit | Recognize a single SE0 bit as an end of packet, otherwise two successive bits are required. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:3 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw | 0x0 | pinflip | Flip the D+/D- pins. Particularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | rw | 0x0 | usb_ref_disable | 0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw | 0x0 | tx_osc_test_mode | Disable (0) or enable (1) oscillator test mode. If enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock. Note that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization. The clock might drift off. |
usbdev.wake_control @ 0x88
USB wake module control for suspend / resume Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | suspend_req | Suspend request to the wake detection module. Trigger the wake detection module to begin monitoring for wake-from-suspend events. When written with a 1, the wake detection module will activate. Activation may not happen immediately, and its status can be verified by checking wake_events.module_active. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | wake_ack | Wake acknowledgement. Signal to the wake detection module that it may release control of the pull-ups back to the main block and return to an inactive state. The release back to normal state may not happen immediately. The status can be confirmed via wake_events.module_active. Note that this bit can also be used without powering down, such as when usbdev detects resume signaling before transitions to low power states have begun. |
usbdev.wake_events @ 0x8c
USB wake module events and debug Reset default = 0x0, mask 0x301
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x0 | module_active | USB aon wake module is active, monitoring events and controlling the pull-ups. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:1 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | ro | 0x0 | disconnected | USB aon wake module detected VBUS was interrupted while monitoring events. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | ro | 0x0 | bus_reset | USB aon wake module detected a bus reset while monitoring events. |
usbdev.buffer @ + 0x800
512 item rw window
Byte writes are not supported
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2 kB packet buffer. Divided into 32 64-byte buffers. The packet buffer is used for sending and receiveing packets. |