Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module usbdev has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
senseinput

USB host VBUS sense

usb_dpinout

USB data D+

usb_dninout

USB data D-

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
usb_rx_d logic uni rcv 1 USB RX data from an external differential receiver, if available
usb_tx_d logic uni req 1 USB transmit data value (not used if usb_tx_se0 is set)
usb_tx_se0 logic uni req 1 Force transmission of a USB single-ended zero (i.e. both D+ and D- are low) regardless of usb_tx_d
usb_tx_use_d_se0 logic uni req 1 Use the usb_tx_d and usb_tx_se0 TX interface, instead of usb_dp_o and usb_dn_o
usb_dp_pullup logic uni req 1 USB D+ pullup control
usb_dn_pullup logic uni req 1 USB D- pullup control
usb_rx_enable logic uni req 1 USB differential receiver enable
usb_ref_val logic uni req 1
usb_ref_pulse logic uni req 1
usb_aon_suspend_req logic uni req 1
usb_aon_wake_ack logic uni req 1
usb_aon_bus_reset logic uni rcv 1
usb_aon_sense_lost logic uni rcv 1
usb_aon_wake_detect_active logic uni rcv 1
ram_cfg prim_ram_2p_pkg::ram_2p_cfg uni rcv 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
pkt_receivedEvent

Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry.

pkt_sentEvent

Raised if a packet was sent as part of an IN transaction. This interrupt is directly tied to whether a sent packet has not been acknowledged in the in_sent register. It should be cleared only after clearing all bits in the in_sent register.

disconnectedEvent

Raised if VBUS is lost thus the link is disconnected.

host_lostEvent

Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.

link_resetEvent

Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).

link_suspendEvent

Raised if the line has signaled J for longer than 3ms and is therefore in suspend state.

link_resumeEvent

Raised when the link becomes active again after being suspended.

av_emptyEvent

Raised when the AV FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the AV FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

rx_fullEvent

Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

av_overflowEvent

Raised if a write was done to the Available Buffer FIFO when the FIFO was full.

link_in_errEvent

Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.

rx_crc_errEvent

Raised if a CRC error occured.

rx_pid_errEvent

Raised if an invalid packed identifier (PID) was received.

rx_bitstuff_errEvent

Raised if an invalid bitstuffing was received.

frameEvent

Raised when the USB frame number is updated with a valid SOF.

poweredEvent

Raised if VBUS is applied.

link_out_errEvent

Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO.

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
USBDEV.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
usbdev.INTR_STATE 0x0 4

Interrupt State Register

usbdev.INTR_ENABLE 0x4 4

Interrupt Enable Register

usbdev.INTR_TEST 0x8 4

Interrupt Test Register

usbdev.ALERT_TEST 0xc 4

Alert Test Register

usbdev.usbctrl 0x10 4

USB Control

usbdev.ep_out_enable 0x14 4

Enable an endpoint to respond to transactions in the downstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

usbdev.ep_in_enable 0x18 4

Enable an endpoint to respond to transactions in the upstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

usbdev.usbstat 0x1c 4

USB Status

usbdev.avbuffer 0x20 4

Available Buffer FIFO

usbdev.rxfifo 0x24 4

Received Buffer FIFO

usbdev.rxenable_setup 0x28 4

Receive SETUP transaction enable

usbdev.rxenable_out 0x2c 4

Receive OUT transaction enable

usbdev.set_nak_out 0x30 4

Set NAK after OUT transactions

usbdev.in_sent 0x34 4

IN Transaction Sent

usbdev.out_stall 0x38 4

OUT Endpoint STALL control

usbdev.in_stall 0x3c 4

IN Endpoint STALL control

usbdev.configin_0 0x40 4

Configure IN Transaction

usbdev.configin_1 0x44 4

Configure IN Transaction

usbdev.configin_2 0x48 4

Configure IN Transaction

usbdev.configin_3 0x4c 4

Configure IN Transaction

usbdev.configin_4 0x50 4

Configure IN Transaction

usbdev.configin_5 0x54 4

Configure IN Transaction

usbdev.configin_6 0x58 4

Configure IN Transaction

usbdev.configin_7 0x5c 4

Configure IN Transaction

usbdev.configin_8 0x60 4

Configure IN Transaction

usbdev.configin_9 0x64 4

Configure IN Transaction

usbdev.configin_10 0x68 4

Configure IN Transaction

usbdev.configin_11 0x6c 4

Configure IN Transaction

usbdev.out_iso 0x70 4

OUT Endpoint isochronous setting

usbdev.in_iso 0x74 4

IN Endpoint isochronous setting

usbdev.data_toggle_clear 0x78 4

Clear the data toggle flag

usbdev.phy_pins_sense 0x7c 4

USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

usbdev.phy_pins_drive 0x80 4

USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

usbdev.phy_config 0x84 4

USB PHY Configuration

usbdev.wake_control 0x88 4

USB wake module control for suspend / resume

usbdev.wake_events 0x8c 4

USB wake module events and debug

usbdev.buffer 0x800 2048

2 kB packet buffer. Divided into 32 64-byte buffers.

usbdev.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1ffff
31302928272625242322212019181716
  link_out_err
1514131211109876543210
powered frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0rw1c0x0pkt_received

Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry.

1rw1c0x0pkt_sent

Raised if a packet was sent as part of an IN transaction. This interrupt is directly tied to whether a sent packet has not been acknowledged in the in_sent register. It should be cleared only after clearing all bits in the in_sent register.

2rw1c0x0disconnected

Raised if VBUS is lost thus the link is disconnected.

3rw1c0x0host_lost

Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.

4rw1c0x0link_reset

Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).

5rw1c0x0link_suspend

Raised if the line has signaled J for longer than 3ms and is therefore in suspend state.

6rw1c0x0link_resume

Raised when the link becomes active again after being suspended.

7rw1c0x0av_empty

Raised when the AV FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the AV FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

8rw1c0x0rx_full

Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

9rw1c0x0av_overflow

Raised if a write was done to the Available Buffer FIFO when the FIFO was full.

10rw1c0x0link_in_err

Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.

11rw1c0x0rx_crc_err

Raised if a CRC error occured.

12rw1c0x0rx_pid_err

Raised if an invalid packed identifier (PID) was received.

13rw1c0x0rx_bitstuff_err

Raised if an invalid bitstuffing was received.

14rw1c0x0frame

Raised when the USB frame number is updated with a valid SOF.

15rw1c0x0powered

Raised if VBUS is applied.

16rw1c0x0link_out_err

Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO.


usbdev.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1ffff
31302928272625242322212019181716
  link_out_err
1514131211109876543210
powered frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0rw0x0pkt_received

Enable interrupt when INTR_STATE.pkt_received is set.

1rw0x0pkt_sent

Enable interrupt when INTR_STATE.pkt_sent is set.

2rw0x0disconnected

Enable interrupt when INTR_STATE.disconnected is set.

3rw0x0host_lost

Enable interrupt when INTR_STATE.host_lost is set.

4rw0x0link_reset

Enable interrupt when INTR_STATE.link_reset is set.

5rw0x0link_suspend

Enable interrupt when INTR_STATE.link_suspend is set.

6rw0x0link_resume

Enable interrupt when INTR_STATE.link_resume is set.

7rw0x0av_empty

Enable interrupt when INTR_STATE.av_empty is set.

8rw0x0rx_full

Enable interrupt when INTR_STATE.rx_full is set.

9rw0x0av_overflow

Enable interrupt when INTR_STATE.av_overflow is set.

10rw0x0link_in_err

Enable interrupt when INTR_STATE.link_in_err is set.

11rw0x0rx_crc_err

Enable interrupt when INTR_STATE.rx_crc_err is set.

12rw0x0rx_pid_err

Enable interrupt when INTR_STATE.rx_pid_err is set.

13rw0x0rx_bitstuff_err

Enable interrupt when INTR_STATE.rx_bitstuff_err is set.

14rw0x0frame

Enable interrupt when INTR_STATE.frame is set.

15rw0x0powered

Enable interrupt when INTR_STATE.powered is set.

16rw0x0link_out_err

Enable interrupt when INTR_STATE.link_out_err is set.


usbdev.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1ffff
31302928272625242322212019181716
  link_out_err
1514131211109876543210
powered frame rx_bitstuff_err rx_pid_err rx_crc_err link_in_err av_overflow rx_full av_empty link_resume link_suspend link_reset host_lost disconnected pkt_sent pkt_received
BitsTypeResetNameDescription
0wo0x0pkt_received

Write 1 to force INTR_STATE.pkt_received to 1.

1wo0x0pkt_sent

Write 1 to force INTR_STATE.pkt_sent to 1.

2wo0x0disconnected

Write 1 to force INTR_STATE.disconnected to 1.

3wo0x0host_lost

Write 1 to force INTR_STATE.host_lost to 1.

4wo0x0link_reset

Write 1 to force INTR_STATE.link_reset to 1.

5wo0x0link_suspend

Write 1 to force INTR_STATE.link_suspend to 1.

6wo0x0link_resume

Write 1 to force INTR_STATE.link_resume to 1.

7wo0x0av_empty

Write 1 to force INTR_STATE.av_empty to 1.

8wo0x0rx_full

Write 1 to force INTR_STATE.rx_full to 1.

9wo0x0av_overflow

Write 1 to force INTR_STATE.av_overflow to 1.

10wo0x0link_in_err

Write 1 to force INTR_STATE.link_in_err to 1.

11wo0x0rx_crc_err

Write 1 to force INTR_STATE.rx_crc_err to 1.

12wo0x0rx_pid_err

Write 1 to force INTR_STATE.rx_pid_err to 1.

13wo0x0rx_bitstuff_err

Write 1 to force INTR_STATE.rx_bitstuff_err to 1.

14wo0x0frame

Write 1 to force INTR_STATE.frame to 1.

15wo0x0powered

Write 1 to force INTR_STATE.powered to 1.

16wo0x0link_out_err

Write 1 to force INTR_STATE.link_out_err to 1.


usbdev.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


usbdev.usbctrl @ 0x10

USB Control

Reset default = 0x0, mask 0x7f0003
31302928272625242322212019181716
  device_address
1514131211109876543210
  resume_link_active enable
BitsTypeResetNameDescription
0rw0x0enable

Set to connect the USB interface (i.e. assert the pullup).

1wo0x0resume_link_active

Write a 1 to this bit to instruct usbdev to jump to the LinkResuming state. The write will only have an effect when the device is in the LinkPowered state. Its intention is to handle a resume-from-suspend event after the IP has been powered down.

15:2Reserved
22:16rw0x0device_address

Device address set by host (this should be copied from the Set Device ID SETUP packet).

This will be zeroed by the hardware when the link resets.


usbdev.ep_out_enable @ 0x14

Enable an endpoint to respond to transactions in the downstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  enable_11 enable_10 enable_9 enable_8 enable_7 enable_6 enable_5 enable_4 enable_3 enable_2 enable_1 enable_0
BitsTypeResetNameDescription
0rw0x0enable_0

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

1rw0x0enable_1

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

2rw0x0enable_2

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

3rw0x0enable_3

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

4rw0x0enable_4

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

5rw0x0enable_5

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

6rw0x0enable_6

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

7rw0x0enable_7

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

8rw0x0enable_8

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

9rw0x0enable_9

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

10rw0x0enable_10

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

11rw0x0enable_11

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.


usbdev.ep_in_enable @ 0x18

Enable an endpoint to respond to transactions in the upstream direction. Note that as the default endpoint, endpoint 0 must be enabled in both the IN and OUT directions before enabling the USB interface to connect.

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  enable_11 enable_10 enable_9 enable_8 enable_7 enable_6 enable_5 enable_4 enable_3 enable_2 enable_1 enable_0
BitsTypeResetNameDescription
0rw0x0enable_0

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

1rw0x0enable_1

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

2rw0x0enable_2

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

3rw0x0enable_3

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

4rw0x0enable_4

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

5rw0x0enable_5

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

6rw0x0enable_6

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

7rw0x0enable_7

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

8rw0x0enable_8

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

9rw0x0enable_9

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

10rw0x0enable_10

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

11rw0x0enable_11

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.


usbdev.usbstat @ 0x1c

USB Status

Reset default = 0x80000000, mask 0x8787ffff
31302928272625242322212019181716
rx_empty   rx_depth av_full   av_depth
1514131211109876543210
sense link_state host_lost frame
BitsTypeResetNameDescription
10:0roxframe

Frame index received from host. On an active link, this will increment every milisecond.

11roxhost_lost

Start of frame not received from host for 4.096 ms and the line is active.

14:12roxlink_state

State of USB link, decoded from line.

0x0disconnected

Link disconnected (no VBUS or no pull-up connected)

0x1powered

Link powered and connected, but not reset yet

0x2powered_suspended

Link suspended (constant idle/J for > 3 ms), but not reset yet

0x3active

Link active

0x4suspended

Link suspended (constant idle for > 3 ms), was active before becoming suspended

0x5active_nosof

Link active but no SOF has been received since the last reset.

0x6resuming

Link resuming to an active state, pending the end of resume signaling

Other values are reserved.

15roxsense

Reflects the state of the sense pin. 1 indicates that the host is providing VBUS. Note that this bit always shows the state of the actual pin and does not take account of the override control.

18:16roxav_depth

Number of buffers in the Available Buffer FIFO.

These buffers are available for receiving packets.

22:19Reserved
23roxav_full

Available Buffer FIFO is full.

26:24roxrx_depth

Number of buffers in the Received Buffer FIFO.

These buffers have packets that have been received and should be popped from the FIFO and processed.

30:27Reserved
31ro0x1rx_empty

Received Buffer FIFO is empty.


usbdev.avbuffer @ 0x20

Available Buffer FIFO

Reset default = 0x0, mask 0x1f
31302928272625242322212019181716
 
1514131211109876543210
  buffer
BitsTypeResetNameDescription
4:0wo0x0buffer

This field contains the buffer ID being passed to the USB receive engine.

If the Available Buffer FIFO is full, any write operations are discarded.


usbdev.rxfifo @ 0x24

Received Buffer FIFO

Reset default = 0x0, mask 0xf87f1f
31302928272625242322212019181716
  ep setup  
1514131211109876543210
  size   buffer
BitsTypeResetNameDescription
4:0roxbuffer

This field contains the buffer ID that data was received into. On read the buffer ID is popped from the Received Buffer FIFO and returned to software.

7:5Reserved
14:8roxsize

This field contains the data length in bytes of the packet written to the buffer.

18:15Reserved
19roxsetup

This bit indicates if the received transaction is of type SETUP (1) or OUT (0).

23:20roxep

This field contains the endpoint ID to which the packet was directed.


usbdev.rxenable_setup @ 0x28

Receive SETUP transaction enable

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  setup_11 setup_10 setup_9 setup_8 setup_7 setup_6 setup_5 setup_4 setup_3 setup_2 setup_1 setup_0
BitsTypeResetNameDescription
0rw0x0setup_0

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

1rw0x0setup_1

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

2rw0x0setup_2

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

3rw0x0setup_3

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

4rw0x0setup_4

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

5rw0x0setup_5

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

6rw0x0setup_6

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

7rw0x0setup_7

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

8rw0x0setup_8

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

9rw0x0setup_9

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

10rw0x0setup_10

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

11rw0x0setup_11

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).


usbdev.rxenable_out @ 0x2c

Receive OUT transaction enable

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  out_11 out_10 out_9 out_8 out_7 out_6 out_5 out_4 out_3 out_2 out_1 out_0
BitsTypeResetNameDescription
0rw0x0out_0

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

1rw0x0out_1

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

2rw0x0out_2

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

3rw0x0out_3

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

4rw0x0out_4

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

5rw0x0out_5

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

6rw0x0out_6

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

7rw0x0out_7

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

8rw0x0out_8

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

9rw0x0out_9

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

10rw0x0out_10

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

11rw0x0out_11

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.


usbdev.set_nak_out @ 0x30

Set NAK after OUT transactions

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  enable_11 enable_10 enable_9 enable_8 enable_7 enable_6 enable_5 enable_4 enable_3 enable_2 enable_1 enable_0
BitsTypeResetNameDescription
0rw0x0enable_0

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

1rw0x0enable_1

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

2rw0x0enable_2

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

3rw0x0enable_3

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

4rw0x0enable_4

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

5rw0x0enable_5

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

6rw0x0enable_6

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

7rw0x0enable_7

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

8rw0x0enable_8

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

9rw0x0enable_9

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

10rw0x0enable_10

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

11rw0x0enable_11

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.


usbdev.in_sent @ 0x34

IN Transaction Sent

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  sent_11 sent_10 sent_9 sent_8 sent_7 sent_6 sent_5 sent_4 sent_3 sent_2 sent_1 sent_0
BitsTypeResetNameDescription
0rw1c0x0sent_0

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

1rw1c0x0sent_1

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

2rw1c0x0sent_2

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

3rw1c0x0sent_3

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

4rw1c0x0sent_4

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

5rw1c0x0sent_5

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

6rw1c0x0sent_6

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

7rw1c0x0sent_7

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

8rw1c0x0sent_8

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

9rw1c0x0sent_9

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

10rw1c0x0sent_10

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

11rw1c0x0sent_11

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.


usbdev.out_stall @ 0x38

OUT Endpoint STALL control

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  endpoint_11 endpoint_10 endpoint_9 endpoint_8 endpoint_7 endpoint_6 endpoint_5 endpoint_4 endpoint_3 endpoint_2 endpoint_1 endpoint_0
BitsTypeResetNameDescription
0rw0x0endpoint_0

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

1rw0x0endpoint_1

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

2rw0x0endpoint_2

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

3rw0x0endpoint_3

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

4rw0x0endpoint_4

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

5rw0x0endpoint_5

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

6rw0x0endpoint_6

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

7rw0x0endpoint_7

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

8rw0x0endpoint_8

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

9rw0x0endpoint_9

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

10rw0x0endpoint_10

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

11rw0x0endpoint_11

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.


usbdev.in_stall @ 0x3c

IN Endpoint STALL control

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  endpoint_11 endpoint_10 endpoint_9 endpoint_8 endpoint_7 endpoint_6 endpoint_5 endpoint_4 endpoint_3 endpoint_2 endpoint_1 endpoint_0
BitsTypeResetNameDescription
0rw0x0endpoint_0

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

1rw0x0endpoint_1

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

2rw0x0endpoint_2

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

3rw0x0endpoint_3

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

4rw0x0endpoint_4

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

5rw0x0endpoint_5

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

6rw0x0endpoint_6

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

7rw0x0endpoint_7

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

8rw0x0endpoint_8

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

9rw0x0endpoint_9

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

10rw0x0endpoint_10

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

11rw0x0endpoint_11

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.


usbdev.configin_0 @ 0x40

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_0 pend_0  
1514131211109876543210
  size_0   buffer_0
BitsTypeResetNameDescription
4:0rw0x0buffer_0

The buffer ID containing the data to send when an IN transaction is received on the endpoint.

7:5Reserved
14:8rw0x0size_0

The number of bytes to send from the buffer.

If this is 0 then a CRC only packet is sent.

If this is greater than 64 then 64 bytes are sent.

29:15Reserved
30rw1c0x0pend_0

This bit indicates a pending transaction was canceled by the hardware.

The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected.

The bit remains set until cleared by being written with a 1.

31rw0x0rdy_0

This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data.

This bit will also be cleared if an enabled SETUP transaction is received on the endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit.


usbdev.configin_1 @ 0x44

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_1 pend_1  
1514131211109876543210
  size_1   buffer_1
BitsTypeResetNameDescription
4:0rw0x0buffer_1

For Endpoint1

7:5Reserved
14:8rw0x0size_1

For Endpoint1

29:15Reserved
30rw1c0x0pend_1

For Endpoint1

31rw0x0rdy_1

For Endpoint1


usbdev.configin_2 @ 0x48

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_2 pend_2  
1514131211109876543210
  size_2   buffer_2
BitsTypeResetNameDescription
4:0rw0x0buffer_2

For Endpoint2

7:5Reserved
14:8rw0x0size_2

For Endpoint2

29:15Reserved
30rw1c0x0pend_2

For Endpoint2

31rw0x0rdy_2

For Endpoint2


usbdev.configin_3 @ 0x4c

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_3 pend_3  
1514131211109876543210
  size_3   buffer_3
BitsTypeResetNameDescription
4:0rw0x0buffer_3

For Endpoint3

7:5Reserved
14:8rw0x0size_3

For Endpoint3

29:15Reserved
30rw1c0x0pend_3

For Endpoint3

31rw0x0rdy_3

For Endpoint3


usbdev.configin_4 @ 0x50

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_4 pend_4  
1514131211109876543210
  size_4   buffer_4
BitsTypeResetNameDescription
4:0rw0x0buffer_4

For Endpoint4

7:5Reserved
14:8rw0x0size_4

For Endpoint4

29:15Reserved
30rw1c0x0pend_4

For Endpoint4

31rw0x0rdy_4

For Endpoint4


usbdev.configin_5 @ 0x54

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_5 pend_5  
1514131211109876543210
  size_5   buffer_5
BitsTypeResetNameDescription
4:0rw0x0buffer_5

For Endpoint5

7:5Reserved
14:8rw0x0size_5

For Endpoint5

29:15Reserved
30rw1c0x0pend_5

For Endpoint5

31rw0x0rdy_5

For Endpoint5


usbdev.configin_6 @ 0x58

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_6 pend_6  
1514131211109876543210
  size_6   buffer_6
BitsTypeResetNameDescription
4:0rw0x0buffer_6

For Endpoint6

7:5Reserved
14:8rw0x0size_6

For Endpoint6

29:15Reserved
30rw1c0x0pend_6

For Endpoint6

31rw0x0rdy_6

For Endpoint6


usbdev.configin_7 @ 0x5c

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_7 pend_7  
1514131211109876543210
  size_7   buffer_7
BitsTypeResetNameDescription
4:0rw0x0buffer_7

For Endpoint7

7:5Reserved
14:8rw0x0size_7

For Endpoint7

29:15Reserved
30rw1c0x0pend_7

For Endpoint7

31rw0x0rdy_7

For Endpoint7


usbdev.configin_8 @ 0x60

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_8 pend_8  
1514131211109876543210
  size_8   buffer_8
BitsTypeResetNameDescription
4:0rw0x0buffer_8

For Endpoint8

7:5Reserved
14:8rw0x0size_8

For Endpoint8

29:15Reserved
30rw1c0x0pend_8

For Endpoint8

31rw0x0rdy_8

For Endpoint8


usbdev.configin_9 @ 0x64

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_9 pend_9  
1514131211109876543210
  size_9   buffer_9
BitsTypeResetNameDescription
4:0rw0x0buffer_9

For Endpoint9

7:5Reserved
14:8rw0x0size_9

For Endpoint9

29:15Reserved
30rw1c0x0pend_9

For Endpoint9

31rw0x0rdy_9

For Endpoint9


usbdev.configin_10 @ 0x68

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_10 pend_10  
1514131211109876543210
  size_10   buffer_10
BitsTypeResetNameDescription
4:0rw0x0buffer_10

For Endpoint10

7:5Reserved
14:8rw0x0size_10

For Endpoint10

29:15Reserved
30rw1c0x0pend_10

For Endpoint10

31rw0x0rdy_10

For Endpoint10


usbdev.configin_11 @ 0x6c

Configure IN Transaction

Reset default = 0x0, mask 0xc0007f1f
31302928272625242322212019181716
rdy_11 pend_11  
1514131211109876543210
  size_11   buffer_11
BitsTypeResetNameDescription
4:0rw0x0buffer_11

For Endpoint11

7:5Reserved
14:8rw0x0size_11

For Endpoint11

29:15Reserved
30rw1c0x0pend_11

For Endpoint11

31rw0x0rdy_11

For Endpoint11


usbdev.out_iso @ 0x70

OUT Endpoint isochronous setting

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  iso_11 iso_10 iso_9 iso_8 iso_7 iso_6 iso_5 iso_4 iso_3 iso_2 iso_1 iso_0
BitsTypeResetNameDescription
0rw0x0iso_0

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

1rw0x0iso_1

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

2rw0x0iso_2

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

3rw0x0iso_3

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

4rw0x0iso_4

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

5rw0x0iso_5

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

6rw0x0iso_6

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

7rw0x0iso_7

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

8rw0x0iso_8

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

9rw0x0iso_9

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

10rw0x0iso_10

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

11rw0x0iso_11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.


usbdev.in_iso @ 0x74

IN Endpoint isochronous setting

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  iso_11 iso_10 iso_9 iso_8 iso_7 iso_6 iso_5 iso_4 iso_3 iso_2 iso_1 iso_0
BitsTypeResetNameDescription
0rw0x0iso_0

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

1rw0x0iso_1

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

2rw0x0iso_2

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

3rw0x0iso_3

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

4rw0x0iso_4

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

5rw0x0iso_5

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

6rw0x0iso_6

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

7rw0x0iso_7

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

8rw0x0iso_8

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

9rw0x0iso_9

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

10rw0x0iso_10

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

11rw0x0iso_11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.


usbdev.data_toggle_clear @ 0x78

Clear the data toggle flag

Reset default = 0x0, mask 0xfff
31302928272625242322212019181716
 
1514131211109876543210
  clear_11 clear_10 clear_9 clear_8 clear_7 clear_6 clear_5 clear_4 clear_3 clear_2 clear_1 clear_0
BitsTypeResetNameDescription
0wo0x0clear_0

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

1wo0x0clear_1

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

2wo0x0clear_2

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

3wo0x0clear_3

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

4wo0x0clear_4

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

5wo0x0clear_5

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

6wo0x0clear_6

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

7wo0x0clear_7

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

8wo0x0clear_8

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

9wo0x0clear_9

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

10wo0x0clear_10

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

11wo0x0clear_11

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.


usbdev.phy_pins_sense @ 0x7c

USB PHY pins sense. This register can be used to read out the state of the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

Reset default = 0x0, mask 0x11f07
31302928272625242322212019181716
  pwr_sense
1514131211109876543210
  tx_oe_o tx_se0_o tx_d_o tx_dn_o tx_dp_o   rx_d_i rx_dn_i rx_dp_i
BitsTypeResetNameDescription
0roxrx_dp_i

USB D+ input.

1roxrx_dn_i

USB D- input.

2roxrx_d_i

USB data input from an external differential receiver, if available.

7:3Reserved
8roxtx_dp_o

USB transmit D+ output (readback).

9roxtx_dn_o

USB transmit D- output (readback).

10roxtx_d_o

USB transmit data value (readback).

11roxtx_se0_o

USB single-ended zero output (readback).

12roxtx_oe_o

USB OE output (readback).

15:13Reserved
16roxpwr_sense

USB power sense signal.


usbdev.phy_pins_drive @ 0x80

USB PHY pins drive. This register can be used to control the USB device inputs and outputs from software. This is designed to be used for debugging purposes or during chip testing.

Reset default = 0x0, mask 0x100ff
31302928272625242322212019181716
  en
1514131211109876543210
  dn_pullup_en_o dp_pullup_en_o rx_enable_o oe_o se0_o d_o dn_o dp_o
BitsTypeResetNameDescription
0rw0x0dp_o

USB transmit D+ output, used with dn_o.

1rw0x0dn_o

USB transmit D- output, used with dp_o.

2rw0x0d_o

USB transmit data output, encoding K and J when se0_o is 0.

3rw0x0se0_o

USB single-ended zero output.

4rw0x0oe_o

USB OE output.

5rw0x0rx_enable_o

Enable differential receiver.

6rw0x0dp_pullup_en_o

USB D+ pullup enable output.

7rw0x0dn_pullup_en_o

USB D- pullup enable output.

15:8Reserved
16rw0x0en

0: Outputs are controlled by the hardware block. 1: Outputs are controlled with this register.


usbdev.phy_config @ 0x84

USB PHY Configuration

Reset default = 0x4, mask 0xe7
31302928272625242322212019181716
 
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  tx_osc_test_mode usb_ref_disable pinflip   eop_single_bit tx_use_d_se0 use_diff_rcvr
BitsTypeResetNameDescription
0rw0x0use_diff_rcvr

Detect received K and J symbols from the usb_rx_d signal, which must be driven from an external differential receiver. If 1, make use of the usb_rx_d input. If 0, the usb_rx_d input is ignored and the usb_rx_dp and usb_rx_dn pair are used to detect K and J (useful for some environments, but will be unlikely to pass full USB compliance). Regardless of the state of this field usb_rx_dp and usb_rx_dn are always used to detect SE0. This bit also feeds the rx_enable pin, activating the receiver when the device is not suspended.

1rw0x0tx_use_d_se0

If 1, select the d and se0 TX interface. If 0, select the dp and dn TX interface. This directly controls the output pin of the same name. It is intended to be used to enable the use of a variety of external transceivers, to select an encoding that matches the transceiver.

2rw0x1eop_single_bit

Recognize a single SE0 bit as an end of packet, otherwise two successive bits are required.

4:3Reserved
5rw0x0pinflip

Flip the D+/D- pins. Particularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C.

6rw0x0usb_ref_disable

0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero.

7rw0x0tx_osc_test_mode

Disable (0) or enable (1) oscillator test mode. If enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock. Note that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization. The clock might drift off.


usbdev.wake_control @ 0x88

USB wake module control for suspend / resume

Reset default = 0x0, mask 0x3
31302928272625242322212019181716
 
1514131211109876543210
  wake_ack suspend_req
BitsTypeResetNameDescription
0wo0x0suspend_req

Suspend request to the wake detection module.

Trigger the wake detection module to begin monitoring for wake-from-suspend events. When written with a 1, the wake detection module will activate. Activation may not happen immediately, and its status can be verified by checking wake_events.module_active.

1wo0x0wake_ack

Wake acknowledgement.

Signal to the wake detection module that it may release control of the pull-ups back to the main block and return to an inactive state. The release back to normal state may not happen immediately. The status can be confirmed via wake_events.module_active.

Note that this bit can also be used without powering down, such as when usbdev detects resume signaling before transitions to low power states have begun.


usbdev.wake_events @ 0x8c

USB wake module events and debug

Reset default = 0x0, mask 0x301
31302928272625242322212019181716
 
1514131211109876543210
  bus_reset disconnected   module_active
BitsTypeResetNameDescription
0ro0x0module_active

USB aon wake module is active, monitoring events and controlling the pull-ups.

7:1Reserved
8ro0x0disconnected

USB aon wake module detected VBUS was interrupted while monitoring events.

9ro0x0bus_reset

USB aon wake module detected a bus reset while monitoring events.


usbdev.buffer @ + 0x800
512 item rw window
Byte writes are not supported
310
+0x800 
+0x804 
 ...
+0xff8 
+0xffc 

2 kB packet buffer. Divided into 32 64-byte buffers.

The packet buffer is used for sending and receiveing packets.