Raised if a packet was received using an OUT or SETUP transaction. This interrupt is directly tied to whether the RX FIFO is empty, so it should be cleared only after handling the FIFO entry.

Raised if a packet was sent as part of an IN transaction. This interrupt is directly tied to whether a sent packet has not been acknowledged in the in_sent register. It should be cleared only after clearing all bits in the in_sent register.

Raised if VBUS is lost thus the link is disconnected.

Raised if link is active but SOF was not received from host for 4.096 ms. The SOF should be every 1 ms.

Raised if the link is at SE0 longer than 3 us indicating a link reset (host asserts for min 10 ms, device can react after 2.5 us).

Raised if the line has signaled J for longer than 3ms and is therefore in suspend state.

Raised when the link becomes active again after being suspended.

Raised when the AV FIFO is empty and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the AV FIFO must be provided a free buffer before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

Raised when the RX FIFO is full and the device interface is enabled. This interrupt is directly tied to the FIFO status, so the RX FIFO must have an entry removed before the interrupt is cleared. If the condition is not cleared, the interrupt can re-assert.

Raised if a write was done to the Available Buffer FIFO when the FIFO was full.

Raised if a packet to an IN endpoint started to be received but was then dropped due to an error. After transmitting the IN payload, the USB device expects a valid ACK handshake packet. This error is raised if either the packet or CRC is invalid or a different token was received.

Raised if a CRC error occured.

Raised if an invalid packed identifier (PID) was received.

Raised if an invalid bitstuffing was received.

Raised when the USB frame number is updated with a valid SOF.

Raised if VBUS is applied.

Raised if a packet to an OUT endpoint started to be received but was then dropped due to an error. This error is raised if either the data toggle, token, packet or CRC is invalid or if there is no buffer available in the Received Buffer FIFO.

Enable interrupt when INTR_STATE.pkt_received is set.

Enable interrupt when INTR_STATE.pkt_sent is set.

Enable interrupt when INTR_STATE.disconnected is set.

Enable interrupt when INTR_STATE.host_lost is set.

Enable interrupt when INTR_STATE.link_reset is set.

Enable interrupt when INTR_STATE.link_suspend is set.

Enable interrupt when INTR_STATE.link_resume is set.

Enable interrupt when INTR_STATE.av_empty is set.

Enable interrupt when INTR_STATE.rx_full is set.

Enable interrupt when INTR_STATE.av_overflow is set.

Enable interrupt when INTR_STATE.link_in_err is set.

Enable interrupt when INTR_STATE.rx_crc_err is set.

Enable interrupt when INTR_STATE.rx_pid_err is set.

Enable interrupt when INTR_STATE.rx_bitstuff_err is set.

Enable interrupt when INTR_STATE.frame is set.

Enable interrupt when INTR_STATE.powered is set.

Enable interrupt when INTR_STATE.link_out_err is set.

Write 1 to force INTR_STATE.pkt_received to 1.

Write 1 to force INTR_STATE.pkt_sent to 1.

Write 1 to force INTR_STATE.disconnected to 1.

Write 1 to force INTR_STATE.host_lost to 1.

Write 1 to force INTR_STATE.link_reset to 1.

Write 1 to force INTR_STATE.link_suspend to 1.

Write 1 to force INTR_STATE.link_resume to 1.

Write 1 to force INTR_STATE.av_empty to 1.

Write 1 to force INTR_STATE.rx_full to 1.

Write 1 to force INTR_STATE.av_overflow to 1.

Write 1 to force INTR_STATE.link_in_err to 1.

Write 1 to force INTR_STATE.rx_crc_err to 1.

Write 1 to force INTR_STATE.rx_pid_err to 1.

Write 1 to force INTR_STATE.rx_bitstuff_err to 1.

Write 1 to force INTR_STATE.frame to 1.

Write 1 to force INTR_STATE.powered to 1.

Write 1 to force INTR_STATE.link_out_err to 1.

Write 1 to trigger one alert event of this kind.

Set to connect the USB interface (i.e. assert the pullup).

Write a 1 to this bit to instruct usbdev to jump to the LinkResuming state. The write will only have an effect when the device is in the LinkPowered state. Its intention is to handle a resume-from-suspend event after the IP has been powered down.

Device address set by host (this should be copied from the Set Device ID SETUP packet).

This will be zeroed by the hardware when the link resets.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable downstream transactions to be received on the endpoint and elicit responses. If the bit is clear, any SETUP or OUT packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

This bit must be set to enable upstream transactions to be received on the endpoint and elicit responses. If the bit is clear then any IN packets sent to the endpoint will be ignored.

Frame index received from host. On an active link, this will increment every milisecond.

Start of frame not received from host for 4.096 ms and the line is active.

State of USB link, decoded from line.

Other values are reserved.

Reflects the state of the sense pin. 1 indicates that the host is providing VBUS. Note that this bit always shows the state of the actual pin and does not take account of the override control.

Number of buffers in the Available Buffer FIFO.

These buffers are available for receiving packets.

Available Buffer FIFO is full.

Number of buffers in the Received Buffer FIFO.

These buffers have packets that have been received and should be popped from the FIFO and processed.

Received Buffer FIFO is empty.

This field contains the buffer ID being passed to the USB receive engine.

If the Available Buffer FIFO is full, any write operations are discarded.

This field contains the buffer ID that data was received into. On read the buffer ID is popped from the Received Buffer FIFO and returned to software.

This field contains the data length in bytes of the packet written to the buffer.

This bit indicates if the received transaction is of type SETUP (1) or OUT (0).

This field contains the endpoint ID to which the packet was directed.

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable SETUP transactions to be received on the endpoint. If the bit is clear then a SETUP packet will be ignored. The bit should be set for control endpoints (and only control endpoints).

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

This bit must be set to enable OUT transactions to be received on the endpoint. If the bit is clear then an OUT request will be responded to with a NAK, if the endpoint is enabled. If set_nak_out for this endpoint is set, hardware will clear this bit whenever an OUT transaction is received on this endpoint. Software must set this bit again to receive the next OUT transaction. Until that happens, hardware will continue to NAK any OUT transaction to this endpoint.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

When this bit is set, hardware will clear this endpoint's rxenable_out bit whenever an OUT transaction is received on this endpoint. This bit should not be changed while the endpoint is active.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

This bit will be set when the ACK is received from the host to indicate successful packet delivery as part of an IN transaction.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an OUT transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

If this bit is set then an IN transaction to this endpoint will elicit a STALL handshake, when a non-isochronous endpoint is enabled. If the configuration has both STALL and NAK enabled, the STALL handshake will take priority.

Note that SETUP transactions are always either accepted or ignored. For endpoints that accept SETUP transactions, a SETUP packet will clear the STALL flag on endpoints for both the IN and OUT directions.

The buffer ID containing the data to send when an IN transaction is received on the endpoint.

The number of bytes to send from the buffer.

If this is 0 then a CRC only packet is sent.

If this is greater than 64 then 64 bytes are sent.

This bit indicates a pending transaction was canceled by the hardware.

The bit is set when the rdy bit is cleared by hardware because of a SETUP packet being received or a link reset being detected.

The bit remains set until cleared by being written with a 1.

This bit should be set to indicate the buffer is ready for sending. It will be cleared when the ACK is received indicating the host has accepted the data.

This bit will also be cleared if an enabled SETUP transaction is received on the endpoint. This allows use of the IN channel for transfer of SETUP information. The original buffer must be resubmitted after the SETUP sequence is complete. A link reset also clears the bit. In either of the cases where the hardware cancels the transaction it will also set the pend bit.

For Endpoint1

For Endpoint1

For Endpoint1

For Endpoint1

For Endpoint2

For Endpoint2

For Endpoint2

For Endpoint2

For Endpoint3

For Endpoint3

For Endpoint3

For Endpoint3

For Endpoint4

For Endpoint4

For Endpoint4

For Endpoint4

For Endpoint5

For Endpoint5

For Endpoint5

For Endpoint5

For Endpoint6

For Endpoint6

For Endpoint6

For Endpoint6

For Endpoint7

For Endpoint7

For Endpoint7

For Endpoint7

For Endpoint8

For Endpoint8

For Endpoint8

For Endpoint8

For Endpoint9

For Endpoint9

For Endpoint9

For Endpoint9

For Endpoint10

For Endpoint10

For Endpoint10

For Endpoint10

For Endpoint11

For Endpoint11

For Endpoint11

For Endpoint11

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be sent for an OUT transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

If this bit is set then the endpoint will be treated as an isochronous endpoint. No handshake packet will be expected for an IN transaction. Note that if a rxenable_setup is set for this endpoint's number, this bit will not take effect. Control endpoint configuration trumps isochronous endpoint configuration.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

Writing 1 to this bit will clear the data toggle bit for this endpoint to Data0 in both IN and OUT directions. The register must no be written again within 200 ns.

USB D+ input.

USB D- input.

USB data input from an external differential receiver, if available.

USB transmit D+ output (readback).

USB transmit D- output (readback).

USB transmit data value (readback).

USB single-ended zero output (readback).

USB OE output (readback).

USB power sense signal.

USB transmit D+ output, used with dn_o.

USB transmit D- output, used with dp_o.

USB transmit data output, encoding K and J when se0_o is 0.

USB single-ended zero output.

USB OE output.

Enable differential receiver.

USB D+ pullup enable output.

USB D- pullup enable output.

0: Outputs are controlled by the hardware block. 1: Outputs are controlled with this register.

Detect received K and J symbols from the usb_rx_d signal, which must be driven from an external differential receiver. If 1, make use of the usb_rx_d input. If 0, the usb_rx_d input is ignored and the usb_rx_dp and usb_rx_dn pair are used to detect K and J (useful for some environments, but will be unlikely to pass full USB compliance). Regardless of the state of this field usb_rx_dp and usb_rx_dn are always used to detect SE0. This bit also feeds the rx_enable pin, activating the receiver when the device is not suspended.

If 1, select the d and se0 TX interface. If 0, select the dp and dn TX interface. This directly controls the output pin of the same name. It is intended to be used to enable the use of a variety of external transceivers, to select an encoding that matches the transceiver.

Recognize a single SE0 bit as an end of packet, otherwise two successive bits are required.

Flip the D+/D- pins. Particularly useful if D+/D- are mapped to SBU1/SBU2 pins of USB-C.

0: Enable reference signal generation for clock synchronization, 1: disable it by forcing the associated signals to zero.

Disable (0) or enable (1) oscillator test mode. If enabled, the device constantly transmits a J/K pattern, which is useful for testing the USB clock. Note that while in oscillator test mode, the device no longer receives SOFs and consequently does not generate the reference signal for clock synchronization. The clock might drift off.

Suspend request to the wake detection module.

Trigger the wake detection module to begin monitoring for wake-from-suspend events. When written with a 1, the wake detection module will activate. Activation may not happen immediately, and its status can be verified by checking wake_events.module_active.

Wake acknowledgement.

Signal to the wake detection module that it may release control of the pull-ups back to the main block and return to an inactive state. The release back to normal state may not happen immediately. The status can be confirmed via wake_events.module_active.

Note that this bit can also be used without powering down, such as when usbdev detects resume signaling before transitions to low power states have begun.

USB aon wake module is active, monitoring events and controlling the pull-ups.

USB aon wake module detected VBUS was interrupted while monitoring events.

USB aon wake module detected a bus reset while monitoring events.

2 kB packet buffer. Divided into 32 64-byte buffers.

The packet buffer is used for sending and receiveing packets.