Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module lc_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_kmac_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
jtag jtag_pkg::jtag req_rsp rsp 1
esc_scrap_state0_tx prim_esc_pkg::esc_tx uni rcv 1
esc_scrap_state0_rx prim_esc_pkg::esc_rx uni req 1
esc_scrap_state1_tx prim_esc_pkg::esc_tx uni rcv 1
esc_scrap_state1_rx prim_esc_pkg::esc_rx uni req 1
pwr_lc pwrmgr_pkg::pwr_lc req_rsp rsp 1
lc_otp_vendor_test otp_ctrl_pkg::lc_otp_vendor_test req_rsp req 1
otp_lc_data otp_ctrl_pkg::otp_lc_data uni rcv 1
lc_otp_program otp_ctrl_pkg::lc_otp_program req_rsp req 1
kmac_data kmac_pkg::app req_rsp req 1
lc_dft_en lc_ctrl_pkg::lc_tx uni req 1
lc_nvm_debug_en lc_ctrl_pkg::lc_tx uni req 1
lc_hw_debug_en lc_ctrl_pkg::lc_tx uni req 1
lc_cpu_en lc_ctrl_pkg::lc_tx uni req 1
lc_keymgr_en lc_ctrl_pkg::lc_tx uni req 1
lc_escalate_en lc_ctrl_pkg::lc_tx uni req 1
lc_clk_byp_req lc_ctrl_pkg::lc_tx uni req 1
lc_clk_byp_ack lc_ctrl_pkg::lc_tx uni rcv 1
lc_flash_rma_req lc_ctrl_pkg::lc_tx uni req 1
lc_flash_rma_seed lc_ctrl_pkg::lc_flash_rma_seed uni req 1
lc_flash_rma_ack lc_ctrl_pkg::lc_tx uni rcv 1
lc_check_byp_en lc_ctrl_pkg::lc_tx uni req 1
lc_creator_seed_sw_rw_en lc_ctrl_pkg::lc_tx uni req 1
lc_owner_seed_sw_rw_en lc_ctrl_pkg::lc_tx uni req 1
lc_iso_part_sw_rd_en lc_ctrl_pkg::lc_tx uni req 1
lc_iso_part_sw_wr_en lc_ctrl_pkg::lc_tx uni req 1
lc_seed_hw_rd_en lc_ctrl_pkg::lc_tx uni req 1
lc_keymgr_div lc_ctrl_pkg::lc_keymgr_div uni req 1
otp_device_id otp_ctrl_pkg::otp_device_id uni rcv 1
otp_manuf_state otp_ctrl_pkg::otp_manuf_state uni rcv 1
hw_rev lc_ctrl_pkg::lc_hw_rev uni req 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts: none

Security Alerts:

Alert NameDescription
fatal_prog_error

This alert triggers if an error occurred during an OTP programming operation.

fatal_state_error

This alert triggers if an error in the life cycle state or life cycle controller FSM is detected.

fatal_bus_integ_error

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
LC_CTRL.BUS.INTEGRITY

End-to-end bus integrity scheme.

LC_CTRL.TRANSITION.CONFIG.REGWEN

The transition interface registers are REGWEN protected. The REGWEN is governed by hardware, and is only set to 1 if the interface mutex has been successfully claimed. Also, the REGWEN is set to 0 while a state transition is in progress in order to prevent any accidental changes to the transition interface CSRs during that phase.

LC_CTRL.MANUF.STATE.SPARSE

The manufacturing state vector is sparsely encoded. Although the encoding is randomly chosen, it satisfies specific Hamming weight and Hamming distance thresholds (see lc_ctrl_state_pkg.sv for the statistics). All manufacturing state encodings (except for the RAW state) have been constructed so that all OTP words belonging to the manufacturing state vector have a non-zero value. The individual OTP words are unique and have been engineered so that each word can be incrementally overwritten with another engineered value without causing the ECC bits added by the OTP macro to become inconsistent.

LC_CTRL.TRANSITION.CTR.SPARSE

The life cycle transition counter state is sparsely encoded. Although the encoding is randomly chosen, it satisfies specific Hamming weight and Hamming distance thresholds (see lc_ctrl_state_pkg.sv for the statistics). All counter state encodings (except for the 0 state) have been constructed so that all OTP words belonging to the counter state vector have a non-zero value. The individual OTP words are unique and have been engineered so that each word can be incrementally overwritten with another engineered value without causing the ECC bits added by the OTP macro to become inconsistent.

LC_CTRL.MANUF.STATE.BKGN_CHK

The manufacturing state vector is continuously decoded and checked, once the life cycle controller has initialized. If any mismatch is detected, local escalation is triggered (MAIN.FSM.LOCAL_ESC).

LC_CTRL.TRANSITION.CTR.BKGN_CHK

The life cycle transition counter is continuously decoded and checked, once the life cycle controller has initialized. If any mismatch is detected, local escalation is triggered (MAIN.FSM.LOCAL_ESC). Note that any non-RAW manufacturing state requires the transition counter to be nonzero. Also, the transition counter is used to enforce a limit of maximum 24 state transitions in order to guard against bruteforcing.

LC_CTRL.STATE.CONFIG.SPARSE

The decoded manufacturing state uses a replicated enum encoding to fill the 32bit value exposed in the CSRs (both the LC_STATE and TRANSITION_TARGET registers). This is done to 1) ease hardening of firmware code, and 2) to ensure that even the decoded life cycle state vector inside the life cycle controller still has a redundant encoding.

LC_CTRL.MAIN.FSM.SPARSE

The main state FSM is sparsely encoded.

LC_CTRL.KMAC.FSM.SPARSE

The KMAC interface FSM is sparsely encoded.

LC_CTRL.MAIN.FSM.LOCAL_ESC

Upon local escalation due to an invalid state encoding of the life cycle state vector or an invalid KMAC interface FSM state, the main state FSM moves to the InvalidSt state which behaves like a virtual scrap state.

LC_CTRL.MAIN.FSM.GLOBAL_ESC

Upon global escalation (triggered by the alert escalation receivers), the main state FSM moves to the EscalateSt state which behaves like a virtual scrap state.

LC_CTRL.MAIN.CTRL_FLOW.CONSISTENCY

The control flow of the main FSM is constructed so that the FSM only progresses linearly in one direction. There are no transition arcs that loop back to previous FSM states.

LC_CTRL.INTERSIG.MUBI

Life cycle control signals are multibit encoded.

LC_CTRL.TOKEN_VALID.CTRL.MUBI

The token valid signals coming from OTP are MUBI encoded.

LC_CTRL.TOKEN.DIGEST

Life cycle transition tokens are hashed with cSHAKE128, using a custom 'LC_CTRL' prefix.

LC_CTRL.TOKEN_MUX.CTRL.REDUN

The life cycle transition token mux is broken into two halves that are steered with separately decoded and buffered MUBI valid signals (see also TOKEN_VALID.CTRL.MUBI).

LC_CTRL.TOKEN_VALID.MUX.REDUN

The life cycle transition token valid mux is replicated twice. If a transition is initiated and the two mux index signals are inconsistent or if any of the two valid mux outputs is not set to valid, the transition will fail with a TRANSITION_ERROR.

Registers

Summary
Name Offset Length Description
lc_ctrl.ALERT_TEST 0x0 4

Alert Test Register
lc_ctrl.STATUS 0x4 4

life cycle status register. Note that all errors are terminal and require a reset cycle.
lc_ctrl.CLAIM_TRANSITION_IF 0x8 4

Hardware mutex to claim exclusive access to the transition interface.
lc_ctrl.TRANSITION_REGWEN 0xc 4

Register write enable for all transition interface registers.
lc_ctrl.TRANSITION_CMD 0x10 4

Command register for state transition requests.
lc_ctrl.TRANSITION_CTRL 0x14 4

Control register for state transition requests.
lc_ctrl.TRANSITION_TOKEN_0 0x18 4

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.
lc_ctrl.TRANSITION_TOKEN_1 0x1c 4

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.
lc_ctrl.TRANSITION_TOKEN_2 0x20 4

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.
lc_ctrl.TRANSITION_TOKEN_3 0x24 4

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.
lc_ctrl.TRANSITION_TARGET 0x28 4

This register exposes the decoded life cycle state.
lc_ctrl.OTP_VENDOR_TEST_CTRL 0x2c 4

Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will be gated to zero before sending them to the OTP macro wrapper - even if this register is programmed to a non-zero value.
lc_ctrl.OTP_VENDOR_TEST_STATUS 0x30 4

Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will read as zero.
lc_ctrl.LC_STATE 0x34 4

This register exposes the decoded life cycle state.
lc_ctrl.LC_TRANSITION_CNT 0x38 4

This register exposes the state of the decoded life cycle transition counter.
lc_ctrl.LC_ID_STATE 0x3c 4

This register exposes the id state of the device.
lc_ctrl.HW_REV 0x40 4

This register holds the 32bit hardware revision, which is split into two 16bit fields holding the CHIP_GEN and CHIP_REV numbers.
lc_ctrl.DEVICE_ID_0 0x44 4

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.
lc_ctrl.DEVICE_ID_1 0x48 4

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.
lc_ctrl.DEVICE_ID_2 0x4c 4

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.
lc_ctrl.DEVICE_ID_3 0x50 4

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.
lc_ctrl.DEVICE_ID_4 0x54 4

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.
lc_ctrl.DEVICE_ID_5 0x58 4

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.
lc_ctrl.DEVICE_ID_6 0x5c 4

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.
lc_ctrl.DEVICE_ID_7 0x60 4

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.
lc_ctrl.MANUF_STATE_0 0x64 4

This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_1 0x68 4

This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_2 0x6c 4

This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_3 0x70 4

This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_4 0x74 4

This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_5 0x78 4

This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_6 0x7c 4

This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.MANUF_STATE_7 0x80 4

This is a 256bit field used for keeping track of the manufacturing state.
lc_ctrl.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
1514131211109876543210
  fatal_bus_integ_error fatal_state_error fatal_prog_error
BitsTypeResetNameDescription
0wo0x0fatal_prog_error

Write 1 to trigger one alert event of this kind.

1wo0x0fatal_state_error

Write 1 to trigger one alert event of this kind.

2wo0x0fatal_bus_integ_error

Write 1 to trigger one alert event of this kind.


lc_ctrl.STATUS @ 0x4

life cycle status register. Note that all errors are terminal and require a reset cycle.

Reset default = 0x0, mask 0x7ff
31302928272625242322212019181716
 
1514131211109876543210
  OTP_PARTITION_ERROR BUS_INTEG_ERROR STATE_ERROR OTP_ERROR FLASH_RMA_ERROR TOKEN_ERROR TRANSITION_ERROR TRANSITION_COUNT_ERROR TRANSITION_SUCCESSFUL READY INITIALIZED
BitsTypeResetNameDescription
0roxINITIALIZED

This bit is set to 1 if the life cycle controller has successfully initialized and the state exposed in LC_STATE and LC_TRANSITION_CNT is valid.

1roxREADY

This bit is set to 1 if the life cycle controller has successfully initialized and is ready to accept a life cycle transition command.

2roxTRANSITION_SUCCESSFUL

This bit is set to 1 if the last life cycle transition request was successful. Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

3roxTRANSITION_COUNT_ERROR

This bit is set to 1 if the LC_TRANSITION_CNT has reached its maximum. If this is the case, no more state transitions can be performed. Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

4roxTRANSITION_ERROR

This bit is set to 1 if the last transition command requested an invalid state transition (e.g. DEV -> RAW). Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

5roxTOKEN_ERROR

This bit is set to 1 if the token supplied for a conditional transition was invalid. Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

6roxFLASH_RMA_ERROR

This bit is set to 1 if flash failed to correctly respond to an RMA request. Note that each transition attempt increments the LC_TRANSITION_CNT and moves the life cycle state into POST_TRANSITION.

7roxOTP_ERROR

This bit is set to 1 if an error occurred during an OTP programming operation. This error will move the life cycle state automatically to POST_TRANSITION and raise a fatal_prog_error alert.

8roxSTATE_ERROR

This bit is set to 1 if either the controller FSM state or the life cycle state is invalid or has been corrupted as part of a tampering attempt. This error will move the life cycle state automatically to INVALID and raise a fatal_state_error alert.

9roxBUS_INTEG_ERROR

This bit is set to 1 if a fatal bus integrity fault is detected. This error triggers a fatal_bus_integ_error alert.

10roxOTP_PARTITION_ERROR

This bit is set to 1 if the life cycle partition in OTP is in error state. This bit is intended for production testing during the RAW life cycle state, where the OTP control and status registers are not accessible. This error does not trigger an alert in the life cycle controller.


lc_ctrl.CLAIM_TRANSITION_IF @ 0x8

Hardware mutex to claim exclusive access to the transition interface.

Reset default = 0x69, mask 0xff
31302928272625242322212019181716
 
1514131211109876543210
  MUTEX
BitsTypeResetNameDescription
7:0rw0x69MUTEX

In order to have exclusive access to the transition interface, SW must first claim the associated hardware mutex by writing kMultiBitBool8True to this register. If the register reads back kMultiBitBool8True, the mutex claim has been successful, and TRANSITION_REGWEN will be set automatically to 1 by HW. Write 0 to this register in order to release the HW mutex.


lc_ctrl.TRANSITION_REGWEN @ 0xc

Register write enable for all transition interface registers.

Reset default = 0x0, mask 0x1
31302928272625242322212019181716
 
1514131211109876543210
  TRANSITION_REGWEN
BitsTypeResetNameDescription
0ro0x0TRANSITION_REGWEN

This bit is hardware-managed and only readable by software. By default, this bit is set to 0 by hardware. Once SW has claimed the CLAIM_TRANSITION_IF mutex, this bit will be set to 1. Note that the life cycle controller sets this bit temporarily to 0 while executing a life cycle state transition.


lc_ctrl.TRANSITION_CMD @ 0x10

Command register for state transition requests.

Reset default = 0x0, mask 0x1
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  START
BitsTypeResetNameDescription
0r0w1cxSTART

Writing a 1 to this register initiates the life cycle state transition to the state specified in TRANSITION_TARGET. Note that not all transitions are possible, and certain conditional transitions require an additional TRANSITION_TOKEN_0. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.


lc_ctrl.TRANSITION_CTRL @ 0x14

Control register for state transition requests.

Reset default = 0x0, mask 0x1
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
 
1514131211109876543210
  EXT_CLOCK_EN
BitsTypeResetNameDescription
0rw1sxEXT_CLOCK_EN

When set to 1, the OTP clock will be switched to an externally supplied clock right away when the device is in a non-PROD life cycle state. The clock mux will remain switched until the next system reset.


lc_ctrl.TRANSITION_TOKEN_0 @ 0x18

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.

Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
TRANSITION_TOKEN_0...
1514131211109876543210
...TRANSITION_TOKEN_0
BitsTypeResetNameDescription
31:0rwxTRANSITION_TOKEN_0

lc_ctrl.TRANSITION_TOKEN_1 @ 0x1c

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.

Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
TRANSITION_TOKEN_1...
1514131211109876543210
...TRANSITION_TOKEN_1
BitsTypeResetNameDescription
31:0rwxTRANSITION_TOKEN_1

For WORD1


lc_ctrl.TRANSITION_TOKEN_2 @ 0x20

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.

Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
TRANSITION_TOKEN_2...
1514131211109876543210
...TRANSITION_TOKEN_2
BitsTypeResetNameDescription
31:0rwxTRANSITION_TOKEN_2

For WORD2


lc_ctrl.TRANSITION_TOKEN_3 @ 0x24

128bit token for conditional transitions. Make sure to set this to 0 for unconditional transitions. Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.

Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
TRANSITION_TOKEN_3...
1514131211109876543210
...TRANSITION_TOKEN_3
BitsTypeResetNameDescription
31:0rwxTRANSITION_TOKEN_3

For WORD3


lc_ctrl.TRANSITION_TARGET @ 0x28

This register exposes the decoded life cycle state.

Reset default = 0x0, mask 0x3fffffff
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
  STATE...
1514131211109876543210
...STATE
BitsTypeResetNameDescription
29:0rwxSTATE

This field encodes the target life cycle state in a redundant enum format. The 5bit state enum is repeated 6x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, val, val, val, val].

Note that this register is shared with the life cycle TAP interface. In order to have exclusive access to this register, SW must first claim the associated hardware mutex via CLAIM_TRANSITION_IF.

0x00000000RAW

Raw life cycle state after fabrication where all functions are disabled.

0x02108421TEST_UNLOCKED0

Unlocked test state where debug functions are enabled.

0x04210842TEST_LOCKED0

Locked test state where where all functions are disabled.

0x06318c63TEST_UNLOCKED1

Unlocked test state where debug functions are enabled.

0x08421084TEST_LOCKED1

Locked test state where where all functions are disabled.

0x0a5294a5TEST_UNLOCKED2

Unlocked test state where debug functions are enabled.

0x0c6318c6TEST_LOCKED2

Locked test state where debug all functions are disabled.

0x0e739ce7TEST_UNLOCKED3

Unlocked test state where debug functions are enabled.

0x10842108TEST_LOCKED3

Locked test state where debug all functions are disabled.

0x1294a529TEST_UNLOCKED4

Unlocked test state where debug functions are enabled.

0x14a5294aTEST_LOCKED4

Locked test state where debug all functions are disabled.

0x16b5ad6bTEST_UNLOCKED5

Unlocked test state where debug functions are enabled.

0x18c6318cTEST_LOCKED5

Locked test state where debug all functions are disabled.

0x1ad6b5adTEST_UNLOCKED6

Unlocked test state where debug functions are enabled.

0x1ce739ceTEST_LOCKED6

Locked test state where debug all functions are disabled.

0x1ef7bdefTEST_UNLOCKED7

Unlocked test state where debug functions are enabled.

0x21084210DEV

Development life cycle state where limited debug functionality is available.

0x2318c631PROD

Production life cycle state.

0x25294a52PROD_END

Same as PROD, but transition into RMA is not possible from this state.

0x2739ce73RMA

RMA life cycle state.

0x294a5294SCRAP

SCRAP life cycle state where all functions are disabled.

Other values are reserved.


lc_ctrl.OTP_VENDOR_TEST_CTRL @ 0x2c

Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will be gated to zero before sending them to the OTP macro wrapper - even if this register is programmed to a non-zero value.

Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
OTP_VENDOR_TEST_CTRL...
1514131211109876543210
...OTP_VENDOR_TEST_CTRL
BitsTypeResetNameDescription
31:0rwxOTP_VENDOR_TEST_CTRL

lc_ctrl.OTP_VENDOR_TEST_STATUS @ 0x30

Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will read as zero.

Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN
31302928272625242322212019181716
OTP_VENDOR_TEST_STATUS...
1514131211109876543210
...OTP_VENDOR_TEST_STATUS
BitsTypeResetNameDescription
31:0roxOTP_VENDOR_TEST_STATUS

lc_ctrl.LC_STATE @ 0x34

This register exposes the decoded life cycle state.

Reset default = 0x0, mask 0x3fffffff
31302928272625242322212019181716
  STATE...
1514131211109876543210
...STATE
BitsTypeResetNameDescription
29:0roxSTATE

This field exposes the decoded life cycle state in a redundant enum format. The 5bit state enum is repeated 6x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, val, val, val, val].

0x00000000RAW

Raw life cycle state after fabrication where all functions are disabled.

0x02108421TEST_UNLOCKED0

Unlocked test state where debug functions are enabled.

0x04210842TEST_LOCKED0

Locked test state where where all functions are disabled.

0x06318c63TEST_UNLOCKED1

Unlocked test state where debug functions are enabled.

0x08421084TEST_LOCKED1

Locked test state where where all functions are disabled.

0x0a5294a5TEST_UNLOCKED2

Unlocked test state where debug functions are enabled.

0x0c6318c6TEST_LOCKED2

Locked test state where debug all functions are disabled.

0x0e739ce7TEST_UNLOCKED3

Unlocked test state where debug functions are enabled.

0x10842108TEST_LOCKED3

Locked test state where debug all functions are disabled.

0x1294a529TEST_UNLOCKED4

Unlocked test state where debug functions are enabled.

0x14a5294aTEST_LOCKED4

Locked test state where debug all functions are disabled.

0x16b5ad6bTEST_UNLOCKED5

Unlocked test state where debug functions are enabled.

0x18c6318cTEST_LOCKED5

Locked test state where debug all functions are disabled.

0x1ad6b5adTEST_UNLOCKED6

Unlocked test state where debug functions are enabled.

0x1ce739ceTEST_LOCKED6

Locked test state where debug all functions are disabled.

0x1ef7bdefTEST_UNLOCKED7

Unlocked test state where debug functions are enabled.

0x21084210DEV

Development life cycle state where limited debug functionality is available.

0x2318c631PROD

Production life cycle state.

0x25294a52PROD_END

Same as PROD, but transition into RMA is not possible from this state.

0x2739ce73RMA

RMA life cycle state.

0x294a5294SCRAP

SCRAP life cycle state where all functions are disabled.

0x2b5ad6b5POST_TRANSITION

This state is temporary and behaves the same way as SCRAP.

0x2d6b5ad6ESCALATE

This state is temporary and behaves the same way as SCRAP.

0x2f7bdef7INVALID

This state is reported when the life cycle state encoding is invalid. This state is temporary and behaves the same way as SCRAP.

Other values are reserved.


lc_ctrl.LC_TRANSITION_CNT @ 0x38

This register exposes the state of the decoded life cycle transition counter.

Reset default = 0x0, mask 0x1f
31302928272625242322212019181716
 
1514131211109876543210
  CNT
BitsTypeResetNameDescription
4:0roxCNT

Number of total life cycle state transition attempts. The life cycle controller allows up to 24 transition attempts. If this counter is equal to 24, the LC_STATE is considered to be invalid and will read as SCRAP.

If the counter state is invalid, or the life cycle controller is in the post-transition state, the counter will have the value 31 (i.e., all counter bits will be set).


lc_ctrl.LC_ID_STATE @ 0x3c

This register exposes the id state of the device.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
STATE...
1514131211109876543210
...STATE
BitsTypeResetNameDescription
31:0roxSTATE

This field exposes the id state in redundant enum format. The 2bit id state enum is repeated 16x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, ... val]."

0x00000000BLANK

The device has not yet been personalized.

0x11111111PERSONALIZED

The device has been personalized.

0x22222222INVALID

The state is not valid.

Other values are reserved.


lc_ctrl.HW_REV @ 0x40

This register holds the 32bit hardware revision, which is split into two 16bit fields holding the CHIP_GEN and CHIP_REV numbers.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
CHIP_GEN
1514131211109876543210
CHIP_REV
BitsTypeResetNameDescription
15:0roxCHIP_REV

Chip revision number.

31:16roxCHIP_GEN

Chip generation number.


lc_ctrl.DEVICE_ID_0 @ 0x44

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DEVICE_ID_0...
1514131211109876543210
...DEVICE_ID_0
BitsTypeResetNameDescription
31:0roxDEVICE_ID_0

lc_ctrl.DEVICE_ID_1 @ 0x48

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DEVICE_ID_1...
1514131211109876543210
...DEVICE_ID_1
BitsTypeResetNameDescription
31:0roxDEVICE_ID_1

For WORD1


lc_ctrl.DEVICE_ID_2 @ 0x4c

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DEVICE_ID_2...
1514131211109876543210
...DEVICE_ID_2
BitsTypeResetNameDescription
31:0roxDEVICE_ID_2

For WORD2


lc_ctrl.DEVICE_ID_3 @ 0x50

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DEVICE_ID_3...
1514131211109876543210
...DEVICE_ID_3
BitsTypeResetNameDescription
31:0roxDEVICE_ID_3

For WORD3


lc_ctrl.DEVICE_ID_4 @ 0x54

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DEVICE_ID_4...
1514131211109876543210
...DEVICE_ID_4
BitsTypeResetNameDescription
31:0roxDEVICE_ID_4

For WORD4


lc_ctrl.DEVICE_ID_5 @ 0x58

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DEVICE_ID_5...
1514131211109876543210
...DEVICE_ID_5
BitsTypeResetNameDescription
31:0roxDEVICE_ID_5

For WORD5


lc_ctrl.DEVICE_ID_6 @ 0x5c

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DEVICE_ID_6...
1514131211109876543210
...DEVICE_ID_6
BitsTypeResetNameDescription
31:0roxDEVICE_ID_6

For WORD6


lc_ctrl.DEVICE_ID_7 @ 0x60

This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
DEVICE_ID_7...
1514131211109876543210
...DEVICE_ID_7
BitsTypeResetNameDescription
31:0roxDEVICE_ID_7

For WORD7


lc_ctrl.MANUF_STATE_0 @ 0x64

This is a 256bit field used for keeping track of the manufacturing state.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MANUF_STATE_0...
1514131211109876543210
...MANUF_STATE_0
BitsTypeResetNameDescription
31:0roxMANUF_STATE_0

lc_ctrl.MANUF_STATE_1 @ 0x68

This is a 256bit field used for keeping track of the manufacturing state.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MANUF_STATE_1...
1514131211109876543210
...MANUF_STATE_1
BitsTypeResetNameDescription
31:0roxMANUF_STATE_1

For WORD1


lc_ctrl.MANUF_STATE_2 @ 0x6c

This is a 256bit field used for keeping track of the manufacturing state.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MANUF_STATE_2...
1514131211109876543210
...MANUF_STATE_2
BitsTypeResetNameDescription
31:0roxMANUF_STATE_2

For WORD2


lc_ctrl.MANUF_STATE_3 @ 0x70

This is a 256bit field used for keeping track of the manufacturing state.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MANUF_STATE_3...
1514131211109876543210
...MANUF_STATE_3
BitsTypeResetNameDescription
31:0roxMANUF_STATE_3

For WORD3


lc_ctrl.MANUF_STATE_4 @ 0x74

This is a 256bit field used for keeping track of the manufacturing state.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MANUF_STATE_4...
1514131211109876543210
...MANUF_STATE_4
BitsTypeResetNameDescription
31:0roxMANUF_STATE_4

For WORD4


lc_ctrl.MANUF_STATE_5 @ 0x78

This is a 256bit field used for keeping track of the manufacturing state.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MANUF_STATE_5...
1514131211109876543210
...MANUF_STATE_5
BitsTypeResetNameDescription
31:0roxMANUF_STATE_5

For WORD5


lc_ctrl.MANUF_STATE_6 @ 0x7c

This is a 256bit field used for keeping track of the manufacturing state.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MANUF_STATE_6...
1514131211109876543210
...MANUF_STATE_6
BitsTypeResetNameDescription
31:0roxMANUF_STATE_6

For WORD6


lc_ctrl.MANUF_STATE_7 @ 0x80

This is a 256bit field used for keeping track of the manufacturing state.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
MANUF_STATE_7...
1514131211109876543210
...MANUF_STATE_7
BitsTypeResetNameDescription
31:0roxMANUF_STATE_7

For WORD7