Hardware Interfaces and Registers
Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module lc_ctrl
has the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: clk_kmac_i
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO: none
Inter-Module Signals: Reference
Port Name | Package::Struct | Type | Act | Width | Description |
---|---|---|---|---|---|
jtag | jtag_pkg::jtag | req_rsp | rsp | 1 | |
esc_scrap_state0_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | |
esc_scrap_state0_rx | prim_esc_pkg::esc_rx | uni | req | 1 | |
esc_scrap_state1_tx | prim_esc_pkg::esc_tx | uni | rcv | 1 | |
esc_scrap_state1_rx | prim_esc_pkg::esc_rx | uni | req | 1 | |
pwr_lc | pwrmgr_pkg::pwr_lc | req_rsp | rsp | 1 | |
lc_otp_vendor_test | otp_ctrl_pkg::lc_otp_vendor_test | req_rsp | req | 1 | |
otp_lc_data | otp_ctrl_pkg::otp_lc_data | uni | rcv | 1 | |
lc_otp_program | otp_ctrl_pkg::lc_otp_program | req_rsp | req | 1 | |
kmac_data | kmac_pkg::app | req_rsp | req | 1 | |
lc_dft_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_nvm_debug_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_cpu_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_keymgr_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_clk_byp_req | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_clk_byp_ack | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
lc_flash_rma_req | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_flash_rma_seed | lc_ctrl_pkg::lc_flash_rma_seed | uni | req | 1 | |
lc_flash_rma_ack | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
lc_check_byp_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_creator_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_owner_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_iso_part_sw_rd_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_iso_part_sw_wr_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_seed_hw_rd_en | lc_ctrl_pkg::lc_tx | uni | req | 1 | |
lc_keymgr_div | lc_ctrl_pkg::lc_keymgr_div | uni | req | 1 | |
otp_device_id | otp_ctrl_pkg::otp_device_id | uni | rcv | 1 | |
otp_manuf_state | otp_ctrl_pkg::otp_manuf_state | uni | rcv | 1 | |
hw_rev | lc_ctrl_pkg::lc_hw_rev | uni | req | 1 | |
tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts: none
Security Alerts:
Alert Name | Description |
---|---|
fatal_prog_error | This alert triggers if an error occurred during an OTP programming operation. |
fatal_state_error | This alert triggers if an error in the life cycle state or life cycle controller FSM is detected. |
fatal_bus_integ_error | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
Security Countermeasures:
Countermeasure ID | Description |
---|---|
LC_CTRL.BUS.INTEGRITY | End-to-end bus integrity scheme. |
LC_CTRL.TRANSITION.CONFIG.REGWEN | The transition interface registers are REGWEN protected. The REGWEN is governed by hardware, and is only set to 1 if the interface mutex has been successfully claimed. Also, the REGWEN is set to 0 while a state transition is in progress in order to prevent any accidental changes to the transition interface CSRs during that phase. |
LC_CTRL.MANUF.STATE.SPARSE | The manufacturing state vector is sparsely encoded. Although the encoding is randomly chosen, it satisfies specific Hamming weight and Hamming distance thresholds (see lc_ctrl_state_pkg.sv for the statistics). All manufacturing state encodings (except for the RAW state) have been constructed so that all OTP words belonging to the manufacturing state vector have a non-zero value. The individual OTP words are unique and have been engineered so that each word can be incrementally overwritten with another engineered value without causing the ECC bits added by the OTP macro to become inconsistent. |
LC_CTRL.TRANSITION.CTR.SPARSE | The life cycle transition counter state is sparsely encoded. Although the encoding is randomly chosen, it satisfies specific Hamming weight and Hamming distance thresholds (see lc_ctrl_state_pkg.sv for the statistics). All counter state encodings (except for the 0 state) have been constructed so that all OTP words belonging to the counter state vector have a non-zero value. The individual OTP words are unique and have been engineered so that each word can be incrementally overwritten with another engineered value without causing the ECC bits added by the OTP macro to become inconsistent. |
LC_CTRL.MANUF.STATE.BKGN_CHK | The manufacturing state vector is continuously decoded and checked, once the life cycle controller has initialized. If any mismatch is detected, local escalation is triggered (MAIN.FSM.LOCAL_ESC). |
LC_CTRL.TRANSITION.CTR.BKGN_CHK | The life cycle transition counter is continuously decoded and checked, once the life cycle controller has initialized. If any mismatch is detected, local escalation is triggered (MAIN.FSM.LOCAL_ESC). Note that any non-RAW manufacturing state requires the transition counter to be nonzero. Also, the transition counter is used to enforce a limit of maximum 24 state transitions in order to guard against bruteforcing. |
LC_CTRL.STATE.CONFIG.SPARSE | The decoded manufacturing state uses a replicated enum encoding to fill the 32bit value exposed in the CSRs (both the LC_STATE and TRANSITION_TARGET registers). This is done to 1) ease hardening of firmware code, and 2) to ensure that even the decoded life cycle state vector inside the life cycle controller still has a redundant encoding. |
LC_CTRL.MAIN.FSM.SPARSE | The main state FSM is sparsely encoded. |
LC_CTRL.KMAC.FSM.SPARSE | The KMAC interface FSM is sparsely encoded. |
LC_CTRL.MAIN.FSM.LOCAL_ESC | Upon local escalation due to an invalid state encoding of the life cycle state vector or an invalid KMAC interface FSM state, the main state FSM moves to the InvalidSt state which behaves like a virtual scrap state. |
LC_CTRL.MAIN.FSM.GLOBAL_ESC | Upon global escalation (triggered by the alert escalation receivers), the main state FSM moves to the EscalateSt state which behaves like a virtual scrap state. |
LC_CTRL.MAIN.CTRL_FLOW.CONSISTENCY | The control flow of the main FSM is constructed so that the FSM only progresses linearly in one direction. There are no transition arcs that loop back to previous FSM states. |
LC_CTRL.INTERSIG.MUBI | Life cycle control signals are multibit encoded. |
LC_CTRL.TOKEN_VALID.CTRL.MUBI | The token valid signals coming from OTP are MUBI encoded. |
LC_CTRL.TOKEN.DIGEST | Life cycle transition tokens are hashed with cSHAKE128, using a custom 'LC_CTRL' prefix. |
LC_CTRL.TOKEN_MUX.CTRL.REDUN | The life cycle transition token mux is broken into two halves that are steered with separately decoded and buffered MUBI valid signals (see also TOKEN_VALID.CTRL.MUBI). |
LC_CTRL.TOKEN_VALID.MUX.REDUN | The life cycle transition token valid mux is replicated twice. If a transition is initiated and the two mux index signals are inconsistent or if any of the two valid mux outputs is not set to valid, the transition will fail with a TRANSITION_ERROR. |
Registers
Summary | |||
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Name | Offset | Length | Description |
lc_ctrl.ALERT_TEST | 0x0 | 4 | Alert Test Register |
lc_ctrl.STATUS | 0x4 | 4 | life cycle status register. Note that all errors are terminal and require a reset cycle. |
lc_ctrl.CLAIM_TRANSITION_IF | 0x8 | 4 | Hardware mutex to claim exclusive access to the transition interface. |
lc_ctrl.TRANSITION_REGWEN | 0xc | 4 | Register write enable for all transition interface registers. |
lc_ctrl.TRANSITION_CMD | 0x10 | 4 | Command register for state transition requests. |
lc_ctrl.TRANSITION_CTRL | 0x14 | 4 | Control register for state transition requests. |
lc_ctrl.TRANSITION_TOKEN_0 | 0x18 | 4 | 128bit token for conditional transitions.
Make sure to set this to 0 for unconditional transitions.
Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via |
lc_ctrl.TRANSITION_TOKEN_1 | 0x1c | 4 | 128bit token for conditional transitions.
Make sure to set this to 0 for unconditional transitions.
Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via |
lc_ctrl.TRANSITION_TOKEN_2 | 0x20 | 4 | 128bit token for conditional transitions.
Make sure to set this to 0 for unconditional transitions.
Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via |
lc_ctrl.TRANSITION_TOKEN_3 | 0x24 | 4 | 128bit token for conditional transitions.
Make sure to set this to 0 for unconditional transitions.
Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via |
lc_ctrl.TRANSITION_TARGET | 0x28 | 4 | This register exposes the decoded life cycle state. |
lc_ctrl.OTP_VENDOR_TEST_CTRL | 0x2c | 4 | Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will be gated to zero before sending them to the OTP macro wrapper - even if this register is programmed to a non-zero value. |
lc_ctrl.OTP_VENDOR_TEST_STATUS | 0x30 | 4 | Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will read as zero. |
lc_ctrl.LC_STATE | 0x34 | 4 | This register exposes the decoded life cycle state. |
lc_ctrl.LC_TRANSITION_CNT | 0x38 | 4 | This register exposes the state of the decoded life cycle transition counter. |
lc_ctrl.LC_ID_STATE | 0x3c | 4 | This register exposes the id state of the device. |
lc_ctrl.HW_REV | 0x40 | 4 | This register holds the 32bit hardware revision, which is split into two 16bit fields holding the CHIP_GEN and CHIP_REV numbers. |
lc_ctrl.DEVICE_ID_0 | 0x44 | 4 | This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. |
lc_ctrl.DEVICE_ID_1 | 0x48 | 4 | This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. |
lc_ctrl.DEVICE_ID_2 | 0x4c | 4 | This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. |
lc_ctrl.DEVICE_ID_3 | 0x50 | 4 | This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. |
lc_ctrl.DEVICE_ID_4 | 0x54 | 4 | This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. |
lc_ctrl.DEVICE_ID_5 | 0x58 | 4 | This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. |
lc_ctrl.DEVICE_ID_6 | 0x5c | 4 | This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. |
lc_ctrl.DEVICE_ID_7 | 0x60 | 4 | This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. |
lc_ctrl.MANUF_STATE_0 | 0x64 | 4 | This is a 256bit field used for keeping track of the manufacturing state. |
lc_ctrl.MANUF_STATE_1 | 0x68 | 4 | This is a 256bit field used for keeping track of the manufacturing state. |
lc_ctrl.MANUF_STATE_2 | 0x6c | 4 | This is a 256bit field used for keeping track of the manufacturing state. |
lc_ctrl.MANUF_STATE_3 | 0x70 | 4 | This is a 256bit field used for keeping track of the manufacturing state. |
lc_ctrl.MANUF_STATE_4 | 0x74 | 4 | This is a 256bit field used for keeping track of the manufacturing state. |
lc_ctrl.MANUF_STATE_5 | 0x78 | 4 | This is a 256bit field used for keeping track of the manufacturing state. |
lc_ctrl.MANUF_STATE_6 | 0x7c | 4 | This is a 256bit field used for keeping track of the manufacturing state. |
lc_ctrl.MANUF_STATE_7 | 0x80 | 4 | This is a 256bit field used for keeping track of the manufacturing state. |
lc_ctrl.ALERT_TEST @ 0x0
Alert Test Register Reset default = 0x0, mask 0x7
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | fatal_prog_error | Write 1 to trigger one alert event of this kind. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | fatal_state_error | Write 1 to trigger one alert event of this kind. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | wo | 0x0 | fatal_bus_integ_error | Write 1 to trigger one alert event of this kind. |
lc_ctrl.STATUS @ 0x4
life cycle status register. Note that all errors are terminal and require a reset cycle. Reset default = 0x0, mask 0x7ff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | x | INITIALIZED | This bit is set to 1 if the life cycle controller has successfully initialized and the
state exposed in | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | x | READY | This bit is set to 1 if the life cycle controller has successfully initialized and is ready to accept a life cycle transition command. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | ro | x | TRANSITION_SUCCESSFUL | This bit is set to 1 if the last life cycle transition request was successful.
Note that each transition attempt increments the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | ro | x | TRANSITION_COUNT_ERROR | This bit is set to 1 if the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | ro | x | TRANSITION_ERROR | This bit is set to 1 if the last transition command requested an invalid state transition
(e.g. DEV -> RAW). Note that each transition attempt increments the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | ro | x | TOKEN_ERROR | This bit is set to 1 if the token supplied for a conditional transition was invalid.
Note that each transition attempt increments the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | ro | x | FLASH_RMA_ERROR | This bit is set to 1 if flash failed to correctly respond to an RMA request.
Note that each transition attempt increments the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | ro | x | OTP_ERROR | This bit is set to 1 if an error occurred during an OTP programming operation. This error will move the life cycle state automatically to POST_TRANSITION and raise a fatal_prog_error alert. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | ro | x | STATE_ERROR | This bit is set to 1 if either the controller FSM state or the life cycle state is invalid or has been corrupted as part of a tampering attempt. This error will move the life cycle state automatically to INVALID and raise a fatal_state_error alert. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | ro | x | BUS_INTEG_ERROR | This bit is set to 1 if a fatal bus integrity fault is detected. This error triggers a fatal_bus_integ_error alert. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | ro | x | OTP_PARTITION_ERROR | This bit is set to 1 if the life cycle partition in OTP is in error state. This bit is intended for production testing during the RAW life cycle state, where the OTP control and status registers are not accessible. This error does not trigger an alert in the life cycle controller. |
lc_ctrl.CLAIM_TRANSITION_IF @ 0x8
Hardware mutex to claim exclusive access to the transition interface. Reset default = 0x69, mask 0xff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:0 | rw | 0x69 | MUTEX | In order to have exclusive access to the transition interface, SW must first claim the associated
hardware mutex by writing kMultiBitBool8True to this register.
If the register reads back kMultiBitBool8True, the mutex claim has been successful, and |
lc_ctrl.TRANSITION_REGWEN @ 0xc
Register write enable for all transition interface registers. Reset default = 0x0, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x0 | TRANSITION_REGWEN | This bit is hardware-managed and only readable by software.
By default, this bit is set to 0 by hardware.
Once SW has claimed the |
lc_ctrl.TRANSITION_CMD @ 0x10
Command register for state transition requests. Reset default = 0x0, mask 0x1
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | r0w1c | x | START | Writing a 1 to this register initiates the life cycle state transition to the state
specified in |
lc_ctrl.TRANSITION_CTRL @ 0x14
Control register for state transition requests. Reset default = 0x0, mask 0x1
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1s | x | EXT_CLOCK_EN | When set to 1, the OTP clock will be switched to an externally supplied clock right away when the device is in a non-PROD life cycle state. The clock mux will remain switched until the next system reset. |
lc_ctrl.TRANSITION_TOKEN_0 @ 0x18
128bit token for conditional transitions.
Make sure to set this to 0 for unconditional transitions.
Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | x | TRANSITION_TOKEN_0 |
lc_ctrl.TRANSITION_TOKEN_1 @ 0x1c
128bit token for conditional transitions.
Make sure to set this to 0 for unconditional transitions.
Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | x | TRANSITION_TOKEN_1 | For WORD1 |
lc_ctrl.TRANSITION_TOKEN_2 @ 0x20
128bit token for conditional transitions.
Make sure to set this to 0 for unconditional transitions.
Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | x | TRANSITION_TOKEN_2 | For WORD2 |
lc_ctrl.TRANSITION_TOKEN_3 @ 0x24
128bit token for conditional transitions.
Make sure to set this to 0 for unconditional transitions.
Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | x | TRANSITION_TOKEN_3 | For WORD3 |
lc_ctrl.TRANSITION_TARGET @ 0x28
This register exposes the decoded life cycle state. Reset default = 0x0, mask 0x3fffffff
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:0 | rw | x | STATE | This field encodes the target life cycle state in a redundant enum format. The 5bit state enum is repeated 6x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, val, val, val, val]. Note that this register is shared with the life cycle TAP interface.
In order to have exclusive access to this register, SW must first claim the associated
hardware mutex via
Other values are reserved. |
lc_ctrl.OTP_VENDOR_TEST_CTRL @ 0x2c
Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will be gated to zero before sending them to the OTP macro wrapper - even if this register is programmed to a non-zero value. Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | x | OTP_VENDOR_TEST_CTRL |
lc_ctrl.OTP_VENDOR_TEST_STATUS @ 0x30
Test/vendor-specific settings for the OTP macro wrapper. These values are only active during RAW, TEST_* and RMA life cycle states. In all other states, these values will read as zero. Reset default = 0x0, mask 0xffffffff
Register enable = TRANSITION_REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | OTP_VENDOR_TEST_STATUS |
lc_ctrl.LC_STATE @ 0x34
This register exposes the decoded life cycle state. Reset default = 0x0, mask 0x3fffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29:0 | ro | x | STATE | This field exposes the decoded life cycle state in a redundant enum format. The 5bit state enum is repeated 6x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, val, val, val, val].
Other values are reserved. |
lc_ctrl.LC_TRANSITION_CNT @ 0x38
This register exposes the state of the decoded life cycle transition counter. Reset default = 0x0, mask 0x1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | ro | x | CNT | Number of total life cycle state transition attempts.
The life cycle controller allows up to 24 transition attempts.
If this counter is equal to 24, the If the counter state is invalid, or the life cycle controller is in the post-transition state, the counter will have the value 31 (i.e., all counter bits will be set). |
lc_ctrl.LC_ID_STATE @ 0x3c
This register exposes the id state of the device. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | STATE | This field exposes the id state in redundant enum format. The 2bit id state enum is repeated 16x so that it fills the entire 32bit register. The encoding is straightforward replication: [val, val, ... val]."
Other values are reserved. |
lc_ctrl.HW_REV @ 0x40
This register holds the 32bit hardware revision, which is split into two 16bit fields holding the CHIP_GEN and CHIP_REV numbers. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | CHIP_REV | Chip revision number. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | CHIP_GEN | Chip generation number. |
lc_ctrl.DEVICE_ID_0 @ 0x44
This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | DEVICE_ID_0 |
lc_ctrl.DEVICE_ID_1 @ 0x48
This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | DEVICE_ID_1 | For WORD1 |
lc_ctrl.DEVICE_ID_2 @ 0x4c
This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | DEVICE_ID_2 | For WORD2 |
lc_ctrl.DEVICE_ID_3 @ 0x50
This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | DEVICE_ID_3 | For WORD3 |
lc_ctrl.DEVICE_ID_4 @ 0x54
This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | DEVICE_ID_4 | For WORD4 |
lc_ctrl.DEVICE_ID_5 @ 0x58
This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | DEVICE_ID_5 | For WORD5 |
lc_ctrl.DEVICE_ID_6 @ 0x5c
This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | DEVICE_ID_6 | For WORD6 |
lc_ctrl.DEVICE_ID_7 @ 0x60
This is the 256bit DEVICE_ID value that is stored in the HW_CFG partition in OTP. If this register reads all-one, the HW_CFG partition has not been initialized yet or is in error state. If this register reads all-zero, this is indicative that the value has not been programmed to OTP yet. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | DEVICE_ID_7 | For WORD7 |
lc_ctrl.MANUF_STATE_0 @ 0x64
This is a 256bit field used for keeping track of the manufacturing state. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MANUF_STATE_0 |
lc_ctrl.MANUF_STATE_1 @ 0x68
This is a 256bit field used for keeping track of the manufacturing state. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MANUF_STATE_1 | For WORD1 |
lc_ctrl.MANUF_STATE_2 @ 0x6c
This is a 256bit field used for keeping track of the manufacturing state. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MANUF_STATE_2 | For WORD2 |
lc_ctrl.MANUF_STATE_3 @ 0x70
This is a 256bit field used for keeping track of the manufacturing state. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MANUF_STATE_3 | For WORD3 |
lc_ctrl.MANUF_STATE_4 @ 0x74
This is a 256bit field used for keeping track of the manufacturing state. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MANUF_STATE_4 | For WORD4 |
lc_ctrl.MANUF_STATE_5 @ 0x78
This is a 256bit field used for keeping track of the manufacturing state. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MANUF_STATE_5 | For WORD5 |
lc_ctrl.MANUF_STATE_6 @ 0x7c
This is a 256bit field used for keeping track of the manufacturing state. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MANUF_STATE_6 | For WORD6 |
lc_ctrl.MANUF_STATE_7 @ 0x80
This is a 256bit field used for keeping track of the manufacturing state. Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MANUF_STATE_7 | For WORD7 |