Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module adc_ctrl has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: clk_aon_i
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
adcast_pkg::adc_astreq_rspreq1
wkup_reqlogicunireq1
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
match_doneEventADC match or measurement event done

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure IDDescription
ADC_CTRL.BUS.INTEGRITYEnd-to-end bus integrity scheme.

Registers

Summary

NameOffsetLengthDescription
adc_ctrl.INTR_STATE0x04Interrupt State Register
adc_ctrl.INTR_ENABLE0x44Interrupt Enable Register
adc_ctrl.INTR_TEST0x84Interrupt Test Register
adc_ctrl.ALERT_TEST0xc4Alert Test Register
adc_ctrl.adc_en_ctl0x104ADC enable control register
adc_ctrl.adc_pd_ctl0x144ADC PowerDown(PD) control register
adc_ctrl.adc_lp_sample_ctl0x184ADC Low-Power(LP) sample control register
adc_ctrl.adc_sample_ctl0x1c4ADC sample control register
adc_ctrl.adc_fsm_rst0x204ADC FSM reset control
adc_ctrl.adc_chn0_filter_ctl_00x244ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_10x284ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_20x2c4ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_30x304ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_40x344ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_50x384ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_60x3c4ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_70x404ADC channel0 filter range
adc_ctrl.adc_chn1_filter_ctl_00x444ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_10x484ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_20x4c4ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_30x504ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_40x544ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_50x584ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_60x5c4ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_70x604ADC channel1 filter range
adc_ctrl.adc_chn_val_00x644ADC value sampled on channel
adc_ctrl.adc_chn_val_10x684ADC value sampled on channel
adc_ctrl.adc_wakeup_ctl0x6c4Enable filter matches as wakeups
adc_ctrl.filter_status0x704Adc filter match status
adc_ctrl.adc_intr_ctl0x744Interrupt enable controls.
adc_ctrl.adc_intr_status0x784Debug cable internal status

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0match_doneADC match or measurement event done

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0match_doneEnable interrupt when INTR_STATE.match_done is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0match_doneWrite 1 to force INTR_STATE.match_done to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

adc_en_ctl

ADC enable control register

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0oneshot_modeOneshot mode does not care about the filter value. 1’b0: disable; 1’b1: enable
0rw0x0adc_enable1’b0: to power down ADC and ADC_CTRL FSM will enter the reset state; 1’b1: to power up ADC and ADC_CTRL FSM will start

adc_pd_ctl

ADC PowerDown(PD) control register

  • Offset: 0x14
  • Reset default: 0x64070
  • Reset mask: 0xfffffff1

Fields

BitsTypeResetNameDescription
31:8rw0x640wakeup_timeHow often FSM wakes up from ADC PD mode to take a sample, measured in always on clock cycles.
7:4rw0x7pwrup_timeADC power up time, measured in always on clock cycles. After power up time is reached, the ADC controller needs one additional cycle before an ADC channel is selected for access.
3:1Reserved
0rw0x0lp_mode1’b0: adc_pd is disabled, use adc_sample_ctl. 1’b1: adc_pd is enabled, use both adc_lp_sample_ctl & adc_sample_ctl

adc_lp_sample_ctl

ADC Low-Power(LP) sample control register

  • Offset: 0x18
  • Reset default: 0x4
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0rw0x4lp_sample_cntThe number of samples in low-power mode when the low-power mode is enabled. After the programmed number is met, ADC won’t be powered down any more. This value must be 1 or larger.

adc_sample_ctl

ADC sample control register

  • Offset: 0x1c
  • Reset default: 0x9b
  • Reset mask: 0xffff

Fields

BitsTypeResetNameDescription
31:16Reserved
15:0rw0x9bnp_sample_cntThe number of samples in normal-power mode to meet the debounce spec. Used after the low-power mode condition is met or in the normal power mode. This value must be 1 or larger.

adc_fsm_rst

ADC FSM reset control

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0rst_en1’b0: Normal functional mode. 1’b1: SW to reset all the FSMs and timers

adc_chn0_filter_ctl

ADC channel0 filter range

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

  • Reset default: 0x0
  • Reset mask: 0x8ffc1ffc

Instances

NameOffset
adc_chn0_filter_ctl_00x24
adc_chn0_filter_ctl_10x28
adc_chn0_filter_ctl_20x2c
adc_chn0_filter_ctl_30x30
adc_chn0_filter_ctl_40x34
adc_chn0_filter_ctl_50x38
adc_chn0_filter_ctl_60x3c
adc_chn0_filter_ctl_70x40

Fields

BitsTypeResetNameDescription
31rw0x0ENEnable for filter
30:28Reserved
27:18rw0x0max_v10-bit for chn0 filter max value
17:13Reserved
12rw0x0cond1-bit for the condition; 1’b0 means min<=ADC<=max, 1’b1 means ADC>max or ADC<min
11:2rw0x0min_v10-bit for chn0 filter min value
1:0Reserved

adc_chn1_filter_ctl

ADC channel1 filter range

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

  • Reset default: 0x0
  • Reset mask: 0x8ffc1ffc

Instances

NameOffset
adc_chn1_filter_ctl_00x44
adc_chn1_filter_ctl_10x48
adc_chn1_filter_ctl_20x4c
adc_chn1_filter_ctl_30x50
adc_chn1_filter_ctl_40x54
adc_chn1_filter_ctl_50x58
adc_chn1_filter_ctl_60x5c
adc_chn1_filter_ctl_70x60

Fields

BitsTypeResetNameDescription
31rw0x0ENEnable for filter
30:28Reserved
27:18rw0x0max_v10-bit for chn0 filter max value
17:13Reserved
12rw0x0cond1-bit for the condition; 1’b0 means min<=ADC<=max, 1’b1 means ADC>max or ADC<min
11:2rw0x0min_v10-bit for chn0 filter min value
1:0Reserved

adc_chn_val

ADC value sampled on channel

  • Reset default: 0x0
  • Reset mask: 0xfff0fff

Instances

NameOffset
adc_chn_val_00x64
adc_chn_val_10x68

Fields

BitsTypeResetNameDescription
31:28Reserved
27:18ro0x0adc_chn_value_intrADC value sampled on channel when the interrupt is raised(debug cable is attached or disconnected), each step is 2.148mV
17:16ro0x0adc_chn_value_intr_ext2-bit extension; RO 0
15:12Reserved
11:2ro0x0adc_chn_valueLatest ADC value sampled on channel. each step is 2.148mV
1:0ro0x0adc_chn_value_ext2-bit extension; RO 0

adc_wakeup_ctl

Enable filter matches as wakeups

  • Offset: 0x6c
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0rw0x0EN0: filter match wil not generate wakeupe; 1: filter match will generate wakeup

filter_status

Adc filter match status

Indicates whether a particular filter has matched on all channels.

  • Offset: 0x70
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0rw1c0x0COND0: filter condition is not met; 1: filter condition is met

adc_intr_ctl

Interrupt enable controls.

adc_ctrl sends out only 1 interrupt, so this register controls which internal sources are actually registered.

This register uses the same bit enumeration as ADC_INTR_STATUS

  • Offset: 0x74
  • Reset default: 0x0
  • Reset mask: 0x1ff

Fields

BitsTypeResetNameDescription
31:9Reserved
8:0rw0x0EN0: interrupt source is not enabled; 1: interrupt source is enabled

adc_intr_status

Debug cable internal status

  • Offset: 0x78
  • Reset default: 0x0
  • Reset mask: 0x1ff

Fields

BitsTypeResetNameDescription
31:9Reserved
8rw1c0x0oneshot0: oneshot sample is not done ; 1: oneshot sample is done
7:0rw1c0x0filter_match0: filter condition is not met; 1: filter condition is met