Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module adc_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
adc ast_pkg::adc_ast req_rsp req 1
wkup_req logic uni req 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
match_doneEvent

ADC match or measurement event done

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
ADC_CTRL.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
adc_ctrl.INTR_STATE 0x0 4

Interrupt State Register
adc_ctrl.INTR_ENABLE 0x4 4

Interrupt Enable Register
adc_ctrl.INTR_TEST 0x8 4

Interrupt Test Register
adc_ctrl.ALERT_TEST 0xc 4

Alert Test Register
adc_ctrl.adc_en_ctl 0x10 4

ADC enable control register
adc_ctrl.adc_pd_ctl 0x14 4

ADC PowerDown(PD) control register
adc_ctrl.adc_lp_sample_ctl 0x18 4

ADC Low-Power(LP) sample control register
adc_ctrl.adc_sample_ctl 0x1c 4

ADC sample control register
adc_ctrl.adc_fsm_rst 0x20 4

ADC FSM reset control
adc_ctrl.adc_chn0_filter_ctl_0 0x24 4

ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_1 0x28 4

ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_2 0x2c 4

ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_3 0x30 4

ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_4 0x34 4

ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_5 0x38 4

ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_6 0x3c 4

ADC channel0 filter range
adc_ctrl.adc_chn0_filter_ctl_7 0x40 4

ADC channel0 filter range
adc_ctrl.adc_chn1_filter_ctl_0 0x44 4

ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_1 0x48 4

ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_2 0x4c 4

ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_3 0x50 4

ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_4 0x54 4

ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_5 0x58 4

ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_6 0x5c 4

ADC channel1 filter range
adc_ctrl.adc_chn1_filter_ctl_7 0x60 4

ADC channel1 filter range
adc_ctrl.adc_chn_val_0 0x64 4

ADC value sampled on channel
adc_ctrl.adc_chn_val_1 0x68 4

ADC value sampled on channel
adc_ctrl.adc_wakeup_ctl 0x6c 4

Enable filter matches as wakeups
adc_ctrl.filter_status 0x70 4

Adc filter match status
adc_ctrl.adc_intr_ctl 0x74 4

Interrupt enable controls.
adc_ctrl.adc_intr_status 0x78 4

Debug cable internal status
adc_ctrl.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x1
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  match_done
BitsTypeResetNameDescription
0rw1c0x0match_done

ADC match or measurement event done


adc_ctrl.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x1
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  match_done
BitsTypeResetNameDescription
0rw0x0match_done

Enable interrupt when INTR_STATE.match_done is set.


adc_ctrl.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x1
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  match_done
BitsTypeResetNameDescription
0wo0x0match_done

Write 1 to force INTR_STATE.match_done to 1.


adc_ctrl.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


adc_ctrl.adc_en_ctl @ 0x10

ADC enable control register

Reset default = 0x0, mask 0x3
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  oneshot_mode adc_enable
BitsTypeResetNameDescription
0rw0x0adc_enable

1'b0: to power down ADC and ADC_CTRL FSM will enter the reset state; 1'b1: to power up ADC and ADC_CTRL FSM will start

1rw0x0oneshot_mode

Oneshot mode does not care about the filter value. 1'b0: disable; 1'b1: enable


adc_ctrl.adc_pd_ctl @ 0x14

ADC PowerDown(PD) control register

Reset default = 0x64060, mask 0xfffffff1
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wakeup_time...
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...wakeup_time pwrup_time   lp_mode
BitsTypeResetNameDescription
0rw0x0lp_mode

1'b0: adc_pd is disabled, use adc_sample_ctl. 1'b1: adc_pd is enabled, use both adc_lp_sample_ctl & adc_sample_ctl

3:1Reserved
7:4rw0x6pwrup_time

ADC power up time, measured in always on clock cycles. After power up time is reached, the ADC controller needs one additional cycle before an ADC channel is selected for access.

31:8rw0x640wakeup_time

How often FSM wakes up from ADC PD mode to take a sample, measured in always on clock cycles.


adc_ctrl.adc_lp_sample_ctl @ 0x18

ADC Low-Power(LP) sample control register

Reset default = 0x4, mask 0xff
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  lp_sample_cnt
BitsTypeResetNameDescription
7:0rw0x4lp_sample_cnt

The number of samples in low-power mode when the low-power mode is enabled. After the programmed number is met, ADC won't be powered down any more. This value must be 1 or larger.


adc_ctrl.adc_sample_ctl @ 0x1c

ADC sample control register

Reset default = 0x9b, mask 0xffff
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np_sample_cnt
BitsTypeResetNameDescription
15:0rw0x9bnp_sample_cnt

The number of samples in normal-power mode to meet the debounce spec. Used after the low-power mode condition is met or in the normal power mode. This value must be 1 or larger.


adc_ctrl.adc_fsm_rst @ 0x20

ADC FSM reset control

Reset default = 0x0, mask 0x1
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  rst_en
BitsTypeResetNameDescription
0rw0x0rst_en

1'b0: Normal functional mode. 1'b1: SW to reset all the FSMs and timers


adc_ctrl.adc_chn0_filter_ctl_0 @ 0x24

ADC channel0 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_0   max_v_0  
1514131211109876543210
  cond_0 min_v_0  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_0

10-bit for chn0 filter min value

12rw0x0cond_0

1-bit for the condition; 1'b0 means min<=ADC<=max, 1'b1 means ADC>max or ADC<min

17:13Reserved
27:18rw0x0max_v_0

10-bit for chn0 filter max value

30:28Reserved
31rw0x0EN_0

Enable for filter


adc_ctrl.adc_chn0_filter_ctl_1 @ 0x28

ADC channel0 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_1   max_v_1  
1514131211109876543210
  cond_1 min_v_1  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_1

For ADC_CTRL1

12rw0x0cond_1

For ADC_CTRL1

17:13Reserved
27:18rw0x0max_v_1

For ADC_CTRL1

30:28Reserved
31rw0x0EN_1

For ADC_CTRL1


adc_ctrl.adc_chn0_filter_ctl_2 @ 0x2c

ADC channel0 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_2   max_v_2  
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  cond_2 min_v_2  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_2

For ADC_CTRL2

12rw0x0cond_2

For ADC_CTRL2

17:13Reserved
27:18rw0x0max_v_2

For ADC_CTRL2

30:28Reserved
31rw0x0EN_2

For ADC_CTRL2


adc_ctrl.adc_chn0_filter_ctl_3 @ 0x30

ADC channel0 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_3   max_v_3  
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  cond_3 min_v_3  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_3

For ADC_CTRL3

12rw0x0cond_3

For ADC_CTRL3

17:13Reserved
27:18rw0x0max_v_3

For ADC_CTRL3

30:28Reserved
31rw0x0EN_3

For ADC_CTRL3


adc_ctrl.adc_chn0_filter_ctl_4 @ 0x34

ADC channel0 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_4   max_v_4  
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  cond_4 min_v_4  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_4

For ADC_CTRL4

12rw0x0cond_4

For ADC_CTRL4

17:13Reserved
27:18rw0x0max_v_4

For ADC_CTRL4

30:28Reserved
31rw0x0EN_4

For ADC_CTRL4


adc_ctrl.adc_chn0_filter_ctl_5 @ 0x38

ADC channel0 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_5   max_v_5  
1514131211109876543210
  cond_5 min_v_5  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_5

For ADC_CTRL5

12rw0x0cond_5

For ADC_CTRL5

17:13Reserved
27:18rw0x0max_v_5

For ADC_CTRL5

30:28Reserved
31rw0x0EN_5

For ADC_CTRL5


adc_ctrl.adc_chn0_filter_ctl_6 @ 0x3c

ADC channel0 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_6   max_v_6  
1514131211109876543210
  cond_6 min_v_6  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_6

For ADC_CTRL6

12rw0x0cond_6

For ADC_CTRL6

17:13Reserved
27:18rw0x0max_v_6

For ADC_CTRL6

30:28Reserved
31rw0x0EN_6

For ADC_CTRL6


adc_ctrl.adc_chn0_filter_ctl_7 @ 0x40

ADC channel0 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_7   max_v_7  
1514131211109876543210
  cond_7 min_v_7  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_7

For ADC_CTRL7

12rw0x0cond_7

For ADC_CTRL7

17:13Reserved
27:18rw0x0max_v_7

For ADC_CTRL7

30:28Reserved
31rw0x0EN_7

For ADC_CTRL7


adc_ctrl.adc_chn1_filter_ctl_0 @ 0x44

ADC channel1 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_0   max_v_0  
1514131211109876543210
  cond_0 min_v_0  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_0

10-bit for chn0 filter min value

12rw0x0cond_0

1-bit for the condition; 1'b0 means min<=ADC<=max, 1'b1 means ADC>max or ADC<min

17:13Reserved
27:18rw0x0max_v_0

10-bit for chn0 filter max value

30:28Reserved
31rw0x0EN_0

Enable for filter


adc_ctrl.adc_chn1_filter_ctl_1 @ 0x48

ADC channel1 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

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EN_1   max_v_1  
1514131211109876543210
  cond_1 min_v_1  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_1

For ADC_CTRL1

12rw0x0cond_1

For ADC_CTRL1

17:13Reserved
27:18rw0x0max_v_1

For ADC_CTRL1

30:28Reserved
31rw0x0EN_1

For ADC_CTRL1


adc_ctrl.adc_chn1_filter_ctl_2 @ 0x4c

ADC channel1 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

31302928272625242322212019181716
EN_2   max_v_2  
1514131211109876543210
  cond_2 min_v_2  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_2

For ADC_CTRL2

12rw0x0cond_2

For ADC_CTRL2

17:13Reserved
27:18rw0x0max_v_2

For ADC_CTRL2

30:28Reserved
31rw0x0EN_2

For ADC_CTRL2


adc_ctrl.adc_chn1_filter_ctl_3 @ 0x50

ADC channel1 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

31302928272625242322212019181716
EN_3   max_v_3  
1514131211109876543210
  cond_3 min_v_3  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_3

For ADC_CTRL3

12rw0x0cond_3

For ADC_CTRL3

17:13Reserved
27:18rw0x0max_v_3

For ADC_CTRL3

30:28Reserved
31rw0x0EN_3

For ADC_CTRL3


adc_ctrl.adc_chn1_filter_ctl_4 @ 0x54

ADC channel1 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

31302928272625242322212019181716
EN_4   max_v_4  
1514131211109876543210
  cond_4 min_v_4  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_4

For ADC_CTRL4

12rw0x0cond_4

For ADC_CTRL4

17:13Reserved
27:18rw0x0max_v_4

For ADC_CTRL4

30:28Reserved
31rw0x0EN_4

For ADC_CTRL4


adc_ctrl.adc_chn1_filter_ctl_5 @ 0x58

ADC channel1 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

31302928272625242322212019181716
EN_5   max_v_5  
1514131211109876543210
  cond_5 min_v_5  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_5

For ADC_CTRL5

12rw0x0cond_5

For ADC_CTRL5

17:13Reserved
27:18rw0x0max_v_5

For ADC_CTRL5

30:28Reserved
31rw0x0EN_5

For ADC_CTRL5


adc_ctrl.adc_chn1_filter_ctl_6 @ 0x5c

ADC channel1 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

31302928272625242322212019181716
EN_6   max_v_6  
1514131211109876543210
  cond_6 min_v_6  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_6

For ADC_CTRL6

12rw0x0cond_6

For ADC_CTRL6

17:13Reserved
27:18rw0x0max_v_6

For ADC_CTRL6

30:28Reserved
31rw0x0EN_6

For ADC_CTRL6


adc_ctrl.adc_chn1_filter_ctl_7 @ 0x60

ADC channel1 filter range

Reset default = 0x0, mask 0x8ffc1ffc

Up to 8 filters can be configured per channel and each filter has an associated [min, max] range. The condition bit then defines whether the sample values of that channel need to lie within the range or outside to create a match. The filter range bounds can be configured with a granularity of 2.148mV.

31302928272625242322212019181716
EN_7   max_v_7  
1514131211109876543210
  cond_7 min_v_7  
BitsTypeResetNameDescription
1:0Reserved
11:2rw0x0min_v_7

For ADC_CTRL7

12rw0x0cond_7

For ADC_CTRL7

17:13Reserved
27:18rw0x0max_v_7

For ADC_CTRL7

30:28Reserved
31rw0x0EN_7

For ADC_CTRL7


adc_ctrl.adc_chn_val_0 @ 0x64

ADC value sampled on channel

Reset default = 0x0, mask 0xfff0fff
31302928272625242322212019181716
  adc_chn_value_intr_0 adc_chn_value_intr_ext_0
1514131211109876543210
  adc_chn_value_0 adc_chn_value_ext_0
BitsTypeResetNameDescription
1:0ro0x0adc_chn_value_ext_0

2-bit extension; RO 0

11:2ro0x0adc_chn_value_0

Latest ADC value sampled on channel. each step is 2.148mV

15:12Reserved
17:16ro0x0adc_chn_value_intr_ext_0

2-bit extension; RO 0

27:18ro0x0adc_chn_value_intr_0

ADC value sampled on channel when the interrupt is raised(debug cable is attached or disconnected), each step is 2.148mV


adc_ctrl.adc_chn_val_1 @ 0x68

ADC value sampled on channel

Reset default = 0x0, mask 0xfff0fff
31302928272625242322212019181716
  adc_chn_value_intr_1 adc_chn_value_intr_ext_1
1514131211109876543210
  adc_chn_value_1 adc_chn_value_ext_1
BitsTypeResetNameDescription
1:0ro0x0adc_chn_value_ext_1

For ADC_CTRL1

11:2ro0x0adc_chn_value_1

For ADC_CTRL1

15:12Reserved
17:16ro0x0adc_chn_value_intr_ext_1

For ADC_CTRL1

27:18ro0x0adc_chn_value_intr_1

For ADC_CTRL1


adc_ctrl.adc_wakeup_ctl @ 0x6c

Enable filter matches as wakeups

Reset default = 0x0, mask 0xff
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  EN
BitsTypeResetNameDescription
7:0rw0x0EN

0: filter match wil not generate wakeupe; 1: filter match will generate wakeup


adc_ctrl.filter_status @ 0x70

Adc filter match status

Reset default = 0x0, mask 0xff

Indicates whether a particular filter has matched on all channels.

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  COND
BitsTypeResetNameDescription
7:0rw1c0x0COND

0: filter condition is not met; 1: filter condition is met


adc_ctrl.adc_intr_ctl @ 0x74

Interrupt enable controls.

Reset default = 0x0, mask 0x1ff

adc_ctrl sends out only 1 interrupt, so this register controls which internal sources are actually registered.

This register uses the same bit enumeration as ADC_INTR_STATUS

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  EN
BitsTypeResetNameDescription
8:0rw0x0EN

0: interrupt source is not enabled; 1: interrupt source is enabled


adc_ctrl.adc_intr_status @ 0x78

Debug cable internal status

Reset default = 0x0, mask 0x1ff
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  oneshot filter_match
BitsTypeResetNameDescription
7:0rw1c0x0filter_match

0: filter condition is not met; 1: filter condition is met

8rw1c0x0oneshot

0: oneshot sample is not done ; 1: oneshot sample is done