host mode interrupt: raised when the FMT FIFO depth is less than the low threshold.

host mode interrupt: raised if the RX FIFO is greater than the high threshold.

host mode interrupt: raised if the FMT FIFO has overflowed.

host mode interrupt: raised if the RX FIFO has overflowed.

host mode interrupt: raised if there is no ACK in response to an address or data write

host mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).

host mode interrupt: raised if the SDA line goes low when host is trying to assert high

host mode interrupt: raised if target stretches the clock beyond the allowed timeout period

host mode interrupt: raised if the target does not assert a constant value of SDA during transmission.

host and target mode interrupt. In host mode, raised if the host issues a repated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.

target mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.

target mode interrupt: raised if TX FIFO has overflowed.

target mode interrupt: raised if ACQ FIFO becomes full. This is a level status interrupt.

target mode interrupt: raised if STOP is received without a preceding NACK during an external host read.

target mode interrupt: raised if the host stops sending the clock during an ongoing transaction.

Enable interrupt when INTR_STATE.fmt_threshold is set.

Enable interrupt when INTR_STATE.rx_threshold is set.

Enable interrupt when INTR_STATE.fmt_overflow is set.

Enable interrupt when INTR_STATE.rx_overflow is set.

Enable interrupt when INTR_STATE.nak is set.

Enable interrupt when INTR_STATE.scl_interference is set.

Enable interrupt when INTR_STATE.sda_interference is set.

Enable interrupt when INTR_STATE.stretch_timeout is set.

Enable interrupt when INTR_STATE.sda_unstable is set.

Enable interrupt when INTR_STATE.cmd_complete is set.

Enable interrupt when INTR_STATE.tx_stretch is set.

Enable interrupt when INTR_STATE.tx_overflow is set.

Enable interrupt when INTR_STATE.acq_full is set.

Enable interrupt when INTR_STATE.unexp_stop is set.

Enable interrupt when INTR_STATE.host_timeout is set.

Write 1 to force INTR_STATE.fmt_threshold to 1.

Write 1 to force INTR_STATE.rx_threshold to 1.

Write 1 to force INTR_STATE.fmt_overflow to 1.

Write 1 to force INTR_STATE.rx_overflow to 1.

Write 1 to force INTR_STATE.nak to 1.

Write 1 to force INTR_STATE.scl_interference to 1.

Write 1 to force INTR_STATE.sda_interference to 1.

Write 1 to force INTR_STATE.stretch_timeout to 1.

Write 1 to force INTR_STATE.sda_unstable to 1.

Write 1 to force INTR_STATE.cmd_complete to 1.

Write 1 to force INTR_STATE.tx_stretch to 1.

Write 1 to force INTR_STATE.tx_overflow to 1.

Write 1 to force INTR_STATE.acq_full to 1.

Write 1 to force INTR_STATE.unexp_stop to 1.

Write 1 to force INTR_STATE.host_timeout to 1.

Write 1 to trigger one alert event of this kind.

Enable Host I2C functionality

Enable Target I2C functionality

Enable I2C line loopback test If line loopback is enabled, the internal design sees ACQ and RX data as "1"

FMT FIFO is full

RX FIFO is full

FMT FIFO is empty

Host functionality is idle. No Host transaction is in progress

Target functionality is idle. No Target transaction is in progress

RX FIFO is empty

TX FIFO is full

ACQ FIFO is full

TX FIFO is empty

ACQ FIFO is empty

Format Byte. Directly transmitted if no flags are set.

Issue a START condition before transmitting BYTE.

Issue a STOP condition after this operation

Read BYTE bytes from I2C. (256 if BYTE==0)

Do not NAK the last byte read, let the read operation continue

Do not signal an exception if the current byte is not ACK'd

RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0

FMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0

Trigger level for RX interrupts. If the FIFO depth exceeds this setting, it raises rx_threshold interrupt.

Other values are reserved.

Trigger level for FMT interrupts. If the FIFO depth falls below this setting, it raises fmt_threshold interrupt.

ACQ FIFO reset. Write 1 to the register resets it. Read returns 0

TX FIFO reset. Write 1 to the register resets it. Read returns 0

Current fill level of FMT fifo

Current fill level of TX fifo

Current fill level of RX fifo

Current fill level of ACQ fifo

Override the SDA and SCL TX signals.

Value for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z

Value for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z

Last 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.

Last 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31.

The actual time to hold SCL high in a given pulse

The actual time to hold SCL low between any two SCL pulses

The nominal rise time to anticipate for the bus (depends on capacitance)

The nominal fall time to anticipate for the bus (influences SDA hold times)

Actual setup time for repeated start signals

Actual hold time for start signals

Actual setup time for data (or ack) bits

Actual hold time for data (or ack) bits (Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)

Actual setup time for stop signals

Actual time between each STOP signal and the following START signal

Clock stretching timeout value (in units of input clock frequency)

Enable timeout feature

I2C target address number 0

I2C target mask number 0

I2C target address number 1

I2C target mask number 1

Address for accepted transaction or acquired byte

Host issued a START before transmitting ABYTE, a STOP or a RESTART after the preceeding ABYTE