Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module i2c has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: none

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
sdainout

Serial input data bit

sclinout

Serial input clock bit

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
fmt_thresholdEvent

host mode interrupt: raised when the FMT FIFO depth is less than the low threshold.

rx_thresholdEvent

host mode interrupt: raised if the RX FIFO is greater than the high threshold.

fmt_overflowEvent

host mode interrupt: raised if the FMT FIFO has overflowed.

rx_overflowEvent

host mode interrupt: raised if the RX FIFO has overflowed.

nakEvent

host mode interrupt: raised if there is no ACK in response to an address or data write

scl_interferenceEvent

host mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).

sda_interferenceEvent

host mode interrupt: raised if the SDA line goes low when host is trying to assert high

stretch_timeoutEvent

host mode interrupt: raised if target stretches the clock beyond the allowed timeout period

sda_unstableEvent

host mode interrupt: raised if the target does not assert a constant value of SDA during transmission.

cmd_completeEvent

host and target mode interrupt. In host mode, raised if the host issues a repated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.

tx_stretchStatus

target mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.

tx_overflowEvent

target mode interrupt: raised if TX FIFO has overflowed.

acq_fullStatus

target mode interrupt: raised if ACQ FIFO becomes full. This is a level status interrupt.

unexp_stopEvent

target mode interrupt: raised if STOP is received without a preceding NACK during an external host read.

host_timeoutEvent

target mode interrupt: raised if the host stops sending the clock during an ongoing transaction.

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
I2C.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
i2c.INTR_STATE 0x0 4

Interrupt State Register

i2c.INTR_ENABLE 0x4 4

Interrupt Enable Register

i2c.INTR_TEST 0x8 4

Interrupt Test Register

i2c.ALERT_TEST 0xc 4

Alert Test Register

i2c.CTRL 0x10 4

I2C control register (Functions TBD)

i2c.STATUS 0x14 4

I2C live status register

i2c.RDATA 0x18 4

I2C read data

i2c.FDATA 0x1c 4

I2C Format Data

i2c.FIFO_CTRL 0x20 4

I2C FIFO control register

i2c.FIFO_STATUS 0x24 4

I2C FIFO status register

i2c.OVRD 0x28 4

I2C override control register

i2c.VAL 0x2c 4

Oversampled RX values

i2c.TIMING0 0x30 4

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

i2c.TIMING1 0x34 4

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

i2c.TIMING2 0x38 4

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

i2c.TIMING3 0x3c 4

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

i2c.TIMING4 0x40 4

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

i2c.TIMEOUT_CTRL 0x44 4

I2C clock stretching timeout control

i2c.TARGET_ID 0x48 4

I2C target address and mask pairs

i2c.ACQDATA 0x4c 4

I2C target acquired data

i2c.TXDATA 0x50 4

I2C target transmit data

i2c.HOST_TIMEOUT_CTRL 0x54 4

I2C host clock generation timeout value (in units of input clock frequency)

i2c.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x7fff
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  host_timeout unexp_stop acq_full tx_overflow tx_stretch cmd_complete sda_unstable stretch_timeout sda_interference scl_interference nak rx_overflow fmt_overflow rx_threshold fmt_threshold
BitsTypeResetNameDescription
0rw1c0x0fmt_threshold

host mode interrupt: raised when the FMT FIFO depth is less than the low threshold.

1rw1c0x0rx_threshold

host mode interrupt: raised if the RX FIFO is greater than the high threshold.

2rw1c0x0fmt_overflow

host mode interrupt: raised if the FMT FIFO has overflowed.

3rw1c0x0rx_overflow

host mode interrupt: raised if the RX FIFO has overflowed.

4rw1c0x0nak

host mode interrupt: raised if there is no ACK in response to an address or data write

5rw1c0x0scl_interference

host mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).

6rw1c0x0sda_interference

host mode interrupt: raised if the SDA line goes low when host is trying to assert high

7rw1c0x0stretch_timeout

host mode interrupt: raised if target stretches the clock beyond the allowed timeout period

8rw1c0x0sda_unstable

host mode interrupt: raised if the target does not assert a constant value of SDA during transmission.

9rw1c0x0cmd_complete

host and target mode interrupt. In host mode, raised if the host issues a repated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.

10ro0x0tx_stretch

target mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.

11rw1c0x0tx_overflow

target mode interrupt: raised if TX FIFO has overflowed.

12ro0x0acq_full

target mode interrupt: raised if ACQ FIFO becomes full. This is a level status interrupt.

13rw1c0x0unexp_stop

target mode interrupt: raised if STOP is received without a preceding NACK during an external host read.

14rw1c0x0host_timeout

target mode interrupt: raised if the host stops sending the clock during an ongoing transaction.


i2c.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x7fff
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  host_timeout unexp_stop acq_full tx_overflow tx_stretch cmd_complete sda_unstable stretch_timeout sda_interference scl_interference nak rx_overflow fmt_overflow rx_threshold fmt_threshold
BitsTypeResetNameDescription
0rw0x0fmt_threshold

Enable interrupt when INTR_STATE.fmt_threshold is set.

1rw0x0rx_threshold

Enable interrupt when INTR_STATE.rx_threshold is set.

2rw0x0fmt_overflow

Enable interrupt when INTR_STATE.fmt_overflow is set.

3rw0x0rx_overflow

Enable interrupt when INTR_STATE.rx_overflow is set.

4rw0x0nak

Enable interrupt when INTR_STATE.nak is set.

5rw0x0scl_interference

Enable interrupt when INTR_STATE.scl_interference is set.

6rw0x0sda_interference

Enable interrupt when INTR_STATE.sda_interference is set.

7rw0x0stretch_timeout

Enable interrupt when INTR_STATE.stretch_timeout is set.

8rw0x0sda_unstable

Enable interrupt when INTR_STATE.sda_unstable is set.

9rw0x0cmd_complete

Enable interrupt when INTR_STATE.cmd_complete is set.

10rw0x0tx_stretch

Enable interrupt when INTR_STATE.tx_stretch is set.

11rw0x0tx_overflow

Enable interrupt when INTR_STATE.tx_overflow is set.

12rw0x0acq_full

Enable interrupt when INTR_STATE.acq_full is set.

13rw0x0unexp_stop

Enable interrupt when INTR_STATE.unexp_stop is set.

14rw0x0host_timeout

Enable interrupt when INTR_STATE.host_timeout is set.


i2c.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x7fff
31302928272625242322212019181716
 
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  host_timeout unexp_stop acq_full tx_overflow tx_stretch cmd_complete sda_unstable stretch_timeout sda_interference scl_interference nak rx_overflow fmt_overflow rx_threshold fmt_threshold
BitsTypeResetNameDescription
0wo0x0fmt_threshold

Write 1 to force INTR_STATE.fmt_threshold to 1.

1wo0x0rx_threshold

Write 1 to force INTR_STATE.rx_threshold to 1.

2wo0x0fmt_overflow

Write 1 to force INTR_STATE.fmt_overflow to 1.

3wo0x0rx_overflow

Write 1 to force INTR_STATE.rx_overflow to 1.

4wo0x0nak

Write 1 to force INTR_STATE.nak to 1.

5wo0x0scl_interference

Write 1 to force INTR_STATE.scl_interference to 1.

6wo0x0sda_interference

Write 1 to force INTR_STATE.sda_interference to 1.

7wo0x0stretch_timeout

Write 1 to force INTR_STATE.stretch_timeout to 1.

8wo0x0sda_unstable

Write 1 to force INTR_STATE.sda_unstable to 1.

9wo0x0cmd_complete

Write 1 to force INTR_STATE.cmd_complete to 1.

10wo0x0tx_stretch

Write 1 to force INTR_STATE.tx_stretch to 1.

11wo0x0tx_overflow

Write 1 to force INTR_STATE.tx_overflow to 1.

12wo0x0acq_full

Write 1 to force INTR_STATE.acq_full to 1.

13wo0x0unexp_stop

Write 1 to force INTR_STATE.unexp_stop to 1.

14wo0x0host_timeout

Write 1 to force INTR_STATE.host_timeout to 1.


i2c.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


i2c.CTRL @ 0x10

I2C control register (Functions TBD)

Reset default = 0x0, mask 0x7
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  LLPBK ENABLETARGET ENABLEHOST
BitsTypeResetNameDescription
0rw0x0ENABLEHOST

Enable Host I2C functionality

1rw0x0ENABLETARGET

Enable Target I2C functionality

2rw0x0LLPBK

Enable I2C line loopback test If line loopback is enabled, the internal design sees ACQ and RX data as "1"


i2c.STATUS @ 0x14

I2C live status register

Reset default = 0x33c, mask 0x3ff
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  ACQEMPTY TXEMPTY ACQFULL TXFULL RXEMPTY TARGETIDLE HOSTIDLE FMTEMPTY RXFULL FMTFULL
BitsTypeResetNameDescription
0roxFMTFULL

FMT FIFO is full

1roxRXFULL

RX FIFO is full

2ro0x1FMTEMPTY

FMT FIFO is empty

3ro0x1HOSTIDLE

Host functionality is idle. No Host transaction is in progress

4ro0x1TARGETIDLE

Target functionality is idle. No Target transaction is in progress

5ro0x1RXEMPTY

RX FIFO is empty

6roxTXFULL

TX FIFO is full

7roxACQFULL

ACQ FIFO is full

8ro0x1TXEMPTY

TX FIFO is empty

9ro0x1ACQEMPTY

ACQ FIFO is empty


i2c.RDATA @ 0x18

I2C read data

Reset default = 0x0, mask 0xff
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  RDATA
BitsTypeResetNameDescription
7:0roxRDATA

i2c.FDATA @ 0x1c

I2C Format Data

Reset default = 0x0, mask 0x1fff
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  NAKOK RCONT READ STOP START FBYTE
BitsTypeResetNameDescription
7:0wo0x0FBYTE

Format Byte. Directly transmitted if no flags are set.

8wo0x0START

Issue a START condition before transmitting BYTE.

9wo0x0STOP

Issue a STOP condition after this operation

10wo0x0READ

Read BYTE bytes from I2C. (256 if BYTE==0)

11wo0x0RCONT

Do not NAK the last byte read, let the read operation continue

12wo0x0NAKOK

Do not signal an exception if the current byte is not ACK'd


i2c.FIFO_CTRL @ 0x20

I2C FIFO control register

Reset default = 0x0, mask 0x1ff
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  TXRST ACQRST FMTILVL RXILVL FMTRST RXRST
BitsTypeResetNameDescription
0wo0x0RXRST

RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0

1wo0x0FMTRST

FMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0

4:2rw0x0RXILVL

Trigger level for RX interrupts. If the FIFO depth exceeds this setting, it raises rx_threshold interrupt.

0x0rxlvl1

1 character

0x1rxlvl4

4 characters

0x2rxlvl8

8 characters

0x3rxlvl16

16 characters

0x4rxlvl30

30 characters

Other values are reserved.

6:5rw0x0FMTILVL

Trigger level for FMT interrupts. If the FIFO depth falls below this setting, it raises fmt_threshold interrupt.

0x0fmtlvl1

1 character

0x1fmtlvl4

4 characters

0x2fmtlvl8

8 characters

0x3fmtlvl16

16 characters

7wo0x0ACQRST

ACQ FIFO reset. Write 1 to the register resets it. Read returns 0

8wo0x0TXRST

TX FIFO reset. Write 1 to the register resets it. Read returns 0


i2c.FIFO_STATUS @ 0x24

I2C FIFO status register

Reset default = 0x0, mask 0x7f7f7f7f
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  ACQLVL   RXLVL
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  TXLVL   FMTLVL
BitsTypeResetNameDescription
6:0roxFMTLVL

Current fill level of FMT fifo

7Reserved
14:8roxTXLVL

Current fill level of TX fifo

15Reserved
22:16roxRXLVL

Current fill level of RX fifo

23Reserved
30:24roxACQLVL

Current fill level of ACQ fifo


i2c.OVRD @ 0x28

I2C override control register

Reset default = 0x0, mask 0x7
31302928272625242322212019181716
 
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  SDAVAL SCLVAL TXOVRDEN
BitsTypeResetNameDescription
0rw0x0TXOVRDEN

Override the SDA and SCL TX signals.

1rw0x0SCLVAL

Value for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z

2rw0x0SDAVAL

Value for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z


i2c.VAL @ 0x2c

Oversampled RX values

Reset default = 0x0, mask 0xffffffff
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SDA_RX
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SCL_RX
BitsTypeResetNameDescription
15:0roxSCL_RX

Last 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.

31:16roxSDA_RX

Last 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31.


i2c.TIMING0 @ 0x30

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

Reset default = 0x0, mask 0xffffffff
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TLOW
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THIGH
BitsTypeResetNameDescription
15:0rw0x0THIGH

The actual time to hold SCL high in a given pulse

31:16rw0x0TLOW

The actual time to hold SCL low between any two SCL pulses


i2c.TIMING1 @ 0x34

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
T_F
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T_R
BitsTypeResetNameDescription
15:0rw0x0T_R

The nominal rise time to anticipate for the bus (depends on capacitance)

31:16rw0x0T_F

The nominal fall time to anticipate for the bus (influences SDA hold times)


i2c.TIMING2 @ 0x38

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
THD_STA
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TSU_STA
BitsTypeResetNameDescription
15:0rw0x0TSU_STA

Actual setup time for repeated start signals

31:16rw0x0THD_STA

Actual hold time for start signals


i2c.TIMING3 @ 0x3c

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
THD_DAT
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TSU_DAT
BitsTypeResetNameDescription
15:0rw0x0TSU_DAT

Actual setup time for data (or ack) bits

31:16rw0x0THD_DAT

Actual hold time for data (or ack) bits (Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)


i2c.TIMING4 @ 0x40

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

Reset default = 0x0, mask 0xffffffff
31302928272625242322212019181716
T_BUF
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TSU_STO
BitsTypeResetNameDescription
15:0rw0x0TSU_STO

Actual setup time for stop signals

31:16rw0x0T_BUF

Actual time between each STOP signal and the following START signal


i2c.TIMEOUT_CTRL @ 0x44

I2C clock stretching timeout control

Reset default = 0x0, mask 0xffffffff
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EN VAL...
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...VAL
BitsTypeResetNameDescription
30:0rw0x0VAL

Clock stretching timeout value (in units of input clock frequency)

31rw0x0EN

Enable timeout feature


i2c.TARGET_ID @ 0x48

I2C target address and mask pairs

Reset default = 0x0, mask 0xfffffff
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  MASK1 ADDRESS1...
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...ADDRESS1 MASK0 ADDRESS0
BitsTypeResetNameDescription
6:0rw0x0ADDRESS0

I2C target address number 0

13:7rw0x0MASK0

I2C target mask number 0

20:14rw0x0ADDRESS1

I2C target address number 1

27:21rw0x0MASK1

I2C target mask number 1


i2c.ACQDATA @ 0x4c

I2C target acquired data

Reset default = 0x0, mask 0x3ff
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  SIGNAL ABYTE
BitsTypeResetNameDescription
7:0roxABYTE

Address for accepted transaction or acquired byte

9:8roxSIGNAL

Host issued a START before transmitting ABYTE, a STOP or a RESTART after the preceeding ABYTE


i2c.TXDATA @ 0x50

I2C target transmit data

Reset default = 0x0, mask 0xff
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  TXDATA
BitsTypeResetNameDescription
7:0wo0x0TXDATA

I2C host clock generation timeout value (in units of input clock frequency)

Reset default = 0x0, mask 0xffffffff
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HOST_TIMEOUT_CTRL...
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...HOST_TIMEOUT_CTRL
BitsTypeResetNameDescription
31:0rw0x0HOST_TIMEOUT_CTRL