Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module i2c has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO

Pin nameDirectionDescription
sdainoutSerial input data bit
sclinoutSerial input clock bit

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
fmt_thresholdEventhost mode interrupt: raised when the FMT FIFO depth is less than the low threshold.
rx_thresholdEventhost mode interrupt: raised if the RX FIFO is greater than the high threshold.
fmt_overflowEventhost mode interrupt: raised if the FMT FIFO has overflowed.
rx_overflowEventhost mode interrupt: raised if the RX FIFO has overflowed.
nakEventhost mode interrupt: raised if there is no ACK in response to an address or data write
scl_interferenceEventhost mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).
sda_interferenceEventhost mode interrupt: raised if the SDA line goes low when host is trying to assert high
stretch_timeoutEventhost mode interrupt: raised if target stretches the clock beyond the allowed timeout period
sda_unstableEventhost mode interrupt: raised if the target does not assert a constant value of SDA during transmission.
cmd_completeEventhost and target mode interrupt. In host mode, raised if the host issues a repeated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.
tx_stretchStatustarget mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.
tx_overflowEventtarget mode interrupt: raised if TX FIFO has overflowed.
acq_fullStatustarget mode interrupt: raised if ACQ FIFO becomes full. This is a level status interrupt.
unexp_stopEventtarget mode interrupt: raised if STOP is received without a preceding NACK during an external host read.
host_timeoutEventtarget mode interrupt: raised if the host stops sending the clock during an ongoing transaction.

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure IDDescription
I2C.BUS.INTEGRITYEnd-to-end bus integrity scheme.

Registers

Summary

NameOffsetLengthDescription
i2c.INTR_STATE0x04Interrupt State Register
i2c.INTR_ENABLE0x44Interrupt Enable Register
i2c.INTR_TEST0x84Interrupt Test Register
i2c.ALERT_TEST0xc4Alert Test Register
i2c.CTRL0x104I2C Control Register
i2c.STATUS0x144I2C Live Status Register
i2c.RDATA0x184I2C Read Data
i2c.FDATA0x1c4I2C Format Data
i2c.FIFO_CTRL0x204I2C FIFO control register
i2c.FIFO_STATUS0x244I2C FIFO status register
i2c.OVRD0x284I2C Override Control Register
i2c.VAL0x2c4Oversampled RX values
i2c.TIMING00x304Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
i2c.TIMING10x344Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
i2c.TIMING20x384Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification).
i2c.TIMING30x3c4Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
i2c.TIMING40x404Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification).
i2c.TIMEOUT_CTRL0x444I2C clock stretching timeout control
i2c.TARGET_ID0x484I2C target address and mask pairs
i2c.ACQDATA0x4c4I2C target acquired data
i2c.TXDATA0x504I2C target transmit data
i2c.HOST_TIMEOUT_CTRL0x544I2C host clock generation timeout value (in units of input clock frequency)

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x7fff

Fields

BitsTypeResetNameDescription
31:15Reserved
14rw1c0x0host_timeouttarget mode interrupt: raised if the host stops sending the clock during an ongoing transaction.
13rw1c0x0unexp_stoptarget mode interrupt: raised if STOP is received without a preceding NACK during an external host read.
12ro0x0acq_fulltarget mode interrupt: raised if ACQ FIFO becomes full. This is a level status interrupt.
11rw1c0x0tx_overflowtarget mode interrupt: raised if TX FIFO has overflowed.
10ro0x0tx_stretchtarget mode interrupt: raised if the target is stretching clocks for a read command. This is a level status interrupt.
9rw1c0x0cmd_completehost and target mode interrupt. In host mode, raised if the host issues a repeated START or terminates the transaction by issuing STOP. In target mode, raised if the external host issues a STOP or repeated START.
8rw1c0x0sda_unstablehost mode interrupt: raised if the target does not assert a constant value of SDA during transmission.
7rw1c0x0stretch_timeouthost mode interrupt: raised if target stretches the clock beyond the allowed timeout period
6rw1c0x0sda_interferencehost mode interrupt: raised if the SDA line goes low when host is trying to assert high
5rw1c0x0scl_interferencehost mode interrupt: raised if the SCL line drops early (not supported without clock synchronization).
4rw1c0x0nakhost mode interrupt: raised if there is no ACK in response to an address or data write
3rw1c0x0rx_overflowhost mode interrupt: raised if the RX FIFO has overflowed.
2rw1c0x0fmt_overflowhost mode interrupt: raised if the FMT FIFO has overflowed.
1rw1c0x0rx_thresholdhost mode interrupt: raised if the RX FIFO is greater than the high threshold.
0rw1c0x0fmt_thresholdhost mode interrupt: raised when the FMT FIFO depth is less than the low threshold.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x7fff

Fields

BitsTypeResetNameDescription
31:15Reserved
14rw0x0host_timeoutEnable interrupt when INTR_STATE.host_timeout is set.
13rw0x0unexp_stopEnable interrupt when INTR_STATE.unexp_stop is set.
12rw0x0acq_fullEnable interrupt when INTR_STATE.acq_full is set.
11rw0x0tx_overflowEnable interrupt when INTR_STATE.tx_overflow is set.
10rw0x0tx_stretchEnable interrupt when INTR_STATE.tx_stretch is set.
9rw0x0cmd_completeEnable interrupt when INTR_STATE.cmd_complete is set.
8rw0x0sda_unstableEnable interrupt when INTR_STATE.sda_unstable is set.
7rw0x0stretch_timeoutEnable interrupt when INTR_STATE.stretch_timeout is set.
6rw0x0sda_interferenceEnable interrupt when INTR_STATE.sda_interference is set.
5rw0x0scl_interferenceEnable interrupt when INTR_STATE.scl_interference is set.
4rw0x0nakEnable interrupt when INTR_STATE.nak is set.
3rw0x0rx_overflowEnable interrupt when INTR_STATE.rx_overflow is set.
2rw0x0fmt_overflowEnable interrupt when INTR_STATE.fmt_overflow is set.
1rw0x0rx_thresholdEnable interrupt when INTR_STATE.rx_threshold is set.
0rw0x0fmt_thresholdEnable interrupt when INTR_STATE.fmt_threshold is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x7fff

Fields

BitsTypeResetNameDescription
31:15Reserved
14wo0x0host_timeoutWrite 1 to force INTR_STATE.host_timeout to 1.
13wo0x0unexp_stopWrite 1 to force INTR_STATE.unexp_stop to 1.
12wo0x0acq_fullWrite 1 to force INTR_STATE.acq_full to 1.
11wo0x0tx_overflowWrite 1 to force INTR_STATE.tx_overflow to 1.
10wo0x0tx_stretchWrite 1 to force INTR_STATE.tx_stretch to 1.
9wo0x0cmd_completeWrite 1 to force INTR_STATE.cmd_complete to 1.
8wo0x0sda_unstableWrite 1 to force INTR_STATE.sda_unstable to 1.
7wo0x0stretch_timeoutWrite 1 to force INTR_STATE.stretch_timeout to 1.
6wo0x0sda_interferenceWrite 1 to force INTR_STATE.sda_interference to 1.
5wo0x0scl_interferenceWrite 1 to force INTR_STATE.scl_interference to 1.
4wo0x0nakWrite 1 to force INTR_STATE.nak to 1.
3wo0x0rx_overflowWrite 1 to force INTR_STATE.rx_overflow to 1.
2wo0x0fmt_overflowWrite 1 to force INTR_STATE.fmt_overflow to 1.
1wo0x0rx_thresholdWrite 1 to force INTR_STATE.rx_threshold to 1.
0wo0x0fmt_thresholdWrite 1 to force INTR_STATE.fmt_threshold to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

CTRL

I2C Control Register

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

BitsTypeResetNameDescription
31:3Reserved
2rw0x0LLPBKEnable I2C line loopback test If line loopback is enabled, the internal design sees ACQ and RX data as “1”
1rw0x0ENABLETARGETEnable Target I2C functionality
0rw0x0ENABLEHOSTEnable Host I2C functionality

STATUS

I2C Live Status Register

  • Offset: 0x14
  • Reset default: 0x33c
  • Reset mask: 0x3ff

Fields

BitsTypeResetNameDescription
31:10Reserved
9ro0x1ACQEMPTYACQ FIFO is empty
8ro0x1TXEMPTYTX FIFO is empty
7roxACQFULLACQ FIFO is full
6roxTXFULLTX FIFO is full
5ro0x1RXEMPTYRX FIFO is empty
4ro0x1TARGETIDLETarget functionality is idle. No Target transaction is in progress
3ro0x1HOSTIDLEHost functionality is idle. No Host transaction is in progress
2ro0x1FMTEMPTYFMT FIFO is empty
1roxRXFULLRX FIFO is full
0roxFMTFULLFMT FIFO is full

RDATA

I2C Read Data

  • Offset: 0x18
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0roxRDATA

FDATA

I2C Format Data

  • Offset: 0x1c
  • Reset default: 0x0
  • Reset mask: 0x1fff

Fields

BitsTypeResetNameDescription
31:13Reserved
12wo0x0NAKOKDo not signal an exception if the current byte is not ACK’d
11wo0x0RCONTDo not NACK the last byte read, let the read operation continue
10wo0x0READRead BYTE bytes from I2C. (256 if BYTE==0)
9wo0x0STOPIssue a STOP condition after this operation
8wo0x0STARTIssue a START condition before transmitting BYTE.
7:0wo0x0FBYTEFormat Byte. Directly transmitted if no flags are set.

FIFO_CTRL

I2C FIFO control register

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0x1ff

Fields

BitsTypeResetName
31:9Reserved
8wo0x0TXRST
7wo0x0ACQRST
6:5rw0x0FMTILVL
4:2rw0x0RXILVL
1wo0x0FMTRST
0wo0x0RXRST

FIFO_CTRL . TXRST

TX FIFO reset. Write 1 to the register resets it. Read returns 0

FIFO_CTRL . ACQRST

ACQ FIFO reset. Write 1 to the register resets it. Read returns 0

FIFO_CTRL . FMTILVL

Trigger level for FMT interrupts. If the FIFO depth falls below this setting, it raises fmt_threshold interrupt.

ValueNameDescription
0x0fmtlvl11 character
0x1fmtlvl44 characters
0x2fmtlvl88 characters
0x3fmtlvl1616 characters

FIFO_CTRL . RXILVL

Trigger level for RX interrupts. If the FIFO depth exceeds this setting, it raises rx_threshold interrupt.

ValueNameDescription
0x0rxlvl11 character
0x1rxlvl44 characters
0x2rxlvl88 characters
0x3rxlvl1616 characters
0x4rxlvl3030 characters

Other values are reserved.

FIFO_CTRL . FMTRST

FMT fifo reset. Write 1 to the register resets FMT_FIFO. Read returns 0

FIFO_CTRL . RXRST

RX fifo reset. Write 1 to the register resets RX_FIFO. Read returns 0

FIFO_STATUS

I2C FIFO status register

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0x7f7f7f7f

Fields

BitsTypeResetNameDescription
31Reserved
30:24roxACQLVLCurrent fill level of ACQ fifo
23Reserved
22:16roxRXLVLCurrent fill level of RX fifo
15Reserved
14:8roxTXLVLCurrent fill level of TX fifo
7Reserved
6:0roxFMTLVLCurrent fill level of FMT fifo

OVRD

I2C Override Control Register

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0x7

Fields

BitsTypeResetNameDescription
31:3Reserved
2rw0x0SDAVALValue for SDA Override. Set to 0 to drive TX Low, and set to 1 for high-Z
1rw0x0SCLVALValue for SCL Override. Set to 0 to drive TX Low, and set to 1 for high-Z
0rw0x0TXOVRDENOverride the SDA and SCL TX signals.

VAL

Oversampled RX values

  • Offset: 0x2c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16roxSDA_RXLast 16 oversampled values of SDA. Most recent bit is bit 16, oldest 31.
15:0roxSCL_RXLast 16 oversampled values of SCL. Most recent bit is bit 0, oldest 15.

TIMING0

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period. These must be greater than 2 in order for the change in SCL to propagate to the input of the FSM so that acknowledgements are detected correctly.

  • Offset: 0x30
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16rw0x0TLOWThe actual time to hold SCL low between any two SCL pulses
15:0rw0x0THIGHThe actual time to hold SCL high in a given pulse: in host mode, when there is no stretching this value is 3 cycles longer as tracked in issue #18962

TIMING1

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

  • Offset: 0x34
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16rw0x0T_FThe nominal fall time to anticipate for the bus (influences SDA hold times): this is currently counted twice in host mode as tracked in issue #18958
15:0rw0x0T_RThe nominal rise time to anticipate for the bus (depends on capacitance)

TIMING2

Detailed I2C Timings (directly corresponding to table 10 in the I2C Specification). All values are expressed in units of the input clock period.

  • Offset: 0x38
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16rw0x0THD_STAActual hold time for start signals
15:0rw0x0TSU_STAActual setup time for repeated start signals

TIMING3

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

  • Offset: 0x3c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16rw0x0THD_DATActual hold time for data (or ack) bits (Note, where required, the parameters TVD_DAT is taken to be THD_DAT+T_F)
15:0rw0x0TSU_DATActual setup time for data (or ack) bits

TIMING4

Detailed I2C Timings (directly corresponding to table 10, in the I2C Specification). All values are expressed in units of the input clock period.

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16rw0x0T_BUFActual time between each STOP signal and the following START signal
15:0rw0x0TSU_STOActual setup time for stop signals

TIMEOUT_CTRL

I2C clock stretching timeout control

  • Offset: 0x44
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31rw0x0ENEnable timeout feature
30:0rw0x0VALClock stretching timeout value (in units of input clock frequency)

TARGET_ID

I2C target address and mask pairs

  • Offset: 0x48
  • Reset default: 0x0
  • Reset mask: 0xfffffff

Fields

BitsTypeResetNameDescription
31:28Reserved
27:21rw0x0MASK1I2C target mask number 1
20:14rw0x0ADDRESS1I2C target address number 1
13:7rw0x0MASK0I2C target mask number 0
6:0rw0x0ADDRESS0I2C target address number 0

ACQDATA

I2C target acquired data

  • Offset: 0x4c
  • Reset default: 0x0
  • Reset mask: 0x3ff

Fields

BitsTypeResetName
31:10Reserved
9:8roxSIGNAL
7:0roxABYTE

ACQDATA . SIGNAL

Host issued a START before transmitting ABYTE, a STOP or a RESTART after the preceeding ABYTE

ValueNameDescription
0x0NONEABYTE contains ordinary data byte as received
0x1STARTABYTE contains the 8-bit I2C address (R/W in lsb)
0x2STOPABYTE contains junk
0x3RESTARTABYTE contains junk, START with address will follow

ACQDATA . ABYTE

Address for accepted transaction or acquired byte

TXDATA

I2C target transmit data

  • Offset: 0x50
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7:0wo0x0TXDATA

HOST_TIMEOUT_CTRL

I2C host clock generation timeout value (in units of input clock frequency)

  • Offset: 0x54
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0HOST_TIMEOUT_CTRL