Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module otbn has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: clk_edn_i, clk_otp_i
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
otbn_otp_keyotp_ctrl_pkg::otbn_otp_keyreq_rspreq1
edn_rndedn_pkg::ednreq_rspreq1
edn_urndedn_pkg::ednreq_rspreq1
idleprim_mubi_pkg::mubi4unireq1
ram_cfgprim_ram_1p_pkg::ram_1p_cfgunircv1
lc_escalate_enlc_ctrl_pkg::lc_txunircv1
lc_rma_reqlc_ctrl_pkg::lc_txunircv1
lc_rma_acklc_ctrl_pkg::lc_txunireq1
keymgr_keykeymgr_pkg::otbn_key_requnircv1
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
doneEventOTBN has completed the operation.

Security Alerts

Alert NameDescription
fatalA fatal error. Fatal alerts are non-recoverable and will be asserted until a hard reset.
recovA recoverable error. Just sent once (as the processor stops).

Security Countermeasures

Countermeasure IDDescription
OTBN.MEM.SCRAMBLEBoth the imem and dmem are scrambled by using prim_ram_1p_scr.
OTBN.DATA.MEM.INTEGRITYDmem is protected with ECC integrity. This is carried through to OTBN’s register file.
OTBN.INSTRUCTION.MEM.INTEGRITYImem is protected with ECC integrity. This is carried through into OTBN’s execute stage.
OTBN.BUS.INTEGRITYEnd-to-end bus integrity scheme.
OTBN.CONTROLLER.FSM.GLOBAL_ESCThe controller FSM moves to a terminal error state upon global escalation.
OTBN.CONTROLLER.FSM.LOCAL_ESCThe controller FSM moves to a terminal error state upon local escalation. Can be triggered by CONTROLLER.FSM.SPARSE, SCRAMBLE_CTRL.FSM.SPARSE, and START_STOP_CTRL.FSM.SPARSE.
OTBN.CONTROLLER.FSM.SPARSEThe controller FSM uses a sparse state encoding.
OTBN.SCRAMBLE.KEY.SIDELOADThe scrambling key is sideloaded from OTP and thus unreadable by SW.
OTBN.SCRAMBLE_CTRL.FSM.LOCAL_ESCThe scramble control FSM moves to a terminal error state upon local escalation. Can be triggered by SCRAMBLE_CTRL.FSM.SPARSE.
OTBN.SCRAMBLE_CTRL.FSM.SPARSEThe scramble control FSM uses a sparse state encoding.
OTBN.START_STOP_CTRL.FSM.GLOBAL_ESCThe start-stop control FSM moves to a terminal error state upon global escalation.
OTBN.START_STOP_CTRL.FSM.LOCAL_ESCThe start-stop control FSM moves to a terminal error state upon local escalation. Can be triggered by START_STOP_CTRL.FSM.SPARSE.
OTBN.START_STOP_CTRL.FSM.SPARSEThe start-stop control FSM uses a sparse state encoding.
OTBN.DATA_REG_SW.SCABlanking of bignum data paths when unused by the executing instruction.
OTBN.CTRL.REDUNCheck pre-decoded control matches separately decoded control from main decoder. This includes control signals used for blanking, pushing/popping the call stack, controlling loop and branch/jump instructions, as well as the actual branch target.
OTBN.PC.CTRL_FLOW.REDUNCheck prefetch stage PC and execute stage PC match. The prefetch stage and execute stage store their PC’s separately and have separate increment calculations.
OTBN.RND.BUS.CONSISTENCYComparison on successive bus values received over the EDN RND interface.
OTBN.RND.RNG.DIGESTChecking that the random numbers received over the EDN RND interface have not been generated from entropy that failed the FIPS health checks in the entropy source.
OTBN.RF_BASE.DATA_REG_SW.INTEGRITYRegister file is protected with ECC integrity.
OTBN.RF_BASE.DATA_REG_SW.GLITCH_DETECTThis countermeasure checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes.
OTBN.STACK_WR_PTR.CTR.REDUNThe write pointer of the stack (used for calls and loops) is redundant. If the two instances of the counter mismatch, an error is emitted.
OTBN.RF_BIGNUM.DATA_REG_SW.INTEGRITYRegister file is protected with ECC integrity.
OTBN.RF_BIGNUM.DATA_REG_SW.GLITCH_DETECTThis countermeasure checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes.
OTBN.LOOP_STACK.CTR.REDUNThe iteration counter of each entry in the loop step uses cross counts via prim_count.
OTBN.LOOP_STACK.ADDR.INTEGRITYLoop start and end address on the loop stack are protected with ECC integrity.
OTBN.CALL_STACK.ADDR.INTEGRITYCall stack entries are protected with ECC integrity.
OTBN.START_STOP_CTRL.STATE.CONSISTENCYThe secure wipe handshake between otbn_controller and otbn_start_stop_control uses a level-based req/ack interface. At the otbn_controller end, there is a check for unexpected acks. In otbn_start_stop_control, there is a check for secure wipe requests when we aren’t in a state that allows it, and also a check for if the request drops at an unexpected time.
OTBN.DATA.MEM.SEC_WIPERotate the scrambling key, effectively wiping the dmem. Initiated on command, upon fatal errors and before RMA entry.
OTBN.INSTRUCTION.MEM.SEC_WIPERotate the scrambling key, effectively wiping the imem. Initiated on command, upon fatal errors and before RMA entry.
OTBN.DATA_REG_SW.SEC_WIPESecurely wipe programmer visible OTBN register (GPRs, WDRs, CSRs, WSRs) state with random data. Initiated after reset, at the end of any OTBN operation, upon recoverable and fatal errors, and before RMA entry.
OTBN.WRITE.MEM.INTEGRITYA software visible checksum is calculated for all dmem and imem writes
OTBN.CTRL_FLOW.COUNTA software visible count of instructions executed
OTBN.CTRL_FLOW.SCAOTBN architecture does not have any data dependent timing behaviour
OTBN.DATA.MEM.SW_NOACCESSA portion of DMEM is invisible to CPU software
OTBN.KEY.SIDELOADKeys can be sideloaded without exposing them to the CPU
OTBN.TLUL_FIFO.CTR.REDUNThe TL-UL response FIFO pointers are implemented with duplicate counters.

Registers

Summary

NameOffsetLengthDescription
otbn.INTR_STATE0x04Interrupt State Register
otbn.INTR_ENABLE0x44Interrupt Enable Register
otbn.INTR_TEST0x84Interrupt Test Register
otbn.ALERT_TEST0xc4Alert Test Register
otbn.CMD0x104Command Register
otbn.CTRL0x144Control Register
otbn.STATUS0x184Status Register
otbn.ERR_BITS0x1c4Operation Result Register
otbn.FATAL_ALERT_CAUSE0x204Fatal Alert Cause Register
otbn.INSN_CNT0x244Instruction Count Register
otbn.LOAD_CHECKSUM0x284A 32-bit CRC checksum of data written to memory
otbn.IMEM0x40004096Instruction Memory Access
otbn.DMEM0x80003072Data Memory Access

INTR_STATE

Interrupt State Register

  • Offset: 0x0
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw1c0x0doneOTBN has completed the operation.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x4
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0doneEnable interrupt when INTR_STATE.done is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0doneWrite 1 to force INTR_STATE.done to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0xc
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0recovWrite 1 to trigger one alert event of this kind.
0wo0x0fatalWrite 1 to trigger one alert event of this kind.

CMD

Command Register

A command initiates an OTBN operation. While performing the operation, OTBN is busy; the STATUS register reflects that.

All operations signal their completion by raising the done interrupt; alternatively, software may poll the STATUS register.

Writes are ignored if OTBN is not idle. Unrecognized commands are ignored.

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetName
31:8Reserved
7:0wo0x0cmd

CMD . cmd

The operation to perform.

ValueNameDescription
0xd8EXECUTEStarts the execution of the program stored in the instruction memory, starting at address zero.
0xc3SEC_WIPE_DMEMSecurely removes all contents from the data memory.
0x1eSEC_WIPE_IMEMSecurely removes all contents from the instruction memory.

CTRL

Control Register

  • Offset: 0x14
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0x0software_errs_fatalControls the reaction to software errors. When set software errors produce fatal errors, rather than recoverable errors. Writes are ignored if OTBN is not idle.

STATUS

Status Register

  • Offset: 0x18
  • Reset default: 0x4
  • Reset mask: 0xff

Fields

BitsTypeResetName
31:8Reserved
7:0ro0x4status

STATUS . status

Indicates the current operational state OTBN is in.

All BUSY values represent an operation started by a write to the CMD register.

ValueNameDescription
0x00IDLEOTBN is idle: it is not performing any action.
0x01BUSY_EXECUTEOTBN is busy executing software.
0x02BUSY_SEC_WIPE_DMEMOTBN is busy securely wiping the data memory.
0x03BUSY_SEC_WIPE_IMEMOTBN is busy securely wiping the instruction memory.
0x04BUSY_SEC_WIPE_INTOTBN is busy securely wiping the internal state.
0xFFLOCKEDOTBN is locked as reaction to a fatal error, and must be reset to unlock it again. See also the section “Reaction to Fatal Errors”.

ERR_BITS

Operation Result Register

Describes the errors detected during an operation.

Refer to the “List of Errors” section for a detailed description of the errors.

The host CPU can clear this register when OTBN is not running, by writing any value. Write attempts while OTBN is running are ignored.

  • Offset: 0x1c
  • Reset default: 0x0
  • Reset mask: 0xff00ff

Fields

BitsTypeResetNameDescription
31:24Reserved
23rw0x0fatal_softwareA FATAL_SOFTWARE error was observed.
22rw0x0lifecycle_escalationA LIFECYCLE_ESCALATION error was observed.
21rw0x0illegal_bus_accessAn ILLEGAL_BUS_ACCESS error was observed.
20rw0x0bad_internal_stateA BAD_INTERNAL_STATE error was observed.
19rw0x0bus_intg_violationA BUS_INTG_VIOLATION error was observed.
18rw0x0reg_intg_violationA REG_INTG_VIOLATION error was observed.
17rw0x0dmem_intg_violationA DMEM_INTG_VIOLATION error was observed.
16rw0x0imem_intg_violationA IMEM_INTG_VIOLATION error was observed.
15:8Reserved
7rw0x0rnd_fips_chk_failAn RND_FIPS_CHK_FAIL error was observed.
6rw0x0rnd_rep_chk_failAn RND_REP_CHK_FAIL error was observed.
5rw0x0key_invalidA KEY_INVALID error was observed.
4rw0x0loopA LOOP error was observed.
3rw0x0illegal_insnAn ILLEGAL_INSN error was observed.
2rw0x0call_stackA CALL_STACK error was observed.
1rw0x0bad_insn_addrA BAD_INSN_ADDR error was observed.
0rw0x0bad_data_addrA BAD_DATA_ADDR error was observed.

FATAL_ALERT_CAUSE

Fatal Alert Cause Register

Describes any errors that led to a fatal alert. A fatal error puts OTBN in locked state; the value of this register does not change until OTBN is reset.

Refer to the “List of Errors” section for a detailed description of the errors.

  • Offset: 0x20
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetNameDescription
31:8Reserved
7ro0x0fatal_softwareA FATAL_SOFTWARE error was observed.
6ro0x0lifecycle_escalationA LIFECYCLE_ESCALATION error was observed.
5ro0x0illegal_bus_accessA ILLEGAL_BUS_ACCESS error was observed.
4ro0x0bad_internal_stateA BAD_INTERNAL_STATE error was observed.
3ro0x0bus_intg_violationA BUS_INTG_VIOLATION error was observed.
2ro0x0reg_intg_violationA REG_INTG_VIOLATION error was observed.
1ro0x0dmem_intg_violationA DMEM_INTG_VIOLATION error was observed.
0ro0x0imem_intg_violationA IMEM_INTG_VIOLATION error was observed.

INSN_CNT

Instruction Count Register

Returns the number of instructions executed in the current or last operation. The counter saturates at 2^32-1 and is reset to 0 at the start of a new operation.

Only the EXECUTE operation counts instructions; for all other operations this register remains at 0. Instructions triggering an error do not count towards the total.

Always reads as 0 if OTBN is locked.

The host CPU can clear this register when OTBN is not running, by writing any value. Write attempts while OTBN is running are ignored.

  • Offset: 0x24
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0insn_cntThe number of executed instructions.

LOAD_CHECKSUM

A 32-bit CRC checksum of data written to memory

See the “Memory Load Integrity” section of the manual for full details.

  • Offset: 0x28
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0checksumChecksum accumulator

IMEM

Instruction Memory Access

The instruction memory may only be accessed through this window while OTBN is idle.

If OTBN is busy or locked, read accesses return 0 and write accesses are ignored. If OTBN is busy, any access additionally triggers an ILLEGAL_BUS_ACCESS fatal error.

  • Word Aligned Offset Range: 0x4000to0x4ffc
  • Size (words): 1024
  • Access: rw
  • Byte writes are not supported.

DMEM

Data Memory Access

The data memory may only be accessed through this window while OTBN is idle.

If OTBN is busy or locked, read accesses return 0 and write accesses are ignored. If OTBN is busy, any access additionally triggers an ILLEGAL_BUS_ACCESS fatal error.

Note that DMEM is actually 4kiB in size, but only the first 3kiB of the memory is visible through this register interface.

  • Word Aligned Offset Range: 0x8000to0x8bfc
  • Size (words): 768
  • Access: rw
  • Byte writes are not supported.