OTBN has completed the operation.

A fatal error. Fatal alerts are non-recoverable and will be asserted until a hard reset.

A recoverable error. Just sent once (as the processor stops).

Both the imem and dmem are scrambled by using prim_ram_1p_scr.

Dmem is protected with ECC integrity. This is carried through to OTBN's register file.

Imem is protected with ECC integrity. This is carried through into OTBN's execute stage.

End-to-end bus integrity scheme.

The controller FSM moves to a terminal error state upon global escalation.

The controller FSM moves to a terminal error state upon local escalation. Can be triggered by CONTROLLER.FSM.SPARSE, SCRAMBLE_CTRL.FSM.SPARSE, and START_STOP_CTRL.FSM.SPARSE.

The controller FSM uses a sparse state encoding.

The scrambling key is sideloaded from OTP and thus unreadable by SW.

The scramble control FSM moves to a terminal error state upon local escalation. Can be triggered by SCRAMBLE_CTRL.FSM.SPARSE.

The scramble control FSM uses a sparse state encoding.

The start-stop control FSM moves to a terminal error state upon global escalation.

The start-stop control FSM moves to a terminal error state upon local escalation. Can be triggered by START_STOP_CTRL.FSM.SPARSE.

The start-stop control FSM uses a sparse state encoding.

Blanking of bignum data paths when unused by the executing instruction.

Check pre-decoded control matches separately decoded control from main decoder. This includes control signals used for blanking, pushing/popping the call stack, controlling loop and branch/jump instructions, as well as the actual branch target.

Check prefetch stage PC and execute stage PC match. The prefetch stage and execute stage store their PC's separately and have separate increment calculations.

Comparison on successive bus values received over the EDN RND interface.

Checking that the random numbers received over the EDN RND interface have not been generated from entropy that failed the FIPS health checks in the entropy source.

Register file is protected with ECC integrity.

This countermeasure checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes.

The write pointer of the stack (used for calls and loops) is redundant. If the two instances of the counter mismatch, an error is emitted.

Register file is protected with ECC integrity.

This countermeasure checks for spurious write-enable signals on the register file by monitoring the one-hot0 property of the individual write-enable strobes.

The iteration counter of each entry in the loop step uses cross counts via prim_count.

Loop start and end address on the loop stack are protected with ECC integrity.

Call stack entries are protected with ECC integrity.

The secure wipe handshake between otbn_controller and otbn_start_stop_control uses a level-based req/ack interface. At the otbn_controller end, there is a check for unexpected acks. In otbn_start_stop_control, there is a check for secure wipe requests when we aren't in a state that allows it, and also a check for if the request drops at an unexpected time.

Rotate the scrambling key, effectively wiping the dmem. Initiated on command, upon fatal errors and before RMA entry.

Rotate the scrambling key, effectively wiping the imem. Initiated on command, upon fatal errors and before RMA entry.

Securely wipe programmer visible OTBN register (GPRs, WDRs, CSRs, WSRs) state with random data. Initiated after reset, at the end of any OTBN operation, upon recoverable and fatal errors, and before RMA entry.

A software visible checksum is calculated for all dmem and imem writes

A software visible count of instructions executed

OTBN architecture does not have any data dependent timing behaviour

A portion of DMEM is invisible to CPU software

Keys can be sideloaded without exposing them to the CPU

The TL-UL response FIFO pointers are implemented with duplicate counters.