Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pinmux has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width	Description
lc_hw_debug_en	lc_ctrl_pkg::lc_tx	uni	rcv	1	Debug enable qualifier coming from life cycle controller, used for HW strap qualification.
lc_dft_en	lc_ctrl_pkg::lc_tx	uni	rcv	1	Test enable qualifier coming from life cycle controller, used for HW strap qualification.
lc_escalate_en	lc_ctrl_pkg::lc_tx	uni	rcv	1	Escalation enable signal coming from life cycle controller, used for invalidating the latched lc_hw_debug_en state inside the strap sampling logic.
lc_check_byp_en	lc_ctrl_pkg::lc_tx	uni	rcv	1	Check bypass enable signal coming from life cycle controller, used for invalidating the latched lc_hw_debug_en state inside the strap sampling logic. This signal is asserted whenever the life cycle controller performs a life cycle transition. Its main use is to skip any background checks inside the life cycle partition of the OTP controller while a life cycle transition is in progress.
pinmux_hw_debug_en	lc_ctrl_pkg::lc_tx	uni	req	1	This is the latched version of lc_hw_debug_en_i. We use it exclusively to gate the JTAG signals and TAP side of the RV_DM so that RV_DM can remain live during an NDM reset cycle.
lc_jtag	jtag_pkg::jtag	req_rsp	req	1	Qualified JTAG signals for life cycle controller TAP.
rv_jtag	jtag_pkg::jtag	req_rsp	req	1	Qualified JTAG signals for RISC-V processor TAP.
dft_jtag	jtag_pkg::jtag	req_rsp	req	1	Qualified JTAG signals for DFT TAP.
dft_strap_test	pinmux_pkg::dft_strap_test_req	uni	req	1	Sampled DFT strap values, going to the DFT TAP.
dft_hold_tap_sel	logic	uni	rcv	1	TAP selection hold indication, asserted by the DFT TAP during boundary scan.
sleep_en	logic	uni	rcv	1	Level signal that is asserted when the power manager enters sleep.
strap_en	logic	uni	rcv	1	This signal is pulsed high by the power manager after reset in order to sample the HW straps.
pin_wkup_req	logic	uni	req	1	Wakeup request from wakeup detectors, to the power manager, running on the AON clock.
usbdev_dppullup_en	logic	uni	rcv	1	Pullup enable signal coming from the USB IP.
usbdev_dnpullup_en	logic	uni	rcv	1	Pullup enable signal coming from the USB IP.
usb_dppullup_en	logic	uni	req	1	Pullup enable signal going to USB PHY, needs to be maintained in low-power mode.
usb_dnpullup_en	logic	uni	req	1	Pullup enable signal going to USB PHY, needs to be maintained in low-power mode.
usb_wkup_req	logic	uni	req	1	Wakeup request from USB wakeup detector, going to the power manager, running on the AON clock.
usbdev_suspend_req	logic	uni	rcv	1	Indicates whether USB is in suspended state, coming from the USB device.
usbdev_wake_ack	logic	uni	rcv	1	Acknowledges the USB wakeup request, coming from the USB device.
usbdev_bus_reset	logic	uni	req	1	Event signal that indicates what happened while monitoring.
usbdev_sense_lost	logic	uni	req	1	Event signal that indicates what happened while monitoring.
usbdev_wake_detect_active	logic	uni	req	1	State debug information.
tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts: none

Security Alerts:

Alert Name	Description
fatal_fault	This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure ID	Description
PINMUX.BUS.INTEGRITY	End-to-end bus integrity scheme.

Registers

Summary
Name	Offset	Length	Description
pinmux.ALERT_TEST	0x0	4	Alert Test Register
pinmux.MIO_PERIPH_INSEL_REGWEN_0	0x4	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_1	0x8	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_2	0xc	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_3	0x10	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_4	0x14	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_5	0x18	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_6	0x1c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_7	0x20	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_8	0x24	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_9	0x28	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_10	0x2c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_11	0x30	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_12	0x34	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_13	0x38	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_14	0x3c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_15	0x40	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_16	0x44	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_17	0x48	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_18	0x4c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_19	0x50	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_20	0x54	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_21	0x58	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_22	0x5c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_23	0x60	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_24	0x64	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_25	0x68	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_26	0x6c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_27	0x70	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_28	0x74	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_29	0x78	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_30	0x7c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_31	0x80	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_32	0x84	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_33	0x88	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_34	0x8c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_35	0x90	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_36	0x94	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_37	0x98	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_38	0x9c	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_39	0xa0	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_40	0xa4	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_41	0xa8	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_42	0xac	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_43	0xb0	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_44	0xb4	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_45	0xb8	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_46	0xbc	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_47	0xc0	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_48	0xc4	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_49	0xc8	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_50	0xcc	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_51	0xd0	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_52	0xd4	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_53	0xd8	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_54	0xdc	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_55	0xe0	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_REGWEN_56	0xe4	4	Register write enable for MIO peripheral input selects.
pinmux.MIO_PERIPH_INSEL_0	0xe8	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_1	0xec	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_2	0xf0	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_3	0xf4	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_4	0xf8	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_5	0xfc	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_6	0x100	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_7	0x104	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_8	0x108	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_9	0x10c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_10	0x110	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_11	0x114	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_12	0x118	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_13	0x11c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_14	0x120	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_15	0x124	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_16	0x128	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_17	0x12c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_18	0x130	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_19	0x134	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_20	0x138	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_21	0x13c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_22	0x140	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_23	0x144	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_24	0x148	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_25	0x14c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_26	0x150	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_27	0x154	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_28	0x158	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_29	0x15c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_30	0x160	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_31	0x164	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_32	0x168	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_33	0x16c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_34	0x170	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_35	0x174	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_36	0x178	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_37	0x17c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_38	0x180	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_39	0x184	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_40	0x188	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_41	0x18c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_42	0x190	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_43	0x194	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_44	0x198	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_45	0x19c	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_46	0x1a0	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_47	0x1a4	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_48	0x1a8	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_49	0x1ac	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_50	0x1b0	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_51	0x1b4	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_52	0x1b8	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_53	0x1bc	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_54	0x1c0	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_55	0x1c4	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_PERIPH_INSEL_56	0x1c8	4	For each peripheral input, this selects the muxable pad input.
pinmux.MIO_OUTSEL_REGWEN_0	0x1cc	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_1	0x1d0	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_2	0x1d4	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_3	0x1d8	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_4	0x1dc	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_5	0x1e0	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_6	0x1e4	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_7	0x1e8	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_8	0x1ec	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_9	0x1f0	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_10	0x1f4	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_11	0x1f8	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_12	0x1fc	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_13	0x200	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_14	0x204	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_15	0x208	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_16	0x20c	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_17	0x210	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_18	0x214	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_19	0x218	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_20	0x21c	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_21	0x220	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_22	0x224	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_23	0x228	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_24	0x22c	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_25	0x230	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_26	0x234	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_27	0x238	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_28	0x23c	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_29	0x240	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_30	0x244	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_31	0x248	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_32	0x24c	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_33	0x250	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_34	0x254	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_35	0x258	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_36	0x25c	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_37	0x260	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_38	0x264	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_39	0x268	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_40	0x26c	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_41	0x270	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_42	0x274	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_43	0x278	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_44	0x27c	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_45	0x280	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_REGWEN_46	0x284	4	Register write enable for MIO output selects.
pinmux.MIO_OUTSEL_0	0x288	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_1	0x28c	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_2	0x290	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_3	0x294	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_4	0x298	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_5	0x29c	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_6	0x2a0	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_7	0x2a4	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_8	0x2a8	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_9	0x2ac	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_10	0x2b0	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_11	0x2b4	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_12	0x2b8	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_13	0x2bc	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_14	0x2c0	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_15	0x2c4	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_16	0x2c8	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_17	0x2cc	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_18	0x2d0	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_19	0x2d4	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_20	0x2d8	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_21	0x2dc	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_22	0x2e0	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_23	0x2e4	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_24	0x2e8	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_25	0x2ec	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_26	0x2f0	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_27	0x2f4	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_28	0x2f8	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_29	0x2fc	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_30	0x300	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_31	0x304	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_32	0x308	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_33	0x30c	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_34	0x310	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_35	0x314	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_36	0x318	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_37	0x31c	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_38	0x320	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_39	0x324	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_40	0x328	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_41	0x32c	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_42	0x330	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_43	0x334	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_44	0x338	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_45	0x33c	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_OUTSEL_46	0x340	4	For each muxable pad, this selects the peripheral output.
pinmux.MIO_PAD_ATTR_REGWEN_0	0x344	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_1	0x348	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_2	0x34c	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_3	0x350	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_4	0x354	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_5	0x358	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_6	0x35c	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_7	0x360	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_8	0x364	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_9	0x368	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_10	0x36c	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_11	0x370	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_12	0x374	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_13	0x378	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_14	0x37c	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_15	0x380	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_16	0x384	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_17	0x388	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_18	0x38c	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_19	0x390	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_20	0x394	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_21	0x398	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_22	0x39c	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_23	0x3a0	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_24	0x3a4	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_25	0x3a8	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_26	0x3ac	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_27	0x3b0	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_28	0x3b4	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_29	0x3b8	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_30	0x3bc	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_31	0x3c0	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_32	0x3c4	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_33	0x3c8	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_34	0x3cc	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_35	0x3d0	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_36	0x3d4	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_37	0x3d8	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_38	0x3dc	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_39	0x3e0	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_40	0x3e4	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_41	0x3e8	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_42	0x3ec	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_43	0x3f0	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_44	0x3f4	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_45	0x3f8	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_REGWEN_46	0x3fc	4	Register write enable for MIO PAD attributes.
pinmux.MIO_PAD_ATTR_0	0x400	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_1	0x404	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_2	0x408	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_3	0x40c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_4	0x410	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_5	0x414	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_6	0x418	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_7	0x41c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_8	0x420	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_9	0x424	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_10	0x428	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_11	0x42c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_12	0x430	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_13	0x434	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_14	0x438	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_15	0x43c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_16	0x440	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_17	0x444	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_18	0x448	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_19	0x44c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_20	0x450	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_21	0x454	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_22	0x458	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_23	0x45c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_24	0x460	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_25	0x464	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_26	0x468	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_27	0x46c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_28	0x470	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_29	0x474	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_30	0x478	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_31	0x47c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_32	0x480	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_33	0x484	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_34	0x488	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_35	0x48c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_36	0x490	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_37	0x494	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_38	0x498	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_39	0x49c	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_40	0x4a0	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_41	0x4a4	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_42	0x4a8	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_43	0x4ac	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_44	0x4b0	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_45	0x4b4	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_ATTR_46	0x4b8	4	Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_REGWEN_0	0x4bc	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_1	0x4c0	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_2	0x4c4	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_3	0x4c8	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_4	0x4cc	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_5	0x4d0	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_6	0x4d4	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_7	0x4d8	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_8	0x4dc	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_9	0x4e0	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_10	0x4e4	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_11	0x4e8	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_12	0x4ec	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_13	0x4f0	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_14	0x4f4	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_REGWEN_15	0x4f8	4	Register write enable for DIO PAD attributes.
pinmux.DIO_PAD_ATTR_0	0x4fc	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_1	0x500	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_2	0x504	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_3	0x508	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_4	0x50c	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_5	0x510	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_6	0x514	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_7	0x518	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_8	0x51c	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_9	0x520	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_10	0x524	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_11	0x528	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_12	0x52c	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_13	0x530	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_14	0x534	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.DIO_PAD_ATTR_15	0x538	4	Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.
pinmux.MIO_PAD_SLEEP_STATUS_0	0x53c	4	Register indicating whether the corresponding pad is in sleep mode.
pinmux.MIO_PAD_SLEEP_STATUS_1	0x540	4	Register indicating whether the corresponding pad is in sleep mode.
pinmux.MIO_PAD_SLEEP_REGWEN_0	0x544	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_1	0x548	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_2	0x54c	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_3	0x550	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_4	0x554	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_5	0x558	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_6	0x55c	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_7	0x560	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_8	0x564	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_9	0x568	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_10	0x56c	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_11	0x570	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_12	0x574	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_13	0x578	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_14	0x57c	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_15	0x580	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_16	0x584	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_17	0x588	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_18	0x58c	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_19	0x590	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_20	0x594	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_21	0x598	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_22	0x59c	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_23	0x5a0	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_24	0x5a4	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_25	0x5a8	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_26	0x5ac	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_27	0x5b0	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_28	0x5b4	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_29	0x5b8	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_30	0x5bc	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_31	0x5c0	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_32	0x5c4	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_33	0x5c8	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_34	0x5cc	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_35	0x5d0	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_36	0x5d4	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_37	0x5d8	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_38	0x5dc	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_39	0x5e0	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_40	0x5e4	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_41	0x5e8	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_42	0x5ec	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_43	0x5f0	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_44	0x5f4	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_45	0x5f8	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_REGWEN_46	0x5fc	4	Register write enable for MIO sleep value configuration.
pinmux.MIO_PAD_SLEEP_EN_0	0x600	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_1	0x604	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_2	0x608	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_3	0x60c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_4	0x610	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_5	0x614	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_6	0x618	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_7	0x61c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_8	0x620	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_9	0x624	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_10	0x628	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_11	0x62c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_12	0x630	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_13	0x634	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_14	0x638	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_15	0x63c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_16	0x640	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_17	0x644	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_18	0x648	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_19	0x64c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_20	0x650	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_21	0x654	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_22	0x658	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_23	0x65c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_24	0x660	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_25	0x664	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_26	0x668	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_27	0x66c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_28	0x670	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_29	0x674	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_30	0x678	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_31	0x67c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_32	0x680	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_33	0x684	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_34	0x688	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_35	0x68c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_36	0x690	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_37	0x694	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_38	0x698	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_39	0x69c	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_40	0x6a0	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_41	0x6a4	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_42	0x6a8	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_43	0x6ac	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_44	0x6b0	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_45	0x6b4	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_EN_46	0x6b8	4	Enables the sleep mode of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_0	0x6bc	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_1	0x6c0	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_2	0x6c4	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_3	0x6c8	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_4	0x6cc	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_5	0x6d0	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_6	0x6d4	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_7	0x6d8	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_8	0x6dc	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_9	0x6e0	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_10	0x6e4	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_11	0x6e8	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_12	0x6ec	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_13	0x6f0	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_14	0x6f4	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_15	0x6f8	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_16	0x6fc	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_17	0x700	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_18	0x704	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_19	0x708	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_20	0x70c	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_21	0x710	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_22	0x714	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_23	0x718	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_24	0x71c	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_25	0x720	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_26	0x724	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_27	0x728	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_28	0x72c	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_29	0x730	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_30	0x734	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_31	0x738	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_32	0x73c	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_33	0x740	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_34	0x744	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_35	0x748	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_36	0x74c	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_37	0x750	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_38	0x754	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_39	0x758	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_40	0x75c	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_41	0x760	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_42	0x764	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_43	0x768	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_44	0x76c	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_45	0x770	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.MIO_PAD_SLEEP_MODE_46	0x774	4	Defines sleep behavior of the corresponding muxed pad.
pinmux.DIO_PAD_SLEEP_STATUS	0x778	4	Register indicating whether the corresponding pad is in sleep mode.
pinmux.DIO_PAD_SLEEP_REGWEN_0	0x77c	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_1	0x780	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_2	0x784	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_3	0x788	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_4	0x78c	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_5	0x790	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_6	0x794	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_7	0x798	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_8	0x79c	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_9	0x7a0	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_10	0x7a4	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_11	0x7a8	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_12	0x7ac	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_13	0x7b0	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_14	0x7b4	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_REGWEN_15	0x7b8	4	Register write enable for DIO sleep value configuration.
pinmux.DIO_PAD_SLEEP_EN_0	0x7bc	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_1	0x7c0	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_2	0x7c4	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_3	0x7c8	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_4	0x7cc	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_5	0x7d0	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_6	0x7d4	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_7	0x7d8	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_8	0x7dc	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_9	0x7e0	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_10	0x7e4	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_11	0x7e8	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_12	0x7ec	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_13	0x7f0	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_14	0x7f4	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_EN_15	0x7f8	4	Enables the sleep mode of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_0	0x7fc	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_1	0x800	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_2	0x804	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_3	0x808	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_4	0x80c	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_5	0x810	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_6	0x814	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_7	0x818	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_8	0x81c	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_9	0x820	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_10	0x824	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_11	0x828	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_12	0x82c	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_13	0x830	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_14	0x834	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.DIO_PAD_SLEEP_MODE_15	0x838	4	Defines sleep behavior of the corresponding dedicated pad.
pinmux.WKUP_DETECTOR_REGWEN_0	0x83c	4	Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_1	0x840	4	Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_2	0x844	4	Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_3	0x848	4	Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_4	0x84c	4	Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_5	0x850	4	Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_6	0x854	4	Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_REGWEN_7	0x858	4	Register write enable for wakeup detectors.
pinmux.WKUP_DETECTOR_EN_0	0x85c	4	Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_EN_1	0x860	4	Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_EN_2	0x864	4	Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_EN_3	0x868	4	Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_EN_4	0x86c	4	Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_EN_5	0x870	4	Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_EN_6	0x874	4	Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_EN_7	0x878	4	Enables for the wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_0	0x87c	4	Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_1	0x880	4	Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_2	0x884	4	Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_3	0x888	4	Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_4	0x88c	4	Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_5	0x890	4	Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_6	0x894	4	Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_7	0x898	4	Configuration of wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_CNT_TH_0	0x89c	4	Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_CNT_TH_1	0x8a0	4	Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_CNT_TH_2	0x8a4	4	Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_CNT_TH_3	0x8a8	4	Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_CNT_TH_4	0x8ac	4	Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_CNT_TH_5	0x8b0	4	Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_CNT_TH_6	0x8b4	4	Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_CNT_TH_7	0x8b8	4	Counter thresholds for wakeup condition detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.
pinmux.WKUP_DETECTOR_PADSEL_0	0x8bc	4	Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
pinmux.WKUP_DETECTOR_PADSEL_1	0x8c0	4	Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
pinmux.WKUP_DETECTOR_PADSEL_2	0x8c4	4	Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
pinmux.WKUP_DETECTOR_PADSEL_3	0x8c8	4	Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
pinmux.WKUP_DETECTOR_PADSEL_4	0x8cc	4	Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
pinmux.WKUP_DETECTOR_PADSEL_5	0x8d0	4	Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
pinmux.WKUP_DETECTOR_PADSEL_6	0x8d4	4	Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
pinmux.WKUP_DETECTOR_PADSEL_7	0x8d8	4	Pad selects for pad wakeup condition detectors. This register is NOT synced to the AON domain since the muxing mechanism is implemented in the same way as the pinmux muxing matrix.
pinmux.WKUP_CAUSE	0x8dc	4	Cause registers for wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed.

pinmux.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															fatal_fault

Bits

Type

Reset

Name

Description

0x0

fatal_fault

Write 1 to trigger one alert event of this kind.

pinmux.MIO_PERIPH_INSEL_REGWEN_0 @ 0x4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

pinmux.MIO_PERIPH_INSEL_REGWEN_1 @ 0x8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For MIO_PERIPH_INSEL1

pinmux.MIO_PERIPH_INSEL_REGWEN_2 @ 0xc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For MIO_PERIPH_INSEL2

pinmux.MIO_PERIPH_INSEL_REGWEN_3 @ 0x10

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For MIO_PERIPH_INSEL3

pinmux.MIO_PERIPH_INSEL_REGWEN_4 @ 0x14

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For MIO_PERIPH_INSEL4

pinmux.MIO_PERIPH_INSEL_REGWEN_5 @ 0x18

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For MIO_PERIPH_INSEL5

pinmux.MIO_PERIPH_INSEL_REGWEN_6 @ 0x1c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For MIO_PERIPH_INSEL6

pinmux.MIO_PERIPH_INSEL_REGWEN_7 @ 0x20

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For MIO_PERIPH_INSEL7

pinmux.MIO_PERIPH_INSEL_REGWEN_8 @ 0x24

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For MIO_PERIPH_INSEL8

pinmux.MIO_PERIPH_INSEL_REGWEN_9 @ 0x28

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For MIO_PERIPH_INSEL9

pinmux.MIO_PERIPH_INSEL_REGWEN_10 @ 0x2c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For MIO_PERIPH_INSEL10

pinmux.MIO_PERIPH_INSEL_REGWEN_11 @ 0x30

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For MIO_PERIPH_INSEL11

pinmux.MIO_PERIPH_INSEL_REGWEN_12 @ 0x34

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For MIO_PERIPH_INSEL12

pinmux.MIO_PERIPH_INSEL_REGWEN_13 @ 0x38

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For MIO_PERIPH_INSEL13

pinmux.MIO_PERIPH_INSEL_REGWEN_14 @ 0x3c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For MIO_PERIPH_INSEL14

pinmux.MIO_PERIPH_INSEL_REGWEN_15 @ 0x40

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For MIO_PERIPH_INSEL15

pinmux.MIO_PERIPH_INSEL_REGWEN_16 @ 0x44

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For MIO_PERIPH_INSEL16

pinmux.MIO_PERIPH_INSEL_REGWEN_17 @ 0x48

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For MIO_PERIPH_INSEL17

pinmux.MIO_PERIPH_INSEL_REGWEN_18 @ 0x4c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For MIO_PERIPH_INSEL18

pinmux.MIO_PERIPH_INSEL_REGWEN_19 @ 0x50

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For MIO_PERIPH_INSEL19

pinmux.MIO_PERIPH_INSEL_REGWEN_20 @ 0x54

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For MIO_PERIPH_INSEL20

pinmux.MIO_PERIPH_INSEL_REGWEN_21 @ 0x58

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For MIO_PERIPH_INSEL21

pinmux.MIO_PERIPH_INSEL_REGWEN_22 @ 0x5c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For MIO_PERIPH_INSEL22

pinmux.MIO_PERIPH_INSEL_REGWEN_23 @ 0x60

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For MIO_PERIPH_INSEL23

pinmux.MIO_PERIPH_INSEL_REGWEN_24 @ 0x64

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For MIO_PERIPH_INSEL24

pinmux.MIO_PERIPH_INSEL_REGWEN_25 @ 0x68

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For MIO_PERIPH_INSEL25

pinmux.MIO_PERIPH_INSEL_REGWEN_26 @ 0x6c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For MIO_PERIPH_INSEL26

pinmux.MIO_PERIPH_INSEL_REGWEN_27 @ 0x70

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For MIO_PERIPH_INSEL27

pinmux.MIO_PERIPH_INSEL_REGWEN_28 @ 0x74

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For MIO_PERIPH_INSEL28

pinmux.MIO_PERIPH_INSEL_REGWEN_29 @ 0x78

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For MIO_PERIPH_INSEL29

pinmux.MIO_PERIPH_INSEL_REGWEN_30 @ 0x7c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For MIO_PERIPH_INSEL30

pinmux.MIO_PERIPH_INSEL_REGWEN_31 @ 0x80

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For MIO_PERIPH_INSEL31

pinmux.MIO_PERIPH_INSEL_REGWEN_32 @ 0x84

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For MIO_PERIPH_INSEL32

pinmux.MIO_PERIPH_INSEL_REGWEN_33 @ 0x88

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For MIO_PERIPH_INSEL33

pinmux.MIO_PERIPH_INSEL_REGWEN_34 @ 0x8c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For MIO_PERIPH_INSEL34

pinmux.MIO_PERIPH_INSEL_REGWEN_35 @ 0x90

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For MIO_PERIPH_INSEL35

pinmux.MIO_PERIPH_INSEL_REGWEN_36 @ 0x94

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For MIO_PERIPH_INSEL36

pinmux.MIO_PERIPH_INSEL_REGWEN_37 @ 0x98

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For MIO_PERIPH_INSEL37

pinmux.MIO_PERIPH_INSEL_REGWEN_38 @ 0x9c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For MIO_PERIPH_INSEL38

pinmux.MIO_PERIPH_INSEL_REGWEN_39 @ 0xa0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For MIO_PERIPH_INSEL39

pinmux.MIO_PERIPH_INSEL_REGWEN_40 @ 0xa4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For MIO_PERIPH_INSEL40

pinmux.MIO_PERIPH_INSEL_REGWEN_41 @ 0xa8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For MIO_PERIPH_INSEL41

pinmux.MIO_PERIPH_INSEL_REGWEN_42 @ 0xac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For MIO_PERIPH_INSEL42

pinmux.MIO_PERIPH_INSEL_REGWEN_43 @ 0xb0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For MIO_PERIPH_INSEL43

pinmux.MIO_PERIPH_INSEL_REGWEN_44 @ 0xb4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For MIO_PERIPH_INSEL44

pinmux.MIO_PERIPH_INSEL_REGWEN_45 @ 0xb8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For MIO_PERIPH_INSEL45

pinmux.MIO_PERIPH_INSEL_REGWEN_46 @ 0xbc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For MIO_PERIPH_INSEL46

pinmux.MIO_PERIPH_INSEL_REGWEN_47 @ 0xc0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_47

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_47

For MIO_PERIPH_INSEL47

pinmux.MIO_PERIPH_INSEL_REGWEN_48 @ 0xc4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_48

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_48

For MIO_PERIPH_INSEL48

pinmux.MIO_PERIPH_INSEL_REGWEN_49 @ 0xc8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_49

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_49

For MIO_PERIPH_INSEL49

pinmux.MIO_PERIPH_INSEL_REGWEN_50 @ 0xcc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_50

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_50

For MIO_PERIPH_INSEL50

pinmux.MIO_PERIPH_INSEL_REGWEN_51 @ 0xd0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_51

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_51

For MIO_PERIPH_INSEL51

pinmux.MIO_PERIPH_INSEL_REGWEN_52 @ 0xd4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_52

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_52

For MIO_PERIPH_INSEL52

pinmux.MIO_PERIPH_INSEL_REGWEN_53 @ 0xd8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_53

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_53

For MIO_PERIPH_INSEL53

pinmux.MIO_PERIPH_INSEL_REGWEN_54 @ 0xdc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_54

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_54

For MIO_PERIPH_INSEL54

pinmux.MIO_PERIPH_INSEL_REGWEN_55 @ 0xe0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_55

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_55

For MIO_PERIPH_INSEL55

pinmux.MIO_PERIPH_INSEL_REGWEN_56 @ 0xe4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_56

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_56

For MIO_PERIPH_INSEL56

pinmux.MIO_PERIPH_INSEL_0 @ 0xe8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_0

Bits

Type

Reset

Name

Description

5:0

0x0

IN_0

0: tie constantly to zero, 1: tie constantly to 1,

=2: MIO pads (i.e., add 2 to the native MIO pad index).

pinmux.MIO_PERIPH_INSEL_1 @ 0xec

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_1

Bits

Type

Reset

Name

Description

5:0

0x0

IN_1

For IN1

pinmux.MIO_PERIPH_INSEL_2 @ 0xf0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_2

Bits

Type

Reset

Name

Description

5:0

0x0

IN_2

For IN2

pinmux.MIO_PERIPH_INSEL_3 @ 0xf4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_3

Bits

Type

Reset

Name

Description

5:0

0x0

IN_3

For IN3

pinmux.MIO_PERIPH_INSEL_4 @ 0xf8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_4

Bits

Type

Reset

Name

Description

5:0

0x0

IN_4

For IN4

pinmux.MIO_PERIPH_INSEL_5 @ 0xfc

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_5

Bits

Type

Reset

Name

Description

5:0

0x0

IN_5

For IN5

pinmux.MIO_PERIPH_INSEL_6 @ 0x100

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_6

Bits

Type

Reset

Name

Description

5:0

0x0

IN_6

For IN6

pinmux.MIO_PERIPH_INSEL_7 @ 0x104

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_7

Bits

Type

Reset

Name

Description

5:0

0x0

IN_7

For IN7

pinmux.MIO_PERIPH_INSEL_8 @ 0x108

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_8

Bits

Type

Reset

Name

Description

5:0

0x0

IN_8

For IN8

pinmux.MIO_PERIPH_INSEL_9 @ 0x10c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_9

Bits

Type

Reset

Name

Description

5:0

0x0

IN_9

For IN9

pinmux.MIO_PERIPH_INSEL_10 @ 0x110

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_10

Bits

Type

Reset

Name

Description

5:0

0x0

IN_10

For IN10

pinmux.MIO_PERIPH_INSEL_11 @ 0x114

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_11

Bits

Type

Reset

Name

Description

5:0

0x0

IN_11

For IN11

pinmux.MIO_PERIPH_INSEL_12 @ 0x118

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_12

Bits

Type

Reset

Name

Description

5:0

0x0

IN_12

For IN12

pinmux.MIO_PERIPH_INSEL_13 @ 0x11c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_13

Bits

Type

Reset

Name

Description

5:0

0x0

IN_13

For IN13

pinmux.MIO_PERIPH_INSEL_14 @ 0x120

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_14

Bits

Type

Reset

Name

Description

5:0

0x0

IN_14

For IN14

pinmux.MIO_PERIPH_INSEL_15 @ 0x124

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_15

Bits

Type

Reset

Name

Description

5:0

0x0

IN_15

For IN15

pinmux.MIO_PERIPH_INSEL_16 @ 0x128

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_16

Bits

Type

Reset

Name

Description

5:0

0x0

IN_16

For IN16

pinmux.MIO_PERIPH_INSEL_17 @ 0x12c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_17

Bits

Type

Reset

Name

Description

5:0

0x0

IN_17

For IN17

pinmux.MIO_PERIPH_INSEL_18 @ 0x130

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_18

Bits

Type

Reset

Name

Description

5:0

0x0

IN_18

For IN18

pinmux.MIO_PERIPH_INSEL_19 @ 0x134

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_19

Bits

Type

Reset

Name

Description

5:0

0x0

IN_19

For IN19

pinmux.MIO_PERIPH_INSEL_20 @ 0x138

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_20

Bits

Type

Reset

Name

Description

5:0

0x0

IN_20

For IN20

pinmux.MIO_PERIPH_INSEL_21 @ 0x13c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_21

Bits

Type

Reset

Name

Description

5:0

0x0

IN_21

For IN21

pinmux.MIO_PERIPH_INSEL_22 @ 0x140

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_22

Bits

Type

Reset

Name

Description

5:0

0x0

IN_22

For IN22

pinmux.MIO_PERIPH_INSEL_23 @ 0x144

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_23

Bits

Type

Reset

Name

Description

5:0

0x0

IN_23

For IN23

pinmux.MIO_PERIPH_INSEL_24 @ 0x148

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_24

Bits

Type

Reset

Name

Description

5:0

0x0

IN_24

For IN24

pinmux.MIO_PERIPH_INSEL_25 @ 0x14c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_25

Bits

Type

Reset

Name

Description

5:0

0x0

IN_25

For IN25

pinmux.MIO_PERIPH_INSEL_26 @ 0x150

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_26

Bits

Type

Reset

Name

Description

5:0

0x0

IN_26

For IN26

pinmux.MIO_PERIPH_INSEL_27 @ 0x154

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_27

Bits

Type

Reset

Name

Description

5:0

0x0

IN_27

For IN27

pinmux.MIO_PERIPH_INSEL_28 @ 0x158

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_28

Bits

Type

Reset

Name

Description

5:0

0x0

IN_28

For IN28

pinmux.MIO_PERIPH_INSEL_29 @ 0x15c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_29

Bits

Type

Reset

Name

Description

5:0

0x0

IN_29

For IN29

pinmux.MIO_PERIPH_INSEL_30 @ 0x160

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_30

Bits

Type

Reset

Name

Description

5:0

0x0

IN_30

For IN30

pinmux.MIO_PERIPH_INSEL_31 @ 0x164

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_31

Bits

Type

Reset

Name

Description

5:0

0x0

IN_31

For IN31

pinmux.MIO_PERIPH_INSEL_32 @ 0x168

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_32

Bits

Type

Reset

Name

Description

5:0

0x0

IN_32

For IN32

pinmux.MIO_PERIPH_INSEL_33 @ 0x16c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_33

Bits

Type

Reset

Name

Description

5:0

0x0

IN_33

For IN33

pinmux.MIO_PERIPH_INSEL_34 @ 0x170

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_34

Bits

Type

Reset

Name

Description

5:0

0x0

IN_34

For IN34

pinmux.MIO_PERIPH_INSEL_35 @ 0x174

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_35

Bits

Type

Reset

Name

Description

5:0

0x0

IN_35

For IN35

pinmux.MIO_PERIPH_INSEL_36 @ 0x178

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_36

Bits

Type

Reset

Name

Description

5:0

0x0

IN_36

For IN36

pinmux.MIO_PERIPH_INSEL_37 @ 0x17c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_37

Bits

Type

Reset

Name

Description

5:0

0x0

IN_37

For IN37

pinmux.MIO_PERIPH_INSEL_38 @ 0x180

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_38

Bits

Type

Reset

Name

Description

5:0

0x0

IN_38

For IN38

pinmux.MIO_PERIPH_INSEL_39 @ 0x184

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_39

Bits

Type

Reset

Name

Description

5:0

0x0

IN_39

For IN39

pinmux.MIO_PERIPH_INSEL_40 @ 0x188

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_40

Bits

Type

Reset

Name

Description

5:0

0x0

IN_40

For IN40

pinmux.MIO_PERIPH_INSEL_41 @ 0x18c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_41

Bits

Type

Reset

Name

Description

5:0

0x0

IN_41

For IN41

pinmux.MIO_PERIPH_INSEL_42 @ 0x190

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_42

Bits

Type

Reset

Name

Description

5:0

0x0

IN_42

For IN42

pinmux.MIO_PERIPH_INSEL_43 @ 0x194

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_43

Bits

Type

Reset

Name

Description

5:0

0x0

IN_43

For IN43

pinmux.MIO_PERIPH_INSEL_44 @ 0x198

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_44

Bits

Type

Reset

Name

Description

5:0

0x0

IN_44

For IN44

pinmux.MIO_PERIPH_INSEL_45 @ 0x19c

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_45

Bits

Type

Reset

Name

Description

5:0

0x0

IN_45

For IN45

pinmux.MIO_PERIPH_INSEL_46 @ 0x1a0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_46

Bits

Type

Reset

Name

Description

5:0

0x0

IN_46

For IN46

pinmux.MIO_PERIPH_INSEL_47 @ 0x1a4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_47

Bits

Type

Reset

Name

Description

5:0

0x0

IN_47

For IN47

pinmux.MIO_PERIPH_INSEL_48 @ 0x1a8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_48

Bits

Type

Reset

Name

Description

5:0

0x0

IN_48

For IN48

pinmux.MIO_PERIPH_INSEL_49 @ 0x1ac

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_49

Bits

Type

Reset

Name

Description

5:0

0x0

IN_49

For IN49

pinmux.MIO_PERIPH_INSEL_50 @ 0x1b0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_50

Bits

Type

Reset

Name

Description

5:0

0x0

IN_50

For IN50

pinmux.MIO_PERIPH_INSEL_51 @ 0x1b4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_51

Bits

Type

Reset

Name

Description

5:0

0x0

IN_51

For IN51

pinmux.MIO_PERIPH_INSEL_52 @ 0x1b8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_52

Bits

Type

Reset

Name

Description

5:0

0x0

IN_52

For IN52

pinmux.MIO_PERIPH_INSEL_53 @ 0x1bc

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_53

Bits

Type

Reset

Name

Description

5:0

0x0

IN_53

For IN53

pinmux.MIO_PERIPH_INSEL_54 @ 0x1c0

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_54

Bits

Type

Reset

Name

Description

5:0

0x0

IN_54

For IN54

pinmux.MIO_PERIPH_INSEL_55 @ 0x1c4

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_55

Bits

Type

Reset

Name

Description

5:0

0x0

IN_55

For IN55

pinmux.MIO_PERIPH_INSEL_56 @ 0x1c8

For each peripheral input, this selects the muxable pad input.

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										IN_56

Bits

Type

Reset

Name

Description

5:0

0x0

IN_56

For IN56

pinmux.MIO_OUTSEL_REGWEN_0 @ 0x1cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_0

pinmux.MIO_OUTSEL_REGWEN_1 @ 0x1d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For MIO_OUTSEL1

pinmux.MIO_OUTSEL_REGWEN_2 @ 0x1d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For MIO_OUTSEL2

pinmux.MIO_OUTSEL_REGWEN_3 @ 0x1d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For MIO_OUTSEL3

pinmux.MIO_OUTSEL_REGWEN_4 @ 0x1dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For MIO_OUTSEL4

pinmux.MIO_OUTSEL_REGWEN_5 @ 0x1e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For MIO_OUTSEL5

pinmux.MIO_OUTSEL_REGWEN_6 @ 0x1e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For MIO_OUTSEL6

pinmux.MIO_OUTSEL_REGWEN_7 @ 0x1e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For MIO_OUTSEL7

pinmux.MIO_OUTSEL_REGWEN_8 @ 0x1ec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For MIO_OUTSEL8

pinmux.MIO_OUTSEL_REGWEN_9 @ 0x1f0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For MIO_OUTSEL9

pinmux.MIO_OUTSEL_REGWEN_10 @ 0x1f4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For MIO_OUTSEL10

pinmux.MIO_OUTSEL_REGWEN_11 @ 0x1f8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For MIO_OUTSEL11

pinmux.MIO_OUTSEL_REGWEN_12 @ 0x1fc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For MIO_OUTSEL12

pinmux.MIO_OUTSEL_REGWEN_13 @ 0x200

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For MIO_OUTSEL13

pinmux.MIO_OUTSEL_REGWEN_14 @ 0x204

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For MIO_OUTSEL14

pinmux.MIO_OUTSEL_REGWEN_15 @ 0x208

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For MIO_OUTSEL15

pinmux.MIO_OUTSEL_REGWEN_16 @ 0x20c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For MIO_OUTSEL16

pinmux.MIO_OUTSEL_REGWEN_17 @ 0x210

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For MIO_OUTSEL17

pinmux.MIO_OUTSEL_REGWEN_18 @ 0x214

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For MIO_OUTSEL18

pinmux.MIO_OUTSEL_REGWEN_19 @ 0x218

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For MIO_OUTSEL19

pinmux.MIO_OUTSEL_REGWEN_20 @ 0x21c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For MIO_OUTSEL20

pinmux.MIO_OUTSEL_REGWEN_21 @ 0x220

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For MIO_OUTSEL21

pinmux.MIO_OUTSEL_REGWEN_22 @ 0x224

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For MIO_OUTSEL22

pinmux.MIO_OUTSEL_REGWEN_23 @ 0x228

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For MIO_OUTSEL23

pinmux.MIO_OUTSEL_REGWEN_24 @ 0x22c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For MIO_OUTSEL24

pinmux.MIO_OUTSEL_REGWEN_25 @ 0x230

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For MIO_OUTSEL25

pinmux.MIO_OUTSEL_REGWEN_26 @ 0x234

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For MIO_OUTSEL26

pinmux.MIO_OUTSEL_REGWEN_27 @ 0x238

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For MIO_OUTSEL27

pinmux.MIO_OUTSEL_REGWEN_28 @ 0x23c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For MIO_OUTSEL28

pinmux.MIO_OUTSEL_REGWEN_29 @ 0x240

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For MIO_OUTSEL29

pinmux.MIO_OUTSEL_REGWEN_30 @ 0x244

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For MIO_OUTSEL30

pinmux.MIO_OUTSEL_REGWEN_31 @ 0x248

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For MIO_OUTSEL31

pinmux.MIO_OUTSEL_REGWEN_32 @ 0x24c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For MIO_OUTSEL32

pinmux.MIO_OUTSEL_REGWEN_33 @ 0x250

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For MIO_OUTSEL33

pinmux.MIO_OUTSEL_REGWEN_34 @ 0x254

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For MIO_OUTSEL34

pinmux.MIO_OUTSEL_REGWEN_35 @ 0x258

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For MIO_OUTSEL35

pinmux.MIO_OUTSEL_REGWEN_36 @ 0x25c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For MIO_OUTSEL36

pinmux.MIO_OUTSEL_REGWEN_37 @ 0x260

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For MIO_OUTSEL37

pinmux.MIO_OUTSEL_REGWEN_38 @ 0x264

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For MIO_OUTSEL38

pinmux.MIO_OUTSEL_REGWEN_39 @ 0x268

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For MIO_OUTSEL39

pinmux.MIO_OUTSEL_REGWEN_40 @ 0x26c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For MIO_OUTSEL40

pinmux.MIO_OUTSEL_REGWEN_41 @ 0x270

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For MIO_OUTSEL41

pinmux.MIO_OUTSEL_REGWEN_42 @ 0x274

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For MIO_OUTSEL42

pinmux.MIO_OUTSEL_REGWEN_43 @ 0x278

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For MIO_OUTSEL43

pinmux.MIO_OUTSEL_REGWEN_44 @ 0x27c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For MIO_OUTSEL44

pinmux.MIO_OUTSEL_REGWEN_45 @ 0x280

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For MIO_OUTSEL45

pinmux.MIO_OUTSEL_REGWEN_46 @ 0x284

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For MIO_OUTSEL46

pinmux.MIO_OUTSEL_0 @ 0x288

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_0

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_0

0: tie constantly to zero, 1: tie constantly to 1, 2: high-Z,

=3: peripheral outputs (i.e., add 3 to the native peripheral pad index).

pinmux.MIO_OUTSEL_1 @ 0x28c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_1

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_1

For OUT1

pinmux.MIO_OUTSEL_2 @ 0x290

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_2

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_2

For OUT2

pinmux.MIO_OUTSEL_3 @ 0x294

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_3

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_3

For OUT3

pinmux.MIO_OUTSEL_4 @ 0x298

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_4

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_4

For OUT4

pinmux.MIO_OUTSEL_5 @ 0x29c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_5

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_5

For OUT5

pinmux.MIO_OUTSEL_6 @ 0x2a0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_6

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_6

For OUT6

pinmux.MIO_OUTSEL_7 @ 0x2a4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_7

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_7

For OUT7

pinmux.MIO_OUTSEL_8 @ 0x2a8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_8

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_8

For OUT8

pinmux.MIO_OUTSEL_9 @ 0x2ac

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_9

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_9

For OUT9

pinmux.MIO_OUTSEL_10 @ 0x2b0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_10

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_10

For OUT10

pinmux.MIO_OUTSEL_11 @ 0x2b4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_11

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_11

For OUT11

pinmux.MIO_OUTSEL_12 @ 0x2b8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_12

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_12

For OUT12

pinmux.MIO_OUTSEL_13 @ 0x2bc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_13

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_13

For OUT13

pinmux.MIO_OUTSEL_14 @ 0x2c0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_14

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_14

For OUT14

pinmux.MIO_OUTSEL_15 @ 0x2c4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_15

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_15

For OUT15

pinmux.MIO_OUTSEL_16 @ 0x2c8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_16

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_16

For OUT16

pinmux.MIO_OUTSEL_17 @ 0x2cc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_17

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_17

For OUT17

pinmux.MIO_OUTSEL_18 @ 0x2d0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_18

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_18

For OUT18

pinmux.MIO_OUTSEL_19 @ 0x2d4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_19

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_19

For OUT19

pinmux.MIO_OUTSEL_20 @ 0x2d8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_20

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_20

For OUT20

pinmux.MIO_OUTSEL_21 @ 0x2dc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_21

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_21

For OUT21

pinmux.MIO_OUTSEL_22 @ 0x2e0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_22

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_22

For OUT22

pinmux.MIO_OUTSEL_23 @ 0x2e4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_23

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_23

For OUT23

pinmux.MIO_OUTSEL_24 @ 0x2e8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_24

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_24

For OUT24

pinmux.MIO_OUTSEL_25 @ 0x2ec

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_25

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_25

For OUT25

pinmux.MIO_OUTSEL_26 @ 0x2f0

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_26

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_26

For OUT26

pinmux.MIO_OUTSEL_27 @ 0x2f4

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_27

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_27

For OUT27

pinmux.MIO_OUTSEL_28 @ 0x2f8

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_28

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_28

For OUT28

pinmux.MIO_OUTSEL_29 @ 0x2fc

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_29

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_29

For OUT29

pinmux.MIO_OUTSEL_30 @ 0x300

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_30

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_30

For OUT30

pinmux.MIO_OUTSEL_31 @ 0x304

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_31

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_31

For OUT31

pinmux.MIO_OUTSEL_32 @ 0x308

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_32

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_32

For OUT32

pinmux.MIO_OUTSEL_33 @ 0x30c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_33

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_33

For OUT33

pinmux.MIO_OUTSEL_34 @ 0x310

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_34

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_34

For OUT34

pinmux.MIO_OUTSEL_35 @ 0x314

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_35

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_35

For OUT35

pinmux.MIO_OUTSEL_36 @ 0x318

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_36

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_36

For OUT36

pinmux.MIO_OUTSEL_37 @ 0x31c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_37

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_37

For OUT37

pinmux.MIO_OUTSEL_38 @ 0x320

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_38

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_38

For OUT38

pinmux.MIO_OUTSEL_39 @ 0x324

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_39

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_39

For OUT39

pinmux.MIO_OUTSEL_40 @ 0x328

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_40

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_40

For OUT40

pinmux.MIO_OUTSEL_41 @ 0x32c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_41

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_41

For OUT41

pinmux.MIO_OUTSEL_42 @ 0x330

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_42

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_42

For OUT42

pinmux.MIO_OUTSEL_43 @ 0x334

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_43

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_43

For OUT43

pinmux.MIO_OUTSEL_44 @ 0x338

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_44

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_44

For OUT44

pinmux.MIO_OUTSEL_45 @ 0x33c

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_45

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_45

For OUT45

pinmux.MIO_OUTSEL_46 @ 0x340

For each muxable pad, this selects the peripheral output.

Reset default = 0x2, mask 0x7f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OUT_46

Bits

Type

Reset

Name

Description

6:0

0x2

OUT_46

For OUT46

pinmux.MIO_PAD_ATTR_REGWEN_0 @ 0x344

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits Type Reset Name Description

rw0c

0x1

EN_0

pinmux.MIO_PAD_ATTR_REGWEN_1 @ 0x348

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For MIO_PAD1

pinmux.MIO_PAD_ATTR_REGWEN_2 @ 0x34c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For MIO_PAD2

pinmux.MIO_PAD_ATTR_REGWEN_3 @ 0x350

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For MIO_PAD3

pinmux.MIO_PAD_ATTR_REGWEN_4 @ 0x354

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For MIO_PAD4

pinmux.MIO_PAD_ATTR_REGWEN_5 @ 0x358

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For MIO_PAD5

pinmux.MIO_PAD_ATTR_REGWEN_6 @ 0x35c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For MIO_PAD6

pinmux.MIO_PAD_ATTR_REGWEN_7 @ 0x360

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For MIO_PAD7

pinmux.MIO_PAD_ATTR_REGWEN_8 @ 0x364

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For MIO_PAD8

pinmux.MIO_PAD_ATTR_REGWEN_9 @ 0x368

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For MIO_PAD9

pinmux.MIO_PAD_ATTR_REGWEN_10 @ 0x36c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For MIO_PAD10

pinmux.MIO_PAD_ATTR_REGWEN_11 @ 0x370

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For MIO_PAD11

pinmux.MIO_PAD_ATTR_REGWEN_12 @ 0x374

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For MIO_PAD12

pinmux.MIO_PAD_ATTR_REGWEN_13 @ 0x378

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For MIO_PAD13

pinmux.MIO_PAD_ATTR_REGWEN_14 @ 0x37c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For MIO_PAD14

pinmux.MIO_PAD_ATTR_REGWEN_15 @ 0x380

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For MIO_PAD15

pinmux.MIO_PAD_ATTR_REGWEN_16 @ 0x384

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For MIO_PAD16

pinmux.MIO_PAD_ATTR_REGWEN_17 @ 0x388

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For MIO_PAD17

pinmux.MIO_PAD_ATTR_REGWEN_18 @ 0x38c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For MIO_PAD18

pinmux.MIO_PAD_ATTR_REGWEN_19 @ 0x390

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For MIO_PAD19

pinmux.MIO_PAD_ATTR_REGWEN_20 @ 0x394

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For MIO_PAD20

pinmux.MIO_PAD_ATTR_REGWEN_21 @ 0x398

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For MIO_PAD21

pinmux.MIO_PAD_ATTR_REGWEN_22 @ 0x39c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For MIO_PAD22

pinmux.MIO_PAD_ATTR_REGWEN_23 @ 0x3a0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For MIO_PAD23

pinmux.MIO_PAD_ATTR_REGWEN_24 @ 0x3a4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For MIO_PAD24

pinmux.MIO_PAD_ATTR_REGWEN_25 @ 0x3a8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For MIO_PAD25

pinmux.MIO_PAD_ATTR_REGWEN_26 @ 0x3ac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For MIO_PAD26

pinmux.MIO_PAD_ATTR_REGWEN_27 @ 0x3b0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For MIO_PAD27

pinmux.MIO_PAD_ATTR_REGWEN_28 @ 0x3b4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For MIO_PAD28

pinmux.MIO_PAD_ATTR_REGWEN_29 @ 0x3b8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For MIO_PAD29

pinmux.MIO_PAD_ATTR_REGWEN_30 @ 0x3bc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For MIO_PAD30

pinmux.MIO_PAD_ATTR_REGWEN_31 @ 0x3c0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For MIO_PAD31

pinmux.MIO_PAD_ATTR_REGWEN_32 @ 0x3c4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For MIO_PAD32

pinmux.MIO_PAD_ATTR_REGWEN_33 @ 0x3c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For MIO_PAD33

pinmux.MIO_PAD_ATTR_REGWEN_34 @ 0x3cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For MIO_PAD34

pinmux.MIO_PAD_ATTR_REGWEN_35 @ 0x3d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For MIO_PAD35

pinmux.MIO_PAD_ATTR_REGWEN_36 @ 0x3d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For MIO_PAD36

pinmux.MIO_PAD_ATTR_REGWEN_37 @ 0x3d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For MIO_PAD37

pinmux.MIO_PAD_ATTR_REGWEN_38 @ 0x3dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For MIO_PAD38

pinmux.MIO_PAD_ATTR_REGWEN_39 @ 0x3e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For MIO_PAD39

pinmux.MIO_PAD_ATTR_REGWEN_40 @ 0x3e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For MIO_PAD40

pinmux.MIO_PAD_ATTR_REGWEN_41 @ 0x3e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For MIO_PAD41

pinmux.MIO_PAD_ATTR_REGWEN_42 @ 0x3ec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For MIO_PAD42

pinmux.MIO_PAD_ATTR_REGWEN_43 @ 0x3f0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For MIO_PAD43

pinmux.MIO_PAD_ATTR_REGWEN_44 @ 0x3f4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For MIO_PAD44

pinmux.MIO_PAD_ATTR_REGWEN_45 @ 0x3f8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For MIO_PAD45

pinmux.MIO_PAD_ATTR_REGWEN_46 @ 0x3fc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For MIO_PAD46

pinmux.MIO_PAD_ATTR_0 @ 0x400

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_0						slew_rate_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_0	schmitt_en_0	keeper_en_0	pull_select_0	pull_en_0	virtual_od_en_0	invert_0

Bits

Type

Reset

Name

Description

0x0

invert_0

Invert input and output levels.

0x0

virtual_od_en_0

Enable virtual open drain.

0x0

pull_en_0

Enable pull-up or pull-down resistor.

0x0

pull_select_0

Pull select (0: pull-down, 1: pull-up).

0x0	pull_down	Select the pull-down resistor.
0x1	pull_up	Select the pull-up resistor.

0x0

keeper_en_0

Enable pull-up or pull-down resistor.

0x0

schmitt_en_0

Enable the schmitt trigger.

0x0

od_en_0

Enable open drain.

15:7

Reserved

17:16

0x0

slew_rate_0

Slew rate (0x0: slowest, 0x3: fastest).

19:18

Reserved

23:20

0x0

drive_strength_0

Drive strength (0x0: weakest, 0xf: strongest)

pinmux.MIO_PAD_ATTR_1 @ 0x404

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_1						slew_rate_1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_1	schmitt_en_1	keeper_en_1	pull_select_1	pull_en_1	virtual_od_en_1	invert_1

Bits

Type

Reset

Name

Description

0x0

invert_1

For MIO_PAD1

0x0

virtual_od_en_1

For MIO_PAD1

0x0

pull_en_1

For MIO_PAD1

0x0

pull_select_1

For MIO_PAD1

0x0

keeper_en_1

For MIO_PAD1

0x0

schmitt_en_1

For MIO_PAD1

0x0

od_en_1

For MIO_PAD1

15:7

Reserved

17:16

0x0

slew_rate_1

For MIO_PAD1

19:18

Reserved

23:20

0x0

drive_strength_1

For MIO_PAD1

pinmux.MIO_PAD_ATTR_2 @ 0x408

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_2						slew_rate_2
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_2	schmitt_en_2	keeper_en_2	pull_select_2	pull_en_2	virtual_od_en_2	invert_2

Bits

Type

Reset

Name

Description

0x0

invert_2

For MIO_PAD2

0x0

virtual_od_en_2

For MIO_PAD2

0x0

pull_en_2

For MIO_PAD2

0x0

pull_select_2

For MIO_PAD2

0x0

keeper_en_2

For MIO_PAD2

0x0

schmitt_en_2

For MIO_PAD2

0x0

od_en_2

For MIO_PAD2

15:7

Reserved

17:16

0x0

slew_rate_2

For MIO_PAD2

19:18

Reserved

23:20

0x0

drive_strength_2

For MIO_PAD2

pinmux.MIO_PAD_ATTR_3 @ 0x40c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_3						slew_rate_3
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_3	schmitt_en_3	keeper_en_3	pull_select_3	pull_en_3	virtual_od_en_3	invert_3

Bits

Type

Reset

Name

Description

0x0

invert_3

For MIO_PAD3

0x0

virtual_od_en_3

For MIO_PAD3

0x0

pull_en_3

For MIO_PAD3

0x0

pull_select_3

For MIO_PAD3

0x0

keeper_en_3

For MIO_PAD3

0x0

schmitt_en_3

For MIO_PAD3

0x0

od_en_3

For MIO_PAD3

15:7

Reserved

17:16

0x0

slew_rate_3

For MIO_PAD3

19:18

Reserved

23:20

0x0

drive_strength_3

For MIO_PAD3

pinmux.MIO_PAD_ATTR_4 @ 0x410

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_4						slew_rate_4
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_4	schmitt_en_4	keeper_en_4	pull_select_4	pull_en_4	virtual_od_en_4	invert_4

Bits

Type

Reset

Name

Description

0x0

invert_4

For MIO_PAD4

0x0

virtual_od_en_4

For MIO_PAD4

0x0

pull_en_4

For MIO_PAD4

0x0

pull_select_4

For MIO_PAD4

0x0

keeper_en_4

For MIO_PAD4

0x0

schmitt_en_4

For MIO_PAD4

0x0

od_en_4

For MIO_PAD4

15:7

Reserved

17:16

0x0

slew_rate_4

For MIO_PAD4

19:18

Reserved

23:20

0x0

drive_strength_4

For MIO_PAD4

pinmux.MIO_PAD_ATTR_5 @ 0x414

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_5						slew_rate_5
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_5	schmitt_en_5	keeper_en_5	pull_select_5	pull_en_5	virtual_od_en_5	invert_5

Bits

Type

Reset

Name

Description

0x0

invert_5

For MIO_PAD5

0x0

virtual_od_en_5

For MIO_PAD5

0x0

pull_en_5

For MIO_PAD5

0x0

pull_select_5

For MIO_PAD5

0x0

keeper_en_5

For MIO_PAD5

0x0

schmitt_en_5

For MIO_PAD5

0x0

od_en_5

For MIO_PAD5

15:7

Reserved

17:16

0x0

slew_rate_5

For MIO_PAD5

19:18

Reserved

23:20

0x0

drive_strength_5

For MIO_PAD5

pinmux.MIO_PAD_ATTR_6 @ 0x418

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_6						slew_rate_6
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_6	schmitt_en_6	keeper_en_6	pull_select_6	pull_en_6	virtual_od_en_6	invert_6

Bits

Type

Reset

Name

Description

0x0

invert_6

For MIO_PAD6

0x0

virtual_od_en_6

For MIO_PAD6

0x0

pull_en_6

For MIO_PAD6

0x0

pull_select_6

For MIO_PAD6

0x0

keeper_en_6

For MIO_PAD6

0x0

schmitt_en_6

For MIO_PAD6

0x0

od_en_6

For MIO_PAD6

15:7

Reserved

17:16

0x0

slew_rate_6

For MIO_PAD6

19:18

Reserved

23:20

0x0

drive_strength_6

For MIO_PAD6

pinmux.MIO_PAD_ATTR_7 @ 0x41c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_7						slew_rate_7
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_7	schmitt_en_7	keeper_en_7	pull_select_7	pull_en_7	virtual_od_en_7	invert_7

Bits

Type

Reset

Name

Description

0x0

invert_7

For MIO_PAD7

0x0

virtual_od_en_7

For MIO_PAD7

0x0

pull_en_7

For MIO_PAD7

0x0

pull_select_7

For MIO_PAD7

0x0

keeper_en_7

For MIO_PAD7

0x0

schmitt_en_7

For MIO_PAD7

0x0

od_en_7

For MIO_PAD7

15:7

Reserved

17:16

0x0

slew_rate_7

For MIO_PAD7

19:18

Reserved

23:20

0x0

drive_strength_7

For MIO_PAD7

pinmux.MIO_PAD_ATTR_8 @ 0x420

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_8						slew_rate_8
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_8	schmitt_en_8	keeper_en_8	pull_select_8	pull_en_8	virtual_od_en_8	invert_8

Bits

Type

Reset

Name

Description

0x0

invert_8

For MIO_PAD8

0x0

virtual_od_en_8

For MIO_PAD8

0x0

pull_en_8

For MIO_PAD8

0x0

pull_select_8

For MIO_PAD8

0x0

keeper_en_8

For MIO_PAD8

0x0

schmitt_en_8

For MIO_PAD8

0x0

od_en_8

For MIO_PAD8

15:7

Reserved

17:16

0x0

slew_rate_8

For MIO_PAD8

19:18

Reserved

23:20

0x0

drive_strength_8

For MIO_PAD8

pinmux.MIO_PAD_ATTR_9 @ 0x424

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_9						slew_rate_9
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_9	schmitt_en_9	keeper_en_9	pull_select_9	pull_en_9	virtual_od_en_9	invert_9

Bits

Type

Reset

Name

Description

0x0

invert_9

For MIO_PAD9

0x0

virtual_od_en_9

For MIO_PAD9

0x0

pull_en_9

For MIO_PAD9

0x0

pull_select_9

For MIO_PAD9

0x0

keeper_en_9

For MIO_PAD9

0x0

schmitt_en_9

For MIO_PAD9

0x0

od_en_9

For MIO_PAD9

15:7

Reserved

17:16

0x0

slew_rate_9

For MIO_PAD9

19:18

Reserved

23:20

0x0

drive_strength_9

For MIO_PAD9

pinmux.MIO_PAD_ATTR_10 @ 0x428

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_10						slew_rate_10
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_10	schmitt_en_10	keeper_en_10	pull_select_10	pull_en_10	virtual_od_en_10	invert_10

Bits

Type

Reset

Name

Description

0x0

invert_10

For MIO_PAD10

0x0

virtual_od_en_10

For MIO_PAD10

0x0

pull_en_10

For MIO_PAD10

0x0

pull_select_10

For MIO_PAD10

0x0

keeper_en_10

For MIO_PAD10

0x0

schmitt_en_10

For MIO_PAD10

0x0

od_en_10

For MIO_PAD10

15:7

Reserved

17:16

0x0

slew_rate_10

For MIO_PAD10

19:18

Reserved

23:20

0x0

drive_strength_10

For MIO_PAD10

pinmux.MIO_PAD_ATTR_11 @ 0x42c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_11						slew_rate_11
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_11	schmitt_en_11	keeper_en_11	pull_select_11	pull_en_11	virtual_od_en_11	invert_11

Bits

Type

Reset

Name

Description

0x0

invert_11

For MIO_PAD11

0x0

virtual_od_en_11

For MIO_PAD11

0x0

pull_en_11

For MIO_PAD11

0x0

pull_select_11

For MIO_PAD11

0x0

keeper_en_11

For MIO_PAD11

0x0

schmitt_en_11

For MIO_PAD11

0x0

od_en_11

For MIO_PAD11

15:7

Reserved

17:16

0x0

slew_rate_11

For MIO_PAD11

19:18

Reserved

23:20

0x0

drive_strength_11

For MIO_PAD11

pinmux.MIO_PAD_ATTR_12 @ 0x430

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_12						slew_rate_12
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_12	schmitt_en_12	keeper_en_12	pull_select_12	pull_en_12	virtual_od_en_12	invert_12

Bits

Type

Reset

Name

Description

0x0

invert_12

For MIO_PAD12

0x0

virtual_od_en_12

For MIO_PAD12

0x0

pull_en_12

For MIO_PAD12

0x0

pull_select_12

For MIO_PAD12

0x0

keeper_en_12

For MIO_PAD12

0x0

schmitt_en_12

For MIO_PAD12

0x0

od_en_12

For MIO_PAD12

15:7

Reserved

17:16

0x0

slew_rate_12

For MIO_PAD12

19:18

Reserved

23:20

0x0

drive_strength_12

For MIO_PAD12

pinmux.MIO_PAD_ATTR_13 @ 0x434

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_13						slew_rate_13
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_13	schmitt_en_13	keeper_en_13	pull_select_13	pull_en_13	virtual_od_en_13	invert_13

Bits

Type

Reset

Name

Description

0x0

invert_13

For MIO_PAD13

0x0

virtual_od_en_13

For MIO_PAD13

0x0

pull_en_13

For MIO_PAD13

0x0

pull_select_13

For MIO_PAD13

0x0

keeper_en_13

For MIO_PAD13

0x0

schmitt_en_13

For MIO_PAD13

0x0

od_en_13

For MIO_PAD13

15:7

Reserved

17:16

0x0

slew_rate_13

For MIO_PAD13

19:18

Reserved

23:20

0x0

drive_strength_13

For MIO_PAD13

pinmux.MIO_PAD_ATTR_14 @ 0x438

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_14						slew_rate_14
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_14	schmitt_en_14	keeper_en_14	pull_select_14	pull_en_14	virtual_od_en_14	invert_14

Bits

Type

Reset

Name

Description

0x0

invert_14

For MIO_PAD14

0x0

virtual_od_en_14

For MIO_PAD14

0x0

pull_en_14

For MIO_PAD14

0x0

pull_select_14

For MIO_PAD14

0x0

keeper_en_14

For MIO_PAD14

0x0

schmitt_en_14

For MIO_PAD14

0x0

od_en_14

For MIO_PAD14

15:7

Reserved

17:16

0x0

slew_rate_14

For MIO_PAD14

19:18

Reserved

23:20

0x0

drive_strength_14

For MIO_PAD14

pinmux.MIO_PAD_ATTR_15 @ 0x43c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_15						slew_rate_15
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_15	schmitt_en_15	keeper_en_15	pull_select_15	pull_en_15	virtual_od_en_15	invert_15

Bits

Type

Reset

Name

Description

0x0

invert_15

For MIO_PAD15

0x0

virtual_od_en_15

For MIO_PAD15

0x0

pull_en_15

For MIO_PAD15

0x0

pull_select_15

For MIO_PAD15

0x0

keeper_en_15

For MIO_PAD15

0x0

schmitt_en_15

For MIO_PAD15

0x0

od_en_15

For MIO_PAD15

15:7

Reserved

17:16

0x0

slew_rate_15

For MIO_PAD15

19:18

Reserved

23:20

0x0

drive_strength_15

For MIO_PAD15

pinmux.MIO_PAD_ATTR_16 @ 0x440

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_16						slew_rate_16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_16	schmitt_en_16	keeper_en_16	pull_select_16	pull_en_16	virtual_od_en_16	invert_16

Bits

Type

Reset

Name

Description

0x0

invert_16

For MIO_PAD16

0x0

virtual_od_en_16

For MIO_PAD16

0x0

pull_en_16

For MIO_PAD16

0x0

pull_select_16

For MIO_PAD16

0x0

keeper_en_16

For MIO_PAD16

0x0

schmitt_en_16

For MIO_PAD16

0x0

od_en_16

For MIO_PAD16

15:7

Reserved

17:16

0x0

slew_rate_16

For MIO_PAD16

19:18

Reserved

23:20

0x0

drive_strength_16

For MIO_PAD16

pinmux.MIO_PAD_ATTR_17 @ 0x444

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_17						slew_rate_17
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_17	schmitt_en_17	keeper_en_17	pull_select_17	pull_en_17	virtual_od_en_17	invert_17

Bits

Type

Reset

Name

Description

0x0

invert_17

For MIO_PAD17

0x0

virtual_od_en_17

For MIO_PAD17

0x0

pull_en_17

For MIO_PAD17

0x0

pull_select_17

For MIO_PAD17

0x0

keeper_en_17

For MIO_PAD17

0x0

schmitt_en_17

For MIO_PAD17

0x0

od_en_17

For MIO_PAD17

15:7

Reserved

17:16

0x0

slew_rate_17

For MIO_PAD17

19:18

Reserved

23:20

0x0

drive_strength_17

For MIO_PAD17

pinmux.MIO_PAD_ATTR_18 @ 0x448

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_18						slew_rate_18
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_18	schmitt_en_18	keeper_en_18	pull_select_18	pull_en_18	virtual_od_en_18	invert_18

Bits

Type

Reset

Name

Description

0x0

invert_18

For MIO_PAD18

0x0

virtual_od_en_18

For MIO_PAD18

0x0

pull_en_18

For MIO_PAD18

0x0

pull_select_18

For MIO_PAD18

0x0

keeper_en_18

For MIO_PAD18

0x0

schmitt_en_18

For MIO_PAD18

0x0

od_en_18

For MIO_PAD18

15:7

Reserved

17:16

0x0

slew_rate_18

For MIO_PAD18

19:18

Reserved

23:20

0x0

drive_strength_18

For MIO_PAD18

pinmux.MIO_PAD_ATTR_19 @ 0x44c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_19						slew_rate_19
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_19	schmitt_en_19	keeper_en_19	pull_select_19	pull_en_19	virtual_od_en_19	invert_19

Bits

Type

Reset

Name

Description

0x0

invert_19

For MIO_PAD19

0x0

virtual_od_en_19

For MIO_PAD19

0x0

pull_en_19

For MIO_PAD19

0x0

pull_select_19

For MIO_PAD19

0x0

keeper_en_19

For MIO_PAD19

0x0

schmitt_en_19

For MIO_PAD19

0x0

od_en_19

For MIO_PAD19

15:7

Reserved

17:16

0x0

slew_rate_19

For MIO_PAD19

19:18

Reserved

23:20

0x0

drive_strength_19

For MIO_PAD19

pinmux.MIO_PAD_ATTR_20 @ 0x450

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_20						slew_rate_20
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_20	schmitt_en_20	keeper_en_20	pull_select_20	pull_en_20	virtual_od_en_20	invert_20

Bits

Type

Reset

Name

Description

0x0

invert_20

For MIO_PAD20

0x0

virtual_od_en_20

For MIO_PAD20

0x0

pull_en_20

For MIO_PAD20

0x0

pull_select_20

For MIO_PAD20

0x0

keeper_en_20

For MIO_PAD20

0x0

schmitt_en_20

For MIO_PAD20

0x0

od_en_20

For MIO_PAD20

15:7

Reserved

17:16

0x0

slew_rate_20

For MIO_PAD20

19:18

Reserved

23:20

0x0

drive_strength_20

For MIO_PAD20

pinmux.MIO_PAD_ATTR_21 @ 0x454

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_21						slew_rate_21
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_21	schmitt_en_21	keeper_en_21	pull_select_21	pull_en_21	virtual_od_en_21	invert_21

Bits

Type

Reset

Name

Description

0x0

invert_21

For MIO_PAD21

0x0

virtual_od_en_21

For MIO_PAD21

0x0

pull_en_21

For MIO_PAD21

0x0

pull_select_21

For MIO_PAD21

0x0

keeper_en_21

For MIO_PAD21

0x0

schmitt_en_21

For MIO_PAD21

0x0

od_en_21

For MIO_PAD21

15:7

Reserved

17:16

0x0

slew_rate_21

For MIO_PAD21

19:18

Reserved

23:20

0x0

drive_strength_21

For MIO_PAD21

pinmux.MIO_PAD_ATTR_22 @ 0x458

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_22						slew_rate_22
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_22	schmitt_en_22	keeper_en_22	pull_select_22	pull_en_22	virtual_od_en_22	invert_22

Bits

Type

Reset

Name

Description

0x0

invert_22

For MIO_PAD22

0x0

virtual_od_en_22

For MIO_PAD22

0x0

pull_en_22

For MIO_PAD22

0x0

pull_select_22

For MIO_PAD22

0x0

keeper_en_22

For MIO_PAD22

0x0

schmitt_en_22

For MIO_PAD22

0x0

od_en_22

For MIO_PAD22

15:7

Reserved

17:16

0x0

slew_rate_22

For MIO_PAD22

19:18

Reserved

23:20

0x0

drive_strength_22

For MIO_PAD22

pinmux.MIO_PAD_ATTR_23 @ 0x45c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_23						slew_rate_23
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_23	schmitt_en_23	keeper_en_23	pull_select_23	pull_en_23	virtual_od_en_23	invert_23

Bits

Type

Reset

Name

Description

0x0

invert_23

For MIO_PAD23

0x0

virtual_od_en_23

For MIO_PAD23

0x0

pull_en_23

For MIO_PAD23

0x0

pull_select_23

For MIO_PAD23

0x0

keeper_en_23

For MIO_PAD23

0x0

schmitt_en_23

For MIO_PAD23

0x0

od_en_23

For MIO_PAD23

15:7

Reserved

17:16

0x0

slew_rate_23

For MIO_PAD23

19:18

Reserved

23:20

0x0

drive_strength_23

For MIO_PAD23

pinmux.MIO_PAD_ATTR_24 @ 0x460

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_24						slew_rate_24
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_24	schmitt_en_24	keeper_en_24	pull_select_24	pull_en_24	virtual_od_en_24	invert_24

Bits

Type

Reset

Name

Description

0x0

invert_24

For MIO_PAD24

0x0

virtual_od_en_24

For MIO_PAD24

0x0

pull_en_24

For MIO_PAD24

0x0

pull_select_24

For MIO_PAD24

0x0

keeper_en_24

For MIO_PAD24

0x0

schmitt_en_24

For MIO_PAD24

0x0

od_en_24

For MIO_PAD24

15:7

Reserved

17:16

0x0

slew_rate_24

For MIO_PAD24

19:18

Reserved

23:20

0x0

drive_strength_24

For MIO_PAD24

pinmux.MIO_PAD_ATTR_25 @ 0x464

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_25						slew_rate_25
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_25	schmitt_en_25	keeper_en_25	pull_select_25	pull_en_25	virtual_od_en_25	invert_25

Bits

Type

Reset

Name

Description

0x0

invert_25

For MIO_PAD25

0x0

virtual_od_en_25

For MIO_PAD25

0x0

pull_en_25

For MIO_PAD25

0x0

pull_select_25

For MIO_PAD25

0x0

keeper_en_25

For MIO_PAD25

0x0

schmitt_en_25

For MIO_PAD25

0x0

od_en_25

For MIO_PAD25

15:7

Reserved

17:16

0x0

slew_rate_25

For MIO_PAD25

19:18

Reserved

23:20

0x0

drive_strength_25

For MIO_PAD25

pinmux.MIO_PAD_ATTR_26 @ 0x468

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_26						slew_rate_26
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_26	schmitt_en_26	keeper_en_26	pull_select_26	pull_en_26	virtual_od_en_26	invert_26

Bits

Type

Reset

Name

Description

0x0

invert_26

For MIO_PAD26

0x0

virtual_od_en_26

For MIO_PAD26

0x0

pull_en_26

For MIO_PAD26

0x0

pull_select_26

For MIO_PAD26

0x0

keeper_en_26

For MIO_PAD26

0x0

schmitt_en_26

For MIO_PAD26

0x0

od_en_26

For MIO_PAD26

15:7

Reserved

17:16

0x0

slew_rate_26

For MIO_PAD26

19:18

Reserved

23:20

0x0

drive_strength_26

For MIO_PAD26

pinmux.MIO_PAD_ATTR_27 @ 0x46c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_27						slew_rate_27
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_27	schmitt_en_27	keeper_en_27	pull_select_27	pull_en_27	virtual_od_en_27	invert_27

Bits

Type

Reset

Name

Description

0x0

invert_27

For MIO_PAD27

0x0

virtual_od_en_27

For MIO_PAD27

0x0

pull_en_27

For MIO_PAD27

0x0

pull_select_27

For MIO_PAD27

0x0

keeper_en_27

For MIO_PAD27

0x0

schmitt_en_27

For MIO_PAD27

0x0

od_en_27

For MIO_PAD27

15:7

Reserved

17:16

0x0

slew_rate_27

For MIO_PAD27

19:18

Reserved

23:20

0x0

drive_strength_27

For MIO_PAD27

pinmux.MIO_PAD_ATTR_28 @ 0x470

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_28						slew_rate_28
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_28	schmitt_en_28	keeper_en_28	pull_select_28	pull_en_28	virtual_od_en_28	invert_28

Bits

Type

Reset

Name

Description

0x0

invert_28

For MIO_PAD28

0x0

virtual_od_en_28

For MIO_PAD28

0x0

pull_en_28

For MIO_PAD28

0x0

pull_select_28

For MIO_PAD28

0x0

keeper_en_28

For MIO_PAD28

0x0

schmitt_en_28

For MIO_PAD28

0x0

od_en_28

For MIO_PAD28

15:7

Reserved

17:16

0x0

slew_rate_28

For MIO_PAD28

19:18

Reserved

23:20

0x0

drive_strength_28

For MIO_PAD28

pinmux.MIO_PAD_ATTR_29 @ 0x474

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_29						slew_rate_29
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_29	schmitt_en_29	keeper_en_29	pull_select_29	pull_en_29	virtual_od_en_29	invert_29

Bits

Type

Reset

Name

Description

0x0

invert_29

For MIO_PAD29

0x0

virtual_od_en_29

For MIO_PAD29

0x0

pull_en_29

For MIO_PAD29

0x0

pull_select_29

For MIO_PAD29

0x0

keeper_en_29

For MIO_PAD29

0x0

schmitt_en_29

For MIO_PAD29

0x0

od_en_29

For MIO_PAD29

15:7

Reserved

17:16

0x0

slew_rate_29

For MIO_PAD29

19:18

Reserved

23:20

0x0

drive_strength_29

For MIO_PAD29

pinmux.MIO_PAD_ATTR_30 @ 0x478

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_30						slew_rate_30
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_30	schmitt_en_30	keeper_en_30	pull_select_30	pull_en_30	virtual_od_en_30	invert_30

Bits

Type

Reset

Name

Description

0x0

invert_30

For MIO_PAD30

0x0

virtual_od_en_30

For MIO_PAD30

0x0

pull_en_30

For MIO_PAD30

0x0

pull_select_30

For MIO_PAD30

0x0

keeper_en_30

For MIO_PAD30

0x0

schmitt_en_30

For MIO_PAD30

0x0

od_en_30

For MIO_PAD30

15:7

Reserved

17:16

0x0

slew_rate_30

For MIO_PAD30

19:18

Reserved

23:20

0x0

drive_strength_30

For MIO_PAD30

pinmux.MIO_PAD_ATTR_31 @ 0x47c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_31						slew_rate_31
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_31	schmitt_en_31	keeper_en_31	pull_select_31	pull_en_31	virtual_od_en_31	invert_31

Bits

Type

Reset

Name

Description

0x0

invert_31

For MIO_PAD31

0x0

virtual_od_en_31

For MIO_PAD31

0x0

pull_en_31

For MIO_PAD31

0x0

pull_select_31

For MIO_PAD31

0x0

keeper_en_31

For MIO_PAD31

0x0

schmitt_en_31

For MIO_PAD31

0x0

od_en_31

For MIO_PAD31

15:7

Reserved

17:16

0x0

slew_rate_31

For MIO_PAD31

19:18

Reserved

23:20

0x0

drive_strength_31

For MIO_PAD31

pinmux.MIO_PAD_ATTR_32 @ 0x480

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_32						slew_rate_32
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_32	schmitt_en_32	keeper_en_32	pull_select_32	pull_en_32	virtual_od_en_32	invert_32

Bits

Type

Reset

Name

Description

0x0

invert_32

For MIO_PAD32

0x0

virtual_od_en_32

For MIO_PAD32

0x0

pull_en_32

For MIO_PAD32

0x0

pull_select_32

For MIO_PAD32

0x0

keeper_en_32

For MIO_PAD32

0x0

schmitt_en_32

For MIO_PAD32

0x0

od_en_32

For MIO_PAD32

15:7

Reserved

17:16

0x0

slew_rate_32

For MIO_PAD32

19:18

Reserved

23:20

0x0

drive_strength_32

For MIO_PAD32

pinmux.MIO_PAD_ATTR_33 @ 0x484

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_33						slew_rate_33
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_33	schmitt_en_33	keeper_en_33	pull_select_33	pull_en_33	virtual_od_en_33	invert_33

Bits

Type

Reset

Name

Description

0x0

invert_33

For MIO_PAD33

0x0

virtual_od_en_33

For MIO_PAD33

0x0

pull_en_33

For MIO_PAD33

0x0

pull_select_33

For MIO_PAD33

0x0

keeper_en_33

For MIO_PAD33

0x0

schmitt_en_33

For MIO_PAD33

0x0

od_en_33

For MIO_PAD33

15:7

Reserved

17:16

0x0

slew_rate_33

For MIO_PAD33

19:18

Reserved

23:20

0x0

drive_strength_33

For MIO_PAD33

pinmux.MIO_PAD_ATTR_34 @ 0x488

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_34						slew_rate_34
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_34	schmitt_en_34	keeper_en_34	pull_select_34	pull_en_34	virtual_od_en_34	invert_34

Bits

Type

Reset

Name

Description

0x0

invert_34

For MIO_PAD34

0x0

virtual_od_en_34

For MIO_PAD34

0x0

pull_en_34

For MIO_PAD34

0x0

pull_select_34

For MIO_PAD34

0x0

keeper_en_34

For MIO_PAD34

0x0

schmitt_en_34

For MIO_PAD34

0x0

od_en_34

For MIO_PAD34

15:7

Reserved

17:16

0x0

slew_rate_34

For MIO_PAD34

19:18

Reserved

23:20

0x0

drive_strength_34

For MIO_PAD34

pinmux.MIO_PAD_ATTR_35 @ 0x48c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_35						slew_rate_35
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_35	schmitt_en_35	keeper_en_35	pull_select_35	pull_en_35	virtual_od_en_35	invert_35

Bits

Type

Reset

Name

Description

0x0

invert_35

For MIO_PAD35

0x0

virtual_od_en_35

For MIO_PAD35

0x0

pull_en_35

For MIO_PAD35

0x0

pull_select_35

For MIO_PAD35

0x0

keeper_en_35

For MIO_PAD35

0x0

schmitt_en_35

For MIO_PAD35

0x0

od_en_35

For MIO_PAD35

15:7

Reserved

17:16

0x0

slew_rate_35

For MIO_PAD35

19:18

Reserved

23:20

0x0

drive_strength_35

For MIO_PAD35

pinmux.MIO_PAD_ATTR_36 @ 0x490

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_36						slew_rate_36
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_36	schmitt_en_36	keeper_en_36	pull_select_36	pull_en_36	virtual_od_en_36	invert_36

Bits

Type

Reset

Name

Description

0x0

invert_36

For MIO_PAD36

0x0

virtual_od_en_36

For MIO_PAD36

0x0

pull_en_36

For MIO_PAD36

0x0

pull_select_36

For MIO_PAD36

0x0

keeper_en_36

For MIO_PAD36

0x0

schmitt_en_36

For MIO_PAD36

0x0

od_en_36

For MIO_PAD36

15:7

Reserved

17:16

0x0

slew_rate_36

For MIO_PAD36

19:18

Reserved

23:20

0x0

drive_strength_36

For MIO_PAD36

pinmux.MIO_PAD_ATTR_37 @ 0x494

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_37						slew_rate_37
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_37	schmitt_en_37	keeper_en_37	pull_select_37	pull_en_37	virtual_od_en_37	invert_37

Bits

Type

Reset

Name

Description

0x0

invert_37

For MIO_PAD37

0x0

virtual_od_en_37

For MIO_PAD37

0x0

pull_en_37

For MIO_PAD37

0x0

pull_select_37

For MIO_PAD37

0x0

keeper_en_37

For MIO_PAD37

0x0

schmitt_en_37

For MIO_PAD37

0x0

od_en_37

For MIO_PAD37

15:7

Reserved

17:16

0x0

slew_rate_37

For MIO_PAD37

19:18

Reserved

23:20

0x0

drive_strength_37

For MIO_PAD37

pinmux.MIO_PAD_ATTR_38 @ 0x498

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_38						slew_rate_38
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_38	schmitt_en_38	keeper_en_38	pull_select_38	pull_en_38	virtual_od_en_38	invert_38

Bits

Type

Reset

Name

Description

0x0

invert_38

For MIO_PAD38

0x0

virtual_od_en_38

For MIO_PAD38

0x0

pull_en_38

For MIO_PAD38

0x0

pull_select_38

For MIO_PAD38

0x0

keeper_en_38

For MIO_PAD38

0x0

schmitt_en_38

For MIO_PAD38

0x0

od_en_38

For MIO_PAD38

15:7

Reserved

17:16

0x0

slew_rate_38

For MIO_PAD38

19:18

Reserved

23:20

0x0

drive_strength_38

For MIO_PAD38

pinmux.MIO_PAD_ATTR_39 @ 0x49c

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_39						slew_rate_39
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_39	schmitt_en_39	keeper_en_39	pull_select_39	pull_en_39	virtual_od_en_39	invert_39

Bits

Type

Reset

Name

Description

0x0

invert_39

For MIO_PAD39

0x0

virtual_od_en_39

For MIO_PAD39

0x0

pull_en_39

For MIO_PAD39

0x0

pull_select_39

For MIO_PAD39

0x0

keeper_en_39

For MIO_PAD39

0x0

schmitt_en_39

For MIO_PAD39

0x0

od_en_39

For MIO_PAD39

15:7

Reserved

17:16

0x0

slew_rate_39

For MIO_PAD39

19:18

Reserved

23:20

0x0

drive_strength_39

For MIO_PAD39

pinmux.MIO_PAD_ATTR_40 @ 0x4a0

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_40						slew_rate_40
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_40	schmitt_en_40	keeper_en_40	pull_select_40	pull_en_40	virtual_od_en_40	invert_40

Bits

Type

Reset

Name

Description

0x0

invert_40

For MIO_PAD40

0x0

virtual_od_en_40

For MIO_PAD40

0x0

pull_en_40

For MIO_PAD40

0x0

pull_select_40

For MIO_PAD40

0x0

keeper_en_40

For MIO_PAD40

0x0

schmitt_en_40

For MIO_PAD40

0x0

od_en_40

For MIO_PAD40

15:7

Reserved

17:16

0x0

slew_rate_40

For MIO_PAD40

19:18

Reserved

23:20

0x0

drive_strength_40

For MIO_PAD40

pinmux.MIO_PAD_ATTR_41 @ 0x4a4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_41						slew_rate_41
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_41	schmitt_en_41	keeper_en_41	pull_select_41	pull_en_41	virtual_od_en_41	invert_41

Bits

Type

Reset

Name

Description

0x0

invert_41

For MIO_PAD41

0x0

virtual_od_en_41

For MIO_PAD41

0x0

pull_en_41

For MIO_PAD41

0x0

pull_select_41

For MIO_PAD41

0x0

keeper_en_41

For MIO_PAD41

0x0

schmitt_en_41

For MIO_PAD41

0x0

od_en_41

For MIO_PAD41

15:7

Reserved

17:16

0x0

slew_rate_41

For MIO_PAD41

19:18

Reserved

23:20

0x0

drive_strength_41

For MIO_PAD41

pinmux.MIO_PAD_ATTR_42 @ 0x4a8

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_42						slew_rate_42
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_42	schmitt_en_42	keeper_en_42	pull_select_42	pull_en_42	virtual_od_en_42	invert_42

Bits

Type

Reset

Name

Description

0x0

invert_42

For MIO_PAD42

0x0

virtual_od_en_42

For MIO_PAD42

0x0

pull_en_42

For MIO_PAD42

0x0

pull_select_42

For MIO_PAD42

0x0

keeper_en_42

For MIO_PAD42

0x0

schmitt_en_42

For MIO_PAD42

0x0

od_en_42

For MIO_PAD42

15:7

Reserved

17:16

0x0

slew_rate_42

For MIO_PAD42

19:18

Reserved

23:20

0x0

drive_strength_42

For MIO_PAD42

pinmux.MIO_PAD_ATTR_43 @ 0x4ac

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_43						slew_rate_43
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_43	schmitt_en_43	keeper_en_43	pull_select_43	pull_en_43	virtual_od_en_43	invert_43

Bits

Type

Reset

Name

Description

0x0

invert_43

For MIO_PAD43

0x0

virtual_od_en_43

For MIO_PAD43

0x0

pull_en_43

For MIO_PAD43

0x0

pull_select_43

For MIO_PAD43

0x0

keeper_en_43

For MIO_PAD43

0x0

schmitt_en_43

For MIO_PAD43

0x0

od_en_43

For MIO_PAD43

15:7

Reserved

17:16

0x0

slew_rate_43

For MIO_PAD43

19:18

Reserved

23:20

0x0

drive_strength_43

For MIO_PAD43

pinmux.MIO_PAD_ATTR_44 @ 0x4b0

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_44						slew_rate_44
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_44	schmitt_en_44	keeper_en_44	pull_select_44	pull_en_44	virtual_od_en_44	invert_44

Bits

Type

Reset

Name

Description

0x0

invert_44

For MIO_PAD44

0x0

virtual_od_en_44

For MIO_PAD44

0x0

pull_en_44

For MIO_PAD44

0x0

pull_select_44

For MIO_PAD44

0x0

keeper_en_44

For MIO_PAD44

0x0

schmitt_en_44

For MIO_PAD44

0x0

od_en_44

For MIO_PAD44

15:7

Reserved

17:16

0x0

slew_rate_44

For MIO_PAD44

19:18

Reserved

23:20

0x0

drive_strength_44

For MIO_PAD44

pinmux.MIO_PAD_ATTR_45 @ 0x4b4

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_45						slew_rate_45
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_45	schmitt_en_45	keeper_en_45	pull_select_45	pull_en_45	virtual_od_en_45	invert_45

Bits

Type

Reset

Name

Description

0x0

invert_45

For MIO_PAD45

0x0

virtual_od_en_45

For MIO_PAD45

0x0

pull_en_45

For MIO_PAD45

0x0

pull_select_45

For MIO_PAD45

0x0

keeper_en_45

For MIO_PAD45

0x0

schmitt_en_45

For MIO_PAD45

0x0

od_en_45

For MIO_PAD45

15:7

Reserved

17:16

0x0

slew_rate_45

For MIO_PAD45

19:18

Reserved

23:20

0x0

drive_strength_45

For MIO_PAD45

pinmux.MIO_PAD_ATTR_46 @ 0x4b8

Muxed pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_46						slew_rate_46
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_46	schmitt_en_46	keeper_en_46	pull_select_46	pull_en_46	virtual_od_en_46	invert_46

Bits

Type

Reset

Name

Description

0x0

invert_46

For MIO_PAD46

0x0

virtual_od_en_46

For MIO_PAD46

0x0

pull_en_46

For MIO_PAD46

0x0

pull_select_46

For MIO_PAD46

0x0

keeper_en_46

For MIO_PAD46

0x0

schmitt_en_46

For MIO_PAD46

0x0

od_en_46

For MIO_PAD46

15:7

Reserved

17:16

0x0

slew_rate_46

For MIO_PAD46

19:18

Reserved

23:20

0x0

drive_strength_46

For MIO_PAD46

pinmux.DIO_PAD_ATTR_REGWEN_0 @ 0x4bc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits Type Reset Name Description

rw0c

0x1

EN_0

pinmux.DIO_PAD_ATTR_REGWEN_1 @ 0x4c0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For DIO_PAD1

pinmux.DIO_PAD_ATTR_REGWEN_2 @ 0x4c4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For DIO_PAD2

pinmux.DIO_PAD_ATTR_REGWEN_3 @ 0x4c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For DIO_PAD3

pinmux.DIO_PAD_ATTR_REGWEN_4 @ 0x4cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For DIO_PAD4

pinmux.DIO_PAD_ATTR_REGWEN_5 @ 0x4d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For DIO_PAD5

pinmux.DIO_PAD_ATTR_REGWEN_6 @ 0x4d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For DIO_PAD6

pinmux.DIO_PAD_ATTR_REGWEN_7 @ 0x4d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For DIO_PAD7

pinmux.DIO_PAD_ATTR_REGWEN_8 @ 0x4dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For DIO_PAD8

pinmux.DIO_PAD_ATTR_REGWEN_9 @ 0x4e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For DIO_PAD9

pinmux.DIO_PAD_ATTR_REGWEN_10 @ 0x4e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For DIO_PAD10

pinmux.DIO_PAD_ATTR_REGWEN_11 @ 0x4e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For DIO_PAD11

pinmux.DIO_PAD_ATTR_REGWEN_12 @ 0x4ec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For DIO_PAD12

pinmux.DIO_PAD_ATTR_REGWEN_13 @ 0x4f0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For DIO_PAD13

pinmux.DIO_PAD_ATTR_REGWEN_14 @ 0x4f4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For DIO_PAD14

pinmux.DIO_PAD_ATTR_REGWEN_15 @ 0x4f8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For DIO_PAD15

pinmux.DIO_PAD_ATTR_0 @ 0x4fc

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_0						slew_rate_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_0	schmitt_en_0	keeper_en_0	pull_select_0	pull_en_0	virtual_od_en_0	invert_0

Bits

Type

Reset

Name

Description

0x0

invert_0

Invert input and output levels.

0x0

virtual_od_en_0

Enable virtual open drain.

0x0

pull_en_0

Enable pull-up or pull-down resistor.

0x0

pull_select_0

Pull select (0: pull-down, 1: pull-up).

0x0	pull_down	Select the pull-down resistor.
0x1	pull_up	Select the pull-up resistor.

0x0

keeper_en_0

Enable pull-up or pull-down resistor.

0x0

schmitt_en_0

Enable the schmitt trigger.

0x0

od_en_0

Enable open drain.

15:7

Reserved

17:16

0x0

slew_rate_0

Slew rate (0x0: slowest, 0x3: fastest).

19:18

Reserved

23:20

0x0

drive_strength_0

Drive strength (0x0: weakest, 0xf: strongest)

pinmux.DIO_PAD_ATTR_1 @ 0x500

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_1						slew_rate_1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_1	schmitt_en_1	keeper_en_1	pull_select_1	pull_en_1	virtual_od_en_1	invert_1

Bits

Type

Reset

Name

Description

0x0

invert_1

For DIO_PAD1

0x0

virtual_od_en_1

For DIO_PAD1

0x0

pull_en_1

For DIO_PAD1

0x0

pull_select_1

For DIO_PAD1

0x0

keeper_en_1

For DIO_PAD1

0x0

schmitt_en_1

For DIO_PAD1

0x0

od_en_1

For DIO_PAD1

15:7

Reserved

17:16

0x0

slew_rate_1

For DIO_PAD1

19:18

Reserved

23:20

0x0

drive_strength_1

For DIO_PAD1

pinmux.DIO_PAD_ATTR_2 @ 0x504

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_2						slew_rate_2
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_2	schmitt_en_2	keeper_en_2	pull_select_2	pull_en_2	virtual_od_en_2	invert_2

Bits

Type

Reset

Name

Description

0x0

invert_2

For DIO_PAD2

0x0

virtual_od_en_2

For DIO_PAD2

0x0

pull_en_2

For DIO_PAD2

0x0

pull_select_2

For DIO_PAD2

0x0

keeper_en_2

For DIO_PAD2

0x0

schmitt_en_2

For DIO_PAD2

0x0

od_en_2

For DIO_PAD2

15:7

Reserved

17:16

0x0

slew_rate_2

For DIO_PAD2

19:18

Reserved

23:20

0x0

drive_strength_2

For DIO_PAD2

pinmux.DIO_PAD_ATTR_3 @ 0x508

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_3						slew_rate_3
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_3	schmitt_en_3	keeper_en_3	pull_select_3	pull_en_3	virtual_od_en_3	invert_3

Bits

Type

Reset

Name

Description

0x0

invert_3

For DIO_PAD3

0x0

virtual_od_en_3

For DIO_PAD3

0x0

pull_en_3

For DIO_PAD3

0x0

pull_select_3

For DIO_PAD3

0x0

keeper_en_3

For DIO_PAD3

0x0

schmitt_en_3

For DIO_PAD3

0x0

od_en_3

For DIO_PAD3

15:7

Reserved

17:16

0x0

slew_rate_3

For DIO_PAD3

19:18

Reserved

23:20

0x0

drive_strength_3

For DIO_PAD3

pinmux.DIO_PAD_ATTR_4 @ 0x50c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_4						slew_rate_4
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_4	schmitt_en_4	keeper_en_4	pull_select_4	pull_en_4	virtual_od_en_4	invert_4

Bits

Type

Reset

Name

Description

0x0

invert_4

For DIO_PAD4

0x0

virtual_od_en_4

For DIO_PAD4

0x0

pull_en_4

For DIO_PAD4

0x0

pull_select_4

For DIO_PAD4

0x0

keeper_en_4

For DIO_PAD4

0x0

schmitt_en_4

For DIO_PAD4

0x0

od_en_4

For DIO_PAD4

15:7

Reserved

17:16

0x0

slew_rate_4

For DIO_PAD4

19:18

Reserved

23:20

0x0

drive_strength_4

For DIO_PAD4

pinmux.DIO_PAD_ATTR_5 @ 0x510

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_5						slew_rate_5
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_5	schmitt_en_5	keeper_en_5	pull_select_5	pull_en_5	virtual_od_en_5	invert_5

Bits

Type

Reset

Name

Description

0x0

invert_5

For DIO_PAD5

0x0

virtual_od_en_5

For DIO_PAD5

0x0

pull_en_5

For DIO_PAD5

0x0

pull_select_5

For DIO_PAD5

0x0

keeper_en_5

For DIO_PAD5

0x0

schmitt_en_5

For DIO_PAD5

0x0

od_en_5

For DIO_PAD5

15:7

Reserved

17:16

0x0

slew_rate_5

For DIO_PAD5

19:18

Reserved

23:20

0x0

drive_strength_5

For DIO_PAD5

pinmux.DIO_PAD_ATTR_6 @ 0x514

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_6						slew_rate_6
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_6	schmitt_en_6	keeper_en_6	pull_select_6	pull_en_6	virtual_od_en_6	invert_6

Bits

Type

Reset

Name

Description

0x0

invert_6

For DIO_PAD6

0x0

virtual_od_en_6

For DIO_PAD6

0x0

pull_en_6

For DIO_PAD6

0x0

pull_select_6

For DIO_PAD6

0x0

keeper_en_6

For DIO_PAD6

0x0

schmitt_en_6

For DIO_PAD6

0x0

od_en_6

For DIO_PAD6

15:7

Reserved

17:16

0x0

slew_rate_6

For DIO_PAD6

19:18

Reserved

23:20

0x0

drive_strength_6

For DIO_PAD6

pinmux.DIO_PAD_ATTR_7 @ 0x518

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_7						slew_rate_7
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_7	schmitt_en_7	keeper_en_7	pull_select_7	pull_en_7	virtual_od_en_7	invert_7

Bits

Type

Reset

Name

Description

0x0

invert_7

For DIO_PAD7

0x0

virtual_od_en_7

For DIO_PAD7

0x0

pull_en_7

For DIO_PAD7

0x0

pull_select_7

For DIO_PAD7

0x0

keeper_en_7

For DIO_PAD7

0x0

schmitt_en_7

For DIO_PAD7

0x0

od_en_7

For DIO_PAD7

15:7

Reserved

17:16

0x0

slew_rate_7

For DIO_PAD7

19:18

Reserved

23:20

0x0

drive_strength_7

For DIO_PAD7

pinmux.DIO_PAD_ATTR_8 @ 0x51c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_8						slew_rate_8
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_8	schmitt_en_8	keeper_en_8	pull_select_8	pull_en_8	virtual_od_en_8	invert_8

Bits

Type

Reset

Name

Description

0x0

invert_8

For DIO_PAD8

0x0

virtual_od_en_8

For DIO_PAD8

0x0

pull_en_8

For DIO_PAD8

0x0

pull_select_8

For DIO_PAD8

0x0

keeper_en_8

For DIO_PAD8

0x0

schmitt_en_8

For DIO_PAD8

0x0

od_en_8

For DIO_PAD8

15:7

Reserved

17:16

0x0

slew_rate_8

For DIO_PAD8

19:18

Reserved

23:20

0x0

drive_strength_8

For DIO_PAD8

pinmux.DIO_PAD_ATTR_9 @ 0x520

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_9						slew_rate_9
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_9	schmitt_en_9	keeper_en_9	pull_select_9	pull_en_9	virtual_od_en_9	invert_9

Bits

Type

Reset

Name

Description

0x0

invert_9

For DIO_PAD9

0x0

virtual_od_en_9

For DIO_PAD9

0x0

pull_en_9

For DIO_PAD9

0x0

pull_select_9

For DIO_PAD9

0x0

keeper_en_9

For DIO_PAD9

0x0

schmitt_en_9

For DIO_PAD9

0x0

od_en_9

For DIO_PAD9

15:7

Reserved

17:16

0x0

slew_rate_9

For DIO_PAD9

19:18

Reserved

23:20

0x0

drive_strength_9

For DIO_PAD9

pinmux.DIO_PAD_ATTR_10 @ 0x524

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_10						slew_rate_10
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_10	schmitt_en_10	keeper_en_10	pull_select_10	pull_en_10	virtual_od_en_10	invert_10

Bits

Type

Reset

Name

Description

0x0

invert_10

For DIO_PAD10

0x0

virtual_od_en_10

For DIO_PAD10

0x0

pull_en_10

For DIO_PAD10

0x0

pull_select_10

For DIO_PAD10

0x0

keeper_en_10

For DIO_PAD10

0x0

schmitt_en_10

For DIO_PAD10

0x0

od_en_10

For DIO_PAD10

15:7

Reserved

17:16

0x0

slew_rate_10

For DIO_PAD10

19:18

Reserved

23:20

0x0

drive_strength_10

For DIO_PAD10

pinmux.DIO_PAD_ATTR_11 @ 0x528

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_11						slew_rate_11
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_11	schmitt_en_11	keeper_en_11	pull_select_11	pull_en_11	virtual_od_en_11	invert_11

Bits

Type

Reset

Name

Description

0x0

invert_11

For DIO_PAD11

0x0

virtual_od_en_11

For DIO_PAD11

0x0

pull_en_11

For DIO_PAD11

0x0

pull_select_11

For DIO_PAD11

0x0

keeper_en_11

For DIO_PAD11

0x0

schmitt_en_11

For DIO_PAD11

0x0

od_en_11

For DIO_PAD11

15:7

Reserved

17:16

0x0

slew_rate_11

For DIO_PAD11

19:18

Reserved

23:20

0x0

drive_strength_11

For DIO_PAD11

pinmux.DIO_PAD_ATTR_12 @ 0x52c

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_12						slew_rate_12
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_12	schmitt_en_12	keeper_en_12	pull_select_12	pull_en_12	virtual_od_en_12	invert_12

Bits

Type

Reset

Name

Description

0x0

invert_12

For DIO_PAD12

0x0

virtual_od_en_12

For DIO_PAD12

0x0

pull_en_12

For DIO_PAD12

0x0

pull_select_12

For DIO_PAD12

0x0

keeper_en_12

For DIO_PAD12

0x0

schmitt_en_12

For DIO_PAD12

0x0

od_en_12

For DIO_PAD12

15:7

Reserved

17:16

0x0

slew_rate_12

For DIO_PAD12

19:18

Reserved

23:20

0x0

drive_strength_12

For DIO_PAD12

pinmux.DIO_PAD_ATTR_13 @ 0x530

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_13						slew_rate_13
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_13	schmitt_en_13	keeper_en_13	pull_select_13	pull_en_13	virtual_od_en_13	invert_13

Bits

Type

Reset

Name

Description

0x0

invert_13

For DIO_PAD13

0x0

virtual_od_en_13

For DIO_PAD13

0x0

pull_en_13

For DIO_PAD13

0x0

pull_select_13

For DIO_PAD13

0x0

keeper_en_13

For DIO_PAD13

0x0

schmitt_en_13

For DIO_PAD13

0x0

od_en_13

For DIO_PAD13

15:7

Reserved

17:16

0x0

slew_rate_13

For DIO_PAD13

19:18

Reserved

23:20

0x0

drive_strength_13

For DIO_PAD13

pinmux.DIO_PAD_ATTR_14 @ 0x534

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_14						slew_rate_14
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_14	schmitt_en_14	keeper_en_14	pull_select_14	pull_en_14	virtual_od_en_14	invert_14

Bits

Type

Reset

Name

Description

0x0

invert_14

For DIO_PAD14

0x0

virtual_od_en_14

For DIO_PAD14

0x0

pull_en_14

For DIO_PAD14

0x0

pull_select_14

For DIO_PAD14

0x0

keeper_en_14

For DIO_PAD14

0x0

schmitt_en_14

For DIO_PAD14

0x0

od_en_14

For DIO_PAD14

15:7

Reserved

17:16

0x0

slew_rate_14

For DIO_PAD14

19:18

Reserved

23:20

0x0

drive_strength_14

For DIO_PAD14

pinmux.DIO_PAD_ATTR_15 @ 0x538

Dedicated pad attributes. This register has WARL behavior since not each pad type may support all attributes.

Reset default = 0x0, mask 0xf3007f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								drive_strength_15						slew_rate_15
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									od_en_15	schmitt_en_15	keeper_en_15	pull_select_15	pull_en_15	virtual_od_en_15	invert_15

Bits

Type

Reset

Name

Description

0x0

invert_15

For DIO_PAD15

0x0

virtual_od_en_15

For DIO_PAD15

0x0

pull_en_15

For DIO_PAD15

0x0

pull_select_15

For DIO_PAD15

0x0

keeper_en_15

For DIO_PAD15

0x0

schmitt_en_15

For DIO_PAD15

0x0

od_en_15

For DIO_PAD15

15:7

Reserved

17:16

0x0

slew_rate_15

For DIO_PAD15

19:18

Reserved

23:20

0x0

drive_strength_15

For DIO_PAD15

pinmux.MIO_PAD_SLEEP_STATUS_0 @ 0x53c

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EN_31	EN_30	EN_29	EN_28	EN_27	EN_26	EN_25	EN_24	EN_23	EN_22	EN_21	EN_20	EN_19	EN_18	EN_17	EN_16
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EN_15	EN_14	EN_13	EN_12	EN_11	EN_10	EN_9	EN_8	EN_7	EN_6	EN_5	EN_4	EN_3	EN_2	EN_1	EN_0

Bits Type Reset Name Description

rw0c

0x0

EN_0

This register is set to 1 if the deep sleep mode of the corresponding pad has been enabled (MIO_PAD_SLEEP_EN) upon deep sleep entry. The sleep mode of the corresponding pad will remain active until SW clears this bit.

rw0c

0x0

EN_1

rw0c

0x0

EN_2

rw0c

0x0

EN_3

rw0c

0x0

EN_4

rw0c

0x0

EN_5

rw0c

0x0

EN_6

rw0c

0x0

EN_7

rw0c

0x0

EN_8

rw0c

0x0

EN_9

rw0c

0x0

EN_10

rw0c

0x0

EN_11

rw0c

0x0

EN_12

rw0c

0x0

EN_13

rw0c

0x0

EN_14

rw0c

0x0

EN_15

rw0c

0x0

EN_16

rw0c

0x0

EN_17

rw0c

0x0

EN_18

rw0c

0x0

EN_19

rw0c

0x0

EN_20

rw0c

0x0

EN_21

rw0c

0x0

EN_22

rw0c

0x0

EN_23

rw0c

0x0

EN_24

rw0c

0x0

EN_25

rw0c

0x0

EN_26

rw0c

0x0

EN_27

rw0c

0x0

EN_28

rw0c

0x0

EN_29

rw0c

0x0

EN_30

rw0c

0x0

EN_31

pinmux.MIO_PAD_SLEEP_STATUS_1 @ 0x540

Reset default = 0x0, mask 0x7fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EN_46	EN_45	EN_44	EN_43	EN_42	EN_41	EN_40	EN_39	EN_38	EN_37	EN_36	EN_35	EN_34	EN_33	EN_32

Bits

Type

Reset

Name

Description

rw0c

0x0

EN_32

For MIO_PAD1

rw0c

0x0

EN_33

For MIO_PAD1

rw0c

0x0

EN_34

For MIO_PAD1

rw0c

0x0

EN_35

For MIO_PAD1

rw0c

0x0

EN_36

For MIO_PAD1

rw0c

0x0

EN_37

For MIO_PAD1

rw0c

0x0

EN_38

For MIO_PAD1

rw0c

0x0

EN_39

For MIO_PAD1

rw0c

0x0

EN_40

For MIO_PAD1

rw0c

0x0

EN_41

For MIO_PAD1

rw0c

0x0

EN_42

For MIO_PAD1

rw0c

0x0

EN_43

For MIO_PAD1

rw0c

0x0

EN_44

For MIO_PAD1

rw0c

0x0

EN_45

For MIO_PAD1

rw0c

0x0

EN_46

For MIO_PAD1

pinmux.MIO_PAD_SLEEP_REGWEN_0 @ 0x544

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits Type Reset Name Description

rw0c

0x1

EN_0

pinmux.MIO_PAD_SLEEP_REGWEN_1 @ 0x548

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_1

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_1

For MIO_PAD1

pinmux.MIO_PAD_SLEEP_REGWEN_2 @ 0x54c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_2

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_2

For MIO_PAD2

pinmux.MIO_PAD_SLEEP_REGWEN_3 @ 0x550

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_3

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_3

For MIO_PAD3

pinmux.MIO_PAD_SLEEP_REGWEN_4 @ 0x554

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_4

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_4

For MIO_PAD4

pinmux.MIO_PAD_SLEEP_REGWEN_5 @ 0x558

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_5

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_5

For MIO_PAD5

pinmux.MIO_PAD_SLEEP_REGWEN_6 @ 0x55c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_6

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_6

For MIO_PAD6

pinmux.MIO_PAD_SLEEP_REGWEN_7 @ 0x560

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_7

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_7

For MIO_PAD7

pinmux.MIO_PAD_SLEEP_REGWEN_8 @ 0x564

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_8

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_8

For MIO_PAD8

pinmux.MIO_PAD_SLEEP_REGWEN_9 @ 0x568

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_9

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_9

For MIO_PAD9

pinmux.MIO_PAD_SLEEP_REGWEN_10 @ 0x56c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_10

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_10

For MIO_PAD10

pinmux.MIO_PAD_SLEEP_REGWEN_11 @ 0x570

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_11

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_11

For MIO_PAD11

pinmux.MIO_PAD_SLEEP_REGWEN_12 @ 0x574

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_12

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_12

For MIO_PAD12

pinmux.MIO_PAD_SLEEP_REGWEN_13 @ 0x578

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_13

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_13

For MIO_PAD13

pinmux.MIO_PAD_SLEEP_REGWEN_14 @ 0x57c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_14

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_14

For MIO_PAD14

pinmux.MIO_PAD_SLEEP_REGWEN_15 @ 0x580

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_15

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_15

For MIO_PAD15

pinmux.MIO_PAD_SLEEP_REGWEN_16 @ 0x584

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_16

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_16

For MIO_PAD16

pinmux.MIO_PAD_SLEEP_REGWEN_17 @ 0x588

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_17

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_17

For MIO_PAD17

pinmux.MIO_PAD_SLEEP_REGWEN_18 @ 0x58c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_18

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_18

For MIO_PAD18

pinmux.MIO_PAD_SLEEP_REGWEN_19 @ 0x590

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_19

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_19

For MIO_PAD19

pinmux.MIO_PAD_SLEEP_REGWEN_20 @ 0x594

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_20

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_20

For MIO_PAD20

pinmux.MIO_PAD_SLEEP_REGWEN_21 @ 0x598

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_21

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_21

For MIO_PAD21

pinmux.MIO_PAD_SLEEP_REGWEN_22 @ 0x59c

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_22

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_22

For MIO_PAD22

pinmux.MIO_PAD_SLEEP_REGWEN_23 @ 0x5a0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_23

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_23

For MIO_PAD23

pinmux.MIO_PAD_SLEEP_REGWEN_24 @ 0x5a4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_24

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_24

For MIO_PAD24

pinmux.MIO_PAD_SLEEP_REGWEN_25 @ 0x5a8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_25

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_25

For MIO_PAD25

pinmux.MIO_PAD_SLEEP_REGWEN_26 @ 0x5ac

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_26

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_26

For MIO_PAD26

pinmux.MIO_PAD_SLEEP_REGWEN_27 @ 0x5b0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_27

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_27

For MIO_PAD27

pinmux.MIO_PAD_SLEEP_REGWEN_28 @ 0x5b4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_28

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_28

For MIO_PAD28

pinmux.MIO_PAD_SLEEP_REGWEN_29 @ 0x5b8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_29

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_29

For MIO_PAD29

pinmux.MIO_PAD_SLEEP_REGWEN_30 @ 0x5bc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_30

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_30

For MIO_PAD30

pinmux.MIO_PAD_SLEEP_REGWEN_31 @ 0x5c0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_31

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_31

For MIO_PAD31

pinmux.MIO_PAD_SLEEP_REGWEN_32 @ 0x5c4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_32

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_32

For MIO_PAD32

pinmux.MIO_PAD_SLEEP_REGWEN_33 @ 0x5c8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_33

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_33

For MIO_PAD33

pinmux.MIO_PAD_SLEEP_REGWEN_34 @ 0x5cc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_34

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_34

For MIO_PAD34

pinmux.MIO_PAD_SLEEP_REGWEN_35 @ 0x5d0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_35

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_35

For MIO_PAD35

pinmux.MIO_PAD_SLEEP_REGWEN_36 @ 0x5d4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_36

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_36

For MIO_PAD36

pinmux.MIO_PAD_SLEEP_REGWEN_37 @ 0x5d8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_37

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_37

For MIO_PAD37

pinmux.MIO_PAD_SLEEP_REGWEN_38 @ 0x5dc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_38

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_38

For MIO_PAD38

pinmux.MIO_PAD_SLEEP_REGWEN_39 @ 0x5e0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_39

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_39

For MIO_PAD39

pinmux.MIO_PAD_SLEEP_REGWEN_40 @ 0x5e4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_40

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_40

For MIO_PAD40

pinmux.MIO_PAD_SLEEP_REGWEN_41 @ 0x5e8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_41

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_41

For MIO_PAD41

pinmux.MIO_PAD_SLEEP_REGWEN_42 @ 0x5ec

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_42

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_42

For MIO_PAD42

pinmux.MIO_PAD_SLEEP_REGWEN_43 @ 0x5f0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_43

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_43

For MIO_PAD43

pinmux.MIO_PAD_SLEEP_REGWEN_44 @ 0x5f4

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_44

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_44

For MIO_PAD44

pinmux.MIO_PAD_SLEEP_REGWEN_45 @ 0x5f8

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_45

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_45

For MIO_PAD45

pinmux.MIO_PAD_SLEEP_REGWEN_46 @ 0x5fc

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_46

Bits

Type

Reset

Name

Description

rw0c

0x1

EN_46

For MIO_PAD46

pinmux.MIO_PAD_SLEEP_EN_0 @ 0x600

Enables the sleep mode of the corresponding muxed pad.

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN_0

Bits Type Reset Name Description

0x0

EN_0

Deep sleep mode enable. If this bit is set to 1 the corresponding pad will enable the sleep behavior specified in MIO_PAD_SLEEP_MODE upon deep sleep entry, and the corresponding bit in MIO_PAD_SLEEP_STATUS will be set to 1. The pad remains in deep sleep mode until the corresponding bit in MIO_PAD_SLEEP_STATUS is cleared by SW. Note that if an always on peripheral is connected to a specific MIO pad, the corresponding MIO_PAD_SLEEP_EN bit should be set to 0.

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers