Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pwm has the following hardware interfaces defined

Primary Clock: clk_i
Other Clocks: clk_core_i
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Interrupts: none

Peripheral Pins for Chip IO

Pin name	Direction	Description
pwm[5:0]	output	Pulse output. Note that though this output is always enabled, there is a formal set of enable pins (pwm_en_o) which are required for top-level integration of comportable IPs.

Inter-Module Signals

Port Name	Package::Struct	Type	Act	Width	Description
tl	tlul_pkg::tl	req_rsp	rsp	1

Security Alerts

Alert Name	Description
fatal_fault	This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure ID	Description
PWM.BUS.INTEGRITY	End-to-end bus integrity scheme.

Registers

Summary

Name	Offset	Length	Description
pwm.`ALERT_TEST`	0x0	4	Alert Test Register
pwm.`REGWEN`	0x4	4	Register write enable for all control registers
pwm.`CFG`	0x8	4	Configuration register
pwm.`PWM_EN`	0xc	4	Enable PWM operation for each channel
pwm.`INVERT`	0x10	4	Invert the PWM output for each channel
pwm.`PWM_PARAM_0`	0x14	4	Basic PWM Channel Parameters
pwm.`PWM_PARAM_1`	0x18	4	Basic PWM Channel Parameters
pwm.`PWM_PARAM_2`	0x1c	4	Basic PWM Channel Parameters
pwm.`PWM_PARAM_3`	0x20	4	Basic PWM Channel Parameters
pwm.`PWM_PARAM_4`	0x24	4	Basic PWM Channel Parameters
pwm.`PWM_PARAM_5`	0x28	4	Basic PWM Channel Parameters
pwm.`DUTY_CYCLE_0`	0x2c	4	Controls the duty_cycle of each channel.
pwm.`DUTY_CYCLE_1`	0x30	4	Controls the duty_cycle of each channel.
pwm.`DUTY_CYCLE_2`	0x34	4	Controls the duty_cycle of each channel.
pwm.`DUTY_CYCLE_3`	0x38	4	Controls the duty_cycle of each channel.
pwm.`DUTY_CYCLE_4`	0x3c	4	Controls the duty_cycle of each channel.
pwm.`DUTY_CYCLE_5`	0x40	4	Controls the duty_cycle of each channel.
pwm.`BLINK_PARAM_0`	0x44	4	Hardware controlled blink/heartbeat parameters.
pwm.`BLINK_PARAM_1`	0x48	4	Hardware controlled blink/heartbeat parameters.
pwm.`BLINK_PARAM_2`	0x4c	4	Hardware controlled blink/heartbeat parameters.
pwm.`BLINK_PARAM_3`	0x50	4	Hardware controlled blink/heartbeat parameters.
pwm.`BLINK_PARAM_4`	0x54	4	Hardware controlled blink/heartbeat parameters.
pwm.`BLINK_PARAM_5`	0x58	4	Hardware controlled blink/heartbeat parameters.

ALERT_TEST

Alert Test Register

Offset: 0x0
Reset default: 0x0
Reset mask: 0x1

Fields

Bits	Type	Reset	Name	Description
31:1				Reserved
0	wo	0x0	fatal_fault	Write 1 to trigger one alert event of this kind.

REGWEN

Offset: 0x4
Reset default: 0x1
Reset mask: 0x1

Fields

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw0c	0x1	REGWEN	When true, all writable registers can be modified. When false, they become read-only. Defaults true, write zero to clear. This can be cleared after initial configuration at boot in order to lock in the listed register settings.

CFG

Configuration register

Offset: 0x8
Reset default: 0x38008000
Reset mask: 0xffffffff
Register enable: REGWEN

Fields

Bits	Type	Reset	Name
31	rw	0x0	CNTR_EN
30:27	rw	0x7	DC_RESN
26:0	rw	0x8000	CLK_DIV

CFG . CNTR_EN

Assert this bit to enable the PWM phase counter. Clearing this bit disables and resets the phase counter.

Phase Resolution (logarithmic). All duty-cycle and phase shift registers represent fractional PWM cycles, expressed in units of 2^16 PWM cycles. Each PWM cycle is divided into 2^(DC_RESN+1) time slices, and thus only the (DC_RESN+1) most significant bits of each phase or duty cycle register are relevant.

CFG . CLK_DIV

Sets the period of each PWM beat to be (CLK_DIV+1) input clock periods. Since PWM pulses are generated once every 2^(DC_RESN+1) beats, the period between output pulses is 2^(DC_RESN+1)*(CLK_DIV+1) times longer than the input clock period.

PWM_EN

Enable PWM operation for each channel

Offset: 0xc
Reset default: 0x0
Reset mask: 0x3f
Register enable: REGWEN

Fields

Bits	Type	Reset	Name	Description
31:6				Reserved
5	rw	0x0	EN_5	Write 1 to this bit to enable PWM pulses on the corresponding channel.
4	rw	0x0	EN_4	Write 1 to this bit to enable PWM pulses on the corresponding channel.
3	rw	0x0	EN_3	Write 1 to this bit to enable PWM pulses on the corresponding channel.
2	rw	0x0	EN_2	Write 1 to this bit to enable PWM pulses on the corresponding channel.
1	rw	0x0	EN_1	Write 1 to this bit to enable PWM pulses on the corresponding channel.
0	rw	0x0	EN_0	Write 1 to this bit to enable PWM pulses on the corresponding channel.

INVERT

Invert the PWM output for each channel

Offset: 0x10
Reset default: 0x0
Reset mask: 0x3f
Register enable: REGWEN

Fields

Bits	Type	Reset	Name	Description
31:6				Reserved
5	rw	0x0	INVERT_5	Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
4	rw	0x0	INVERT_4	Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
3	rw	0x0	INVERT_3	Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
2	rw	0x0	INVERT_2	Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
1	rw	0x0	INVERT_1	Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.
0	rw	0x0	INVERT_0	Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

PWM_PARAM

Basic PWM Channel Parameters

Reset default: 0x0
Reset mask: 0xc000ffff

Instances

Name	Offset
PWM_PARAM_0	0x14
PWM_PARAM_1	0x18
PWM_PARAM_2	0x1c
PWM_PARAM_3	0x20
PWM_PARAM_4	0x24
PWM_PARAM_5	0x28

Fields

Bits	Type	Reset	Name
31	rw	0x0	BLINK_EN
30	rw	0x0	HTBT_EN
29:16			Reserved
15:0	rw	0x0	PHASE_DELAY

PWM_PARAM . BLINK_EN

Enables blink (or heartbeat). If cleared, the output duty cycle will remain constant at DUTY_CYCLE.A. Enabling this bit causes the PWM duty cycle to fluctuate between DUTY_CYCLE.A and DUTY_CYCLE.B

PWM_PARAM . HTBT_EN

Modulates blink behavior to create a heartbeat effect. When HTBT_EN is set, the duty cycle increases (or decreases) linearly from DUTY_CYCLE.A to DUTY_CYCLE.B and back, in steps of (BLINK_PARAM.Y+1), with an increment (decrement) once every (BLINK_PARAM.X+1) PWM cycles. When HTBT_EN is cleared, the standard blink behavior applies, meaning that the output duty cycle alternates between DUTY_CYCLE.A for (BLINK_PARAM.X+1) pulses and DUTY_CYCLE.B for (BLINK_PARAM.Y+1) pulses.

PWM_PARAM . PHASE_DELAY

Phase delay of the PWM rising edge, in units of 2^(-16) PWM cycles

DUTY_CYCLE

Controls the duty_cycle of each channel.

Reset default: 0x7fff7fff
Reset mask: 0xffffffff

Instances

Name	Offset
DUTY_CYCLE_0	0x2c
DUTY_CYCLE_1	0x30
DUTY_CYCLE_2	0x34
DUTY_CYCLE_3	0x38
DUTY_CYCLE_4	0x3c
DUTY_CYCLE_5	0x40

Fields

Bits	Type	Reset	Name
31:16	rw	0x7fff	B
15:0	rw	0x7fff	A

DUTY_CYCLE . B

The target duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting only applies when blinking, and determines the target duty cycle.

DUTY_CYCLE . A

The initial duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting applies continuously when not blinking and determines the initial duty cycle when blinking.

BLINK_PARAM

Hardware controlled blink/heartbeat parameters.

Reset default: 0x0
Reset mask: 0xffffffff

Instances

Name	Offset
BLINK_PARAM_0	0x44
BLINK_PARAM_1	0x48
BLINK_PARAM_2	0x4c
BLINK_PARAM_3	0x50
BLINK_PARAM_4	0x54
BLINK_PARAM_5	0x58

Fields

Bits	Type	Reset	Name
31:16	rw	0x0	Y
15:0	rw	0x0	X

BLINK_PARAM . Y

This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle B for (Y+1) pulse cycles before returning to duty cycle A. If heartbeat is enabled the duty cycle will increase (or decrease) by (Y+1) units every time it is incremented (or decremented)

BLINK_PARAM . X

This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle A for (X+1) pulses before switching to duty cycle B. If heartbeat is enabled the duty-cycle will start at the duty cycle A, but will be incremented (or decremented) every (X+1) cycles. In heartbeat mode is enabled, the size of each step is controlled by BLINK_PARAM.Y.