Write 1 to trigger one alert event of this kind.

When true, all writable registers can be modified. When false, they become read-only. Defaults true, write zero to clear. This can be cleared after initial configuration at boot in order to lock in the listed register settings.

Sets the period of each PWM beat to be (CLK_DIV+1) input clock periods. Since PWM pulses are generated once every 2^(DC_RESN+1) beats, the period between output pulses is 2^(DC_RESN+1)*(CLK_DIV+1) times longer than the input clock period.

Phase Resolution (logarithmic). All duty-cycle and phase shift registers represent fractional PWM cycles, expressed in units of 2^16 PWM cycles. Each PWM cycle is divided into 2^(DC_RESN+1) time slices, and thus only the (DC_RESN+1) most significant bits of each phase or duty cycle register are relevant.

Assert this bit to enable the PWM phase counter. Clearing this bit disables and resets the phase counter.

Write 1 to this bit to enable PWM pulses on the corresponding channel.

Write 1 to this bit to enable PWM pulses on the corresponding channel.

Write 1 to this bit to enable PWM pulses on the corresponding channel.

Write 1 to this bit to enable PWM pulses on the corresponding channel.

Write 1 to this bit to enable PWM pulses on the corresponding channel.

Write 1 to this bit to enable PWM pulses on the corresponding channel.

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

Phase delay of the PWM rising edge, in units of 2^(-16) PWM cycles

Modulates blink behavior to create a heartbeat effect. When HTBT_EN is set, the duty cycle increases (or decreases) linearly from DUTY_CYCLE.A to DUTY_CYCLE.B and back, in steps of (BLINK_PARAM.Y+1), with an increment (decrement) once every (BLINK_PARAM.X+1) PWM cycles. When HTBT_EN is cleared, the standard blink behavior applies, meaning that the output duty cycle alternates between DUTY_CYCLE.A for (BLINK_PARAM.X+1) pulses and DUTY_CYCLE.B for (BLINK_PARAM.Y+1) pulses.

Enables blink (or heartbeat). If cleared, the output duty cycle will remain constant at DUTY_CYCLE.A. Enabling this bit causes the PWM duty cycle to fluctuate between DUTY_CYCLE.A and DUTY_CYCLE.B

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The initial duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting applies continuously when not blinking and determines the initial duty cycle when blinking.

The target duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting only applies when blinking, and determines the target duty cycle.

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This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle A for (X+1) pulses before switching to duty cycle B. If heartbeat is enabled the duty-cycle will start at the duty cycle A, but will be incremented (or decremented) every (X+1) cycles. In heartbeat mode is enabled, the size of each step is controlled by BLINK_PARAM.Y.

This blink-rate timing parameter has two different interpretations depending on whether or not the heartbeat feature is enabled. If heartbeat is disabled, a blinking PWM will pulse at duty cycle B for (Y+1) pulse cycles before returning to duty cycle A. If heartbeat is enabled the duty cycle will increase (or decrease) by (Y+1) units every time it is incremented (or decremented)

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