Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module pwm has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_core_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin namedirectionDescription
pwm[5:0]output

Pulse output. Note that though this output is always enabled, there is a formal set of enable pins (pwm_en_o) which are required for top-level integration of comportable IPs.

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
tl tlul_pkg::tl req_rsp rsp 1

Interrupts: none

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
PWM.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
pwm.ALERT_TEST 0x0 4

Alert Test Register

pwm.REGWEN 0x4 4

Register write enable for all control registers

pwm.CFG 0x8 4

Configuration register

pwm.PWM_EN 0xc 4

Enable PWM operation for each channel

pwm.INVERT 0x10 4

Invert the PWM output for each channel

pwm.PWM_PARAM_0 0x14 4

Basic PWM Channel Parameters

pwm.PWM_PARAM_1 0x18 4

Basic PWM Channel Parameters

pwm.PWM_PARAM_2 0x1c 4

Basic PWM Channel Parameters

pwm.PWM_PARAM_3 0x20 4

Basic PWM Channel Parameters

pwm.PWM_PARAM_4 0x24 4

Basic PWM Channel Parameters

pwm.PWM_PARAM_5 0x28 4

Basic PWM Channel Parameters

pwm.DUTY_CYCLE_0 0x2c 4

Controls the duty_cycle of each channel.

pwm.DUTY_CYCLE_1 0x30 4

Controls the duty_cycle of each channel.

pwm.DUTY_CYCLE_2 0x34 4

Controls the duty_cycle of each channel.

pwm.DUTY_CYCLE_3 0x38 4

Controls the duty_cycle of each channel.

pwm.DUTY_CYCLE_4 0x3c 4

Controls the duty_cycle of each channel.

pwm.DUTY_CYCLE_5 0x40 4

Controls the duty_cycle of each channel.

pwm.BLINK_PARAM_0 0x44 4

Hardware controlled blink/heartbeat parameters.

pwm.BLINK_PARAM_1 0x48 4

Hardware controlled blink/heartbeat parameters.

pwm.BLINK_PARAM_2 0x4c 4

Hardware controlled blink/heartbeat parameters.

pwm.BLINK_PARAM_3 0x50 4

Hardware controlled blink/heartbeat parameters.

pwm.BLINK_PARAM_4 0x54 4

Hardware controlled blink/heartbeat parameters.

pwm.BLINK_PARAM_5 0x58 4

Hardware controlled blink/heartbeat parameters.

pwm.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


pwm.REGWEN @ 0x4

Register write enable for all control registers

Reset default = 0x1, mask 0x1
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  REGWEN
BitsTypeResetNameDescription
0rw0c0x1REGWEN

When true, all writable registers can be modified. When false, they become read-only. Defaults true, write zero to clear. This can be cleared after initial configuration at boot in order to lock in the listed register settings.


pwm.CFG @ 0x8

Configuration register

Reset default = 0x38008000, mask 0xffffffff
Register enable = REGWEN
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CNTR_EN DC_RESN CLK_DIV...
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...CLK_DIV
BitsTypeResetNameDescription
26:0rw0x8000CLK_DIV

Sets the period of each PWM beat to be (CLK_DIV+1) input clock periods. Since PWM pulses are generated once every 2^(DC_RESN+1) beats, the period between output pulses is 2^(DC_RESN+1)*(CLK_DIV+1) times longer than the input clock period.

30:27rw0x7DC_RESN

Phase Resolution (logarithmic). All duty-cycle and phase shift registers represent fractional PWM cycles, expressed in units of 2^16 PWM cycles. Each PWM cycle is divided into 2^(DC_RESN+1) time slices, and thus only the (DC_RESN+1) most significant bits of each phase or duty cycle register are relevant.

31rw0x0CNTR_EN

Assert this bit to enable the PWM phase counter. Clearing this bit disables and resets the phase counter.


pwm.PWM_EN @ 0xc

Enable PWM operation for each channel

Reset default = 0x0, mask 0x3f
Register enable = REGWEN
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  EN_5 EN_4 EN_3 EN_2 EN_1 EN_0
BitsTypeResetNameDescription
0rw0x0EN_0

Write 1 to this bit to enable PWM pulses on the corresponding channel.

1rw0x0EN_1

Write 1 to this bit to enable PWM pulses on the corresponding channel.

2rw0x0EN_2

Write 1 to this bit to enable PWM pulses on the corresponding channel.

3rw0x0EN_3

Write 1 to this bit to enable PWM pulses on the corresponding channel.

4rw0x0EN_4

Write 1 to this bit to enable PWM pulses on the corresponding channel.

5rw0x0EN_5

Write 1 to this bit to enable PWM pulses on the corresponding channel.


pwm.INVERT @ 0x10

Invert the PWM output for each channel

Reset default = 0x0, mask 0x3f
Register enable = REGWEN
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  INVERT_5 INVERT_4 INVERT_3 INVERT_2 INVERT_1 INVERT_0
BitsTypeResetNameDescription
0rw0x0INVERT_0

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

1rw0x0INVERT_1

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

2rw0x0INVERT_2

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

3rw0x0INVERT_3

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

4rw0x0INVERT_4

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.

5rw0x0INVERT_5

Write 1 to this bit to invert the output for each channel, so that the corresponding output is active-low.


pwm.PWM_PARAM_0 @ 0x14

Basic PWM Channel Parameters

Reset default = 0x0, mask 0xc000ffff
Register enable = REGWEN
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BLINK_EN_0 HTBT_EN_0  
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PHASE_DELAY_0
BitsTypeResetNameDescription
15:0rw0x0PHASE_DELAY_0

Phase delay of the PWM rising edge, in units of 2^(-16) PWM cycles

29:16Reserved
30rw0x0HTBT_EN_0

Modulates blink behavior to create a heartbeat effect. When HTBT_EN is set, the duty cycle increases (or decreases) linearly from DUTY_CYCLE.A to DUTY_CYCLE.B and back, in steps of (BLINK_PARAM.Y+1), with an increment (decrement) once every (BLINK_PARAM.X+1) PWM cycles. When HTBT_EN is cleared, the standard blink behavior applies, meaning that the output duty cycle alternates between DUTY_CYCLE.A for (BLINK_PARAM.X+1) pulses and DUTY_CYCLE.B for (BLINK_PARAM.Y+1) pulses.

31rw0x0BLINK_EN_0

Enables blink (or heartbeat). If cleared, the output duty cycle will remain constant at DUTY_CYCLE.A. Enabling this bit causes the PWM duty cycle to fluctuate between DUTY_CYCLE.A and DUTY_CYCLE.B


pwm.PWM_PARAM_1 @ 0x18

Basic PWM Channel Parameters

Reset default = 0x0, mask 0xc000ffff
Register enable = REGWEN
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BLINK_EN_1 HTBT_EN_1  
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PHASE_DELAY_1
BitsTypeResetNameDescription
15:0rw0x0PHASE_DELAY_1

For pwm_params1

29:16Reserved
30rw0x0HTBT_EN_1

For pwm_params1

31rw0x0BLINK_EN_1

For pwm_params1


pwm.PWM_PARAM_2 @ 0x1c

Basic PWM Channel Parameters

Reset default = 0x0, mask 0xc000ffff
Register enable = REGWEN
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BLINK_EN_2 HTBT_EN_2  
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PHASE_DELAY_2
BitsTypeResetNameDescription
15:0rw0x0PHASE_DELAY_2

For pwm_params2

29:16Reserved
30rw0x0HTBT_EN_2

For pwm_params2

31rw0x0BLINK_EN_2

For pwm_params2


pwm.PWM_PARAM_3 @ 0x20

Basic PWM Channel Parameters

Reset default = 0x0, mask 0xc000ffff
Register enable = REGWEN
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BLINK_EN_3 HTBT_EN_3  
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PHASE_DELAY_3
BitsTypeResetNameDescription
15:0rw0x0PHASE_DELAY_3

For pwm_params3

29:16Reserved
30rw0x0HTBT_EN_3

For pwm_params3

31rw0x0BLINK_EN_3

For pwm_params3


pwm.PWM_PARAM_4 @ 0x24

Basic PWM Channel Parameters

Reset default = 0x0, mask 0xc000ffff
Register enable = REGWEN
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BLINK_EN_4 HTBT_EN_4  
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PHASE_DELAY_4
BitsTypeResetNameDescription
15:0rw0x0PHASE_DELAY_4

For pwm_params4

29:16Reserved
30rw0x0HTBT_EN_4

For pwm_params4

31rw0x0BLINK_EN_4

For pwm_params4


pwm.PWM_PARAM_5 @ 0x28

Basic PWM Channel Parameters

Reset default = 0x0, mask 0xc000ffff
Register enable = REGWEN
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BLINK_EN_5 HTBT_EN_5  
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PHASE_DELAY_5
BitsTypeResetNameDescription
15:0rw0x0PHASE_DELAY_5

For pwm_params5

29:16Reserved
30rw0x0HTBT_EN_5

For pwm_params5

31rw0x0BLINK_EN_5

For pwm_params5


pwm.DUTY_CYCLE_0 @ 0x2c

Controls the duty_cycle of each channel.

Reset default = 0x7fff7fff, mask 0xffffffff
Register enable = REGWEN
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B_0
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A_0
BitsTypeResetNameDescription
15:0rw0x7fffA_0

The initial duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting applies continuously when not blinking and determines the initial duty cycle when blinking.

31:16rw0x7fffB_0

The target duty cycle for PWM output, in units of 2^(-16)ths of a pulse cycle. The actual precision is however limited to the (DC_RESN+1) most significant bits. This setting only applies when blinking, and determines the target duty cycle.


pwm.DUTY_CYCLE_1 @ 0x30

Controls the duty_cycle of each channel.

Reset default = 0x7fff7fff, mask 0xffffffff
Register enable = REGWEN
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B_1
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A_1
BitsTypeResetNameDescription
15:0rw0x7fffA_1

For duty_cycle1

31:16rw0x7fffB_1

For duty_cycle1


pwm.DUTY_CYCLE_2 @ 0x34

Controls the duty_cycle of each channel.

Reset default = 0x7fff7fff, mask 0xffffffff
Register enable = REGWEN
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B_2
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A_2
BitsTypeResetNameDescription
15:0rw0x7fffA_2

For duty_cycle2

31:16rw0x7fffB_2

For duty_cycle2


pwm.DUTY_CYCLE_3 @ 0x38

Controls the duty_cycle of each channel.

Reset default = 0x7fff7fff, mask 0xffffffff
Register enable = REGWEN
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B_3
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A_3
BitsTypeResetNameDescription
15:0rw0x7fffA_3

For duty_cycle3

31:16rw0x7fffB_3

For duty_cycle3


pwm.DUTY_CYCLE_4 @ 0x3c

Controls the duty_cycle of each channel.

Reset default = 0x7fff7fff, mask 0xffffffff
Register enable = REGWEN
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B_4
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A_4
BitsTypeResetNameDescription
15:0rw0x7fffA_4

For duty_cycle4

31:16rw0x7fffB_4

For duty_cycle4


pwm.DUTY_CYCLE_5 @ 0x40

Controls the duty_cycle of each channel.

Reset default = 0x7fff7fff, mask 0xffffffff
Register enable = REGWEN
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B_5
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A_5
BitsTypeResetNameDescription
15:0rw0x7fffA_5

For duty_cycle5

31:16rw0x7fffB_5

For duty_cycle5