Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module flash_ctrl has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_otp_i

Bus Device Interfaces (TL-UL): core_tl, prim_tl, mem_tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO:

Pin name	direction	Description
tck	input	jtag clock
tms	input	jtag tms
tdi	input	jtag input
tdo	output	jtag output

Inter-Module Signals: Reference

Inter-Module Signals
Port Name	Package::Struct	Type	Act	Width
otp	otp_ctrl_pkg::flash_otp_key	req_rsp	req	1
lc_nvm_debug_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
flash_bist_enable	prim_mubi_pkg::mubi4	uni	rcv	1
flash_power_down_h	logic	uni	rcv	1
flash_power_ready_h	logic	uni	rcv	1
flash_test_mode_a		io	none	2
flash_test_voltage_h		io	none	1
lc_creator_seed_sw_rw_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_owner_seed_sw_rw_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_iso_part_sw_rd_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_iso_part_sw_wr_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_seed_hw_rd_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_escalate_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
rma_req	lc_ctrl_pkg::lc_tx	uni	rcv	1
rma_ack	lc_ctrl_pkg::lc_tx	uni	req	1
rma_seed	lc_ctrl_pkg::lc_flash_rma_seed	uni	rcv	1
pwrmgr	pwrmgr_pkg::pwr_flash	uni	req	1
keymgr	flash_ctrl_pkg::keymgr_flash	uni	req	1
obs_ctrl	ast_pkg::ast_obs_ctrl	uni	rcv	1
fla_obs	logic	uni	req	8
core_tl	tlul_pkg::tl	req_rsp	rsp	1
prim_tl	tlul_pkg::tl	req_rsp	rsp	1
mem_tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts:

Interrupt Name	Type	Description
prog_empty	Event	Program FIFO empty
prog_lvl	Event	Program FIFO drained to level
rd_full	Event	Read FIFO full
rd_lvl	Event	Read FIFO filled to level
op_done	Event	Operation complete
corr_err	Event	Correctable error encountered

Security Alerts:

Alert Name	Description
recov_err	flash recoverable errors
fatal_std_err	flash standard fatal errors
fatal_err	flash fatal errors
fatal_prim_flash_alert	Fatal alert triggered inside the flash primitive, including fatal TL-UL bus integrity faults of the test interface.
recov_prim_flash_alert	Recoverable alert triggered inside the flash primitive.

Security Countermeasures:

Countermeasure ID	Description
FLASH_CTRL.REG.BUS.INTEGRITY	End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules.
FLASH_CTRL.HOST.BUS.INTEGRITY	End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules.
FLASH_CTRL.MEM.BUS.INTEGRITY	End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules.
FLASH_CTRL.SCRAMBLE.KEY.SIDELOAD	The scrambling key is sideloaded from OTP and thus unreadable by SW.
FLASH_CTRL.LC_CTRL.INTERSIG.MUBI	Life cycle control signals are used control information partition access and flash debug access. See secret information partition, isolated information partitions and jtag connection in documentation for more details.
FLASH_CTRL.CTRL.CONFIG.REGWEN	Configurations cannot be changed when an operation is ongoing.
FLASH_CTRL.DATA_REGIONS.CONFIG.REGWEN	Each data region has a configurable regwen.
FLASH_CTRL.DATA_REGIONS.CONFIG.SHADOW	Data region configuration is shadowed.
FLASH_CTRL.INFO_REGIONS.CONFIG.REGWEN	Each info page of each type in each bank has separate regwen.
FLASH_CTRL.INFO_REGIONS.CONFIG.SHADOW	Each info page is shadowed.
FLASH_CTRL.BANK.CONFIG.REGWEN	Each bank has separate regwen for bank erase.
FLASH_CTRL.BANK.CONFIG.SHADOW	Each bank has separate regwen for bank erase.
FLASH_CTRL.MEM.CTRL.GLOBAL_ESC	Global escalation causes memory to no longer be accessible.
FLASH_CTRL.MEM.CTRL.LOCAL_ESC	A subset of fatal errors cause memory to no longer be accessible. This subset is defined in `STD_FAULT_STATUS`.
FLASH_CTRL.MEM_DISABLE.CONFIG.MUBI	Software control for flash disable is multibit. The register is `DIS`.
FLASH_CTRL.EXEC.CONFIG.REDUN	Software control for flash enable is 32-bit constant. The register is `EXEC`.
FLASH_CTRL.MEM.SCRAMBLE	The flash supports XEX scrambling. The cipher used is PRINCE. The scrambling scheme is enabled by software, please see flash scrambling in documentation for more details.
FLASH_CTRL.MEM.INTEGRITY	The flash supports two layers of ECC integrity: one layer is for integrity, and the other layer is for reliability. These ECCs are enabled and disabled together by software. Please see Flash ECC in the documentation for more details.
FLASH_CTRL.RMA_ENTRY.MEM.SEC_WIPE	RMA entry entry wipes flash memory with random data.
FLASH_CTRL.CTRL.FSM.SPARSE	RMA handling FSMs in flash_ctrl_lcmgr are sparsely encoded. FSM in flash_ctrl_arb is sparsely encoded.
FLASH_CTRL.PHY.FSM.SPARSE	PHY FSMs are sparsely encoded.
FLASH_CTRL.PHY_PROG.FSM.SPARSE	PHY program FSMs are sparsely encoded.
FLASH_CTRL.CTR.REDUN	flash_ctrl_lcmgr handling counters are redundantly encoded. This includes seed count and address count used during seed reading phase, as well as word count, page count and wipe index in RMA entry phase.
FLASH_CTRL.PHY_ARBITER.CTRL.REDUN	The phy arbiter for controller and host is redundant. The arbiter has two instance underneath that are constantly compared to each other.
FLASH_CTRL.PHY_HOST_GRANT.CTRL.CONSISTENCY	The host grant is consistency checked. If the host is ever granted with info partition access, it is an error. If the host is ever granted at the same time as a program/erase operation, it is an error.
FLASH_CTRL.PHY_ACK.CTRL.CONSISTENCY	If the host or controller ever receive an unexpeced transaction acknowledge, it is an error.
FLASH_CTRL.FIFO.CTR.REDUN	The FIFO pointers of several FIFOs are implemented with duplicate counters.
FLASH_CTRL.MEM_TL_LC_GATE.FSM.SPARSE	The control FSM inside the TL-UL gating primitive is sparsely encoded.
FLASH_CTRL.PROG_TL_LC_GATE.FSM.SPARSE	The control FSM inside the TL-UL gating primitive is sparsely encoded.

Registers

Registers visible under device interface `core`

Summary
Name	Offset	Length	Description
flash_ctrl.INTR_STATE	0x0	4	Interrupt State Register
flash_ctrl.INTR_ENABLE	0x4	4	Interrupt Enable Register
flash_ctrl.INTR_TEST	0x8	4	Interrupt Test Register
flash_ctrl.ALERT_TEST	0xc	4	Alert Test Register
flash_ctrl.DIS	0x10	4	Disable flash functionality
flash_ctrl.EXEC	0x14	4	Controls whether flash can be used for code execution fetches
flash_ctrl.INIT	0x18	4	Controller init register
flash_ctrl.CTRL_REGWEN	0x1c	4	Controls the configurability of the `CONTROL` register.
flash_ctrl.CONTROL	0x20	4	Control register
flash_ctrl.ADDR	0x24	4	Address for flash operation
flash_ctrl.PROG_TYPE_EN	0x28	4	Enable different program types
flash_ctrl.ERASE_SUSPEND	0x2c	4	Suspend erase
flash_ctrl.REGION_CFG_REGWEN_0	0x30	4	Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_1	0x34	4	Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_2	0x38	4	Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_3	0x3c	4	Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_4	0x40	4	Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_5	0x44	4	Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_6	0x48	4	Memory region registers configuration enable.
flash_ctrl.REGION_CFG_REGWEN_7	0x4c	4	Memory region registers configuration enable.
flash_ctrl.MP_REGION_CFG_0	0x50	4	Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_1	0x54	4	Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_2	0x58	4	Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_3	0x5c	4	Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_4	0x60	4	Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_5	0x64	4	Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_6	0x68	4	Memory property configuration for data partition
flash_ctrl.MP_REGION_CFG_7	0x6c	4	Memory property configuration for data partition
flash_ctrl.MP_REGION_0	0x70	4	Memory base and size configuration for data partition
flash_ctrl.MP_REGION_1	0x74	4	Memory base and size configuration for data partition
flash_ctrl.MP_REGION_2	0x78	4	Memory base and size configuration for data partition
flash_ctrl.MP_REGION_3	0x7c	4	Memory base and size configuration for data partition
flash_ctrl.MP_REGION_4	0x80	4	Memory base and size configuration for data partition
flash_ctrl.MP_REGION_5	0x84	4	Memory base and size configuration for data partition
flash_ctrl.MP_REGION_6	0x88	4	Memory base and size configuration for data partition
flash_ctrl.MP_REGION_7	0x8c	4	Memory base and size configuration for data partition
flash_ctrl.DEFAULT_REGION	0x90	4	Default region properties
flash_ctrl.BANK0_INFO0_REGWEN_0	0x94	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_1	0x98	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_2	0x9c	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_3	0xa0	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_4	0xa4	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_5	0xa8	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_6	0xac	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_7	0xb0	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_8	0xb4	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_REGWEN_9	0xb8	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO0_PAGE_CFG_0	0xbc	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_1	0xc0	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_2	0xc4	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_3	0xc8	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_4	0xcc	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_5	0xd0	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_6	0xd4	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_7	0xd8	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_8	0xdc	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO0_PAGE_CFG_9	0xe0	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO1_REGWEN	0xe4	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO1_PAGE_CFG	0xe8	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO2_REGWEN_0	0xec	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO2_REGWEN_1	0xf0	4	Memory region registers configuration enable.
flash_ctrl.BANK0_INFO2_PAGE_CFG_0	0xf4	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK0_INFO2_PAGE_CFG_1	0xf8	4	Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_REGWEN_0	0xfc	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_1	0x100	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_2	0x104	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_3	0x108	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_4	0x10c	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_5	0x110	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_6	0x114	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_7	0x118	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_8	0x11c	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_REGWEN_9	0x120	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO0_PAGE_CFG_0	0x124	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_1	0x128	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_2	0x12c	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_3	0x130	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_4	0x134	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_5	0x138	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_6	0x13c	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_7	0x140	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_8	0x144	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO0_PAGE_CFG_9	0x148	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO1_REGWEN	0x14c	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO1_PAGE_CFG	0x150	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO2_REGWEN_0	0x154	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO2_REGWEN_1	0x158	4	Memory region registers configuration enable.
flash_ctrl.BANK1_INFO2_PAGE_CFG_0	0x15c	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.BANK1_INFO2_PAGE_CFG_1	0x160	4	Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.
flash_ctrl.HW_INFO_CFG_OVERRIDE	0x164	4	HW interface info configuration rule overrides
flash_ctrl.BANK_CFG_REGWEN	0x168	4	Bank configuration registers configuration enable.
flash_ctrl.MP_BANK_CFG_SHADOWED	0x16c	4	Memory properties bank configuration
flash_ctrl.OP_STATUS	0x170	4	Flash Operation Status
flash_ctrl.STATUS	0x174	4	Flash Controller Status
flash_ctrl.DEBUG_STATE	0x178	4	Current flash fsm state
flash_ctrl.ERR_CODE	0x17c	4	Flash error code register. This register tabulates detailed error status of the flash. This is separate from `OP_STATUS`, which is used to indicate the current state of the software initiated flash operation.
flash_ctrl.STD_FAULT_STATUS	0x180	4	This register tabulates standard fault status of the flash.
flash_ctrl.FAULT_STATUS	0x184	4	This register tabulates customized fault status of the flash.
flash_ctrl.ERR_ADDR	0x188	4	Synchronous error address
flash_ctrl.ECC_SINGLE_ERR_CNT	0x18c	4	Total number of single bit ECC error count
flash_ctrl.ECC_SINGLE_ERR_ADDR_0	0x190	4	Latest address of ECC single err
flash_ctrl.ECC_SINGLE_ERR_ADDR_1	0x194	4	Latest address of ECC single err
flash_ctrl.PHY_ALERT_CFG	0x198	4	Phy alert configuration
flash_ctrl.PHY_STATUS	0x19c	4	Flash Phy Status
flash_ctrl.Scratch	0x1a0	4	Flash Controller Scratch
flash_ctrl.FIFO_LVL	0x1a4	4	Programmable depth where FIFOs should generate interrupts
flash_ctrl.FIFO_RST	0x1a8	4	Reset for flash controller FIFOs
flash_ctrl.CURR_FIFO_LVL	0x1ac	4	Current program and read fifo depth
flash_ctrl.prog_fifo	0x1b0	4	Flash program FIFO.
flash_ctrl.rd_fifo	0x1b4	4	Flash read FIFO.

flash_ctrl.INTR_STATE @ 0x0

Interrupt State Register

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										corr_err	op_done	rd_lvl	rd_full	prog_lvl	prog_empty

Bits

Type

Reset

Name

Description

rw1c

0x0

prog_empty

Program FIFO empty

rw1c

0x0

prog_lvl

Program FIFO drained to level

rw1c

0x0

rd_full

Read FIFO full

rw1c

0x0

rd_lvl

Read FIFO filled to level

rw1c

0x0

op_done

Operation complete

rw1c

0x0

corr_err

Correctable error encountered

flash_ctrl.INTR_ENABLE @ 0x4

Interrupt Enable Register

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										corr_err	op_done	rd_lvl	rd_full	prog_lvl	prog_empty

Bits Type Reset Name Description

0x0

prog_empty

Enable interrupt when INTR_STATE.prog_empty is set.

0x0

prog_lvl

Enable interrupt when INTR_STATE.prog_lvl is set.

0x0

rd_full

Enable interrupt when INTR_STATE.rd_full is set.

0x0

rd_lvl

Enable interrupt when INTR_STATE.rd_lvl is set.

0x0

op_done

Enable interrupt when INTR_STATE.op_done is set.

0x0

corr_err

Enable interrupt when INTR_STATE.corr_err is set.

flash_ctrl.INTR_TEST @ 0x8

Interrupt Test Register

Reset default = 0x0, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										corr_err	op_done	rd_lvl	rd_full	prog_lvl	prog_empty

Bits Type Reset Name Description

0x0

prog_empty

Write 1 to force INTR_STATE.prog_empty to 1.

0x0

prog_lvl

Write 1 to force INTR_STATE.prog_lvl to 1.

0x0

rd_full

Write 1 to force INTR_STATE.rd_full to 1.

0x0

rd_lvl

Write 1 to force INTR_STATE.rd_lvl to 1.

0x0

op_done

Write 1 to force INTR_STATE.op_done to 1.

0x0

corr_err

Write 1 to force INTR_STATE.corr_err to 1.

flash_ctrl.ALERT_TEST @ 0xc

Alert Test Register

Reset default = 0x0, mask 0x1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											recov_prim_flash_alert	fatal_prim_flash_alert	fatal_err	fatal_std_err	recov_err

Bits

Type

Reset

Name

Description

0x0

recov_err

Write 1 to trigger one alert event of this kind.

0x0

fatal_std_err

Write 1 to trigger one alert event of this kind.

0x0

fatal_err

Write 1 to trigger one alert event of this kind.

0x0

fatal_prim_flash_alert

Write 1 to trigger one alert event of this kind.

0x0

recov_prim_flash_alert

Write 1 to trigger one alert event of this kind.

flash_ctrl.DIS @ 0x10

Disable flash functionality

Reset default = 0x9, mask 0xf

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VAL

Bits

Type

Reset

Name

Description

3:0

rw0c

0x9

VAL

Disables flash functionality completely. This is a shortcut mechanism used by the software to completely kill flash in case of emergency.

Since this register is rw0c instead of rw, to disable, write any value in the form of 0xxx or xxx0, where x could be either 0 or 1.

flash_ctrl.EXEC @ 0x14

Controls whether flash can be used for code execution fetches

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EN...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...EN

Bits

Type

Reset

Name

Description

31:0

0x0

A value of 0xa26a38f7 allows flash to be used for code execution. Any other value prevents code execution.

flash_ctrl.INIT @ 0x18

Controller init register

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															VAL

Bits

Type

Reset

Name

Description

rw1s

0x0

VAL

Initializes the flash controller.

During the initialization process, the flash controller requests the address and data scramble keys and reads out the root seeds stored in flash before allowing other usage of the flash controller.

When the initialization sequence is complete, the flash read buffers are enabled and turned on.

flash_ctrl.CTRL_REGWEN @ 0x1c

Controls the configurability of the CONTROL register.

Reset default = 0x1, mask 0x1

This register ensures the contents of CONTROL cannot be changed by software once a flash operation has begun.

It unlocks whenever the existing flash operation completes, regardless of success or error.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN

Bits Type Reset Name Description

0x1

Configuration enable.

This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated. When the controller completes the flash operation, this bit is set back to 1 to allow software configuration of CONTROL

flash_ctrl.CONTROL @ 0x20

Control register

Reset default = 0x0, mask 0xfff07f1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				NUM
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					INFO_SEL		PARTITION_SEL	ERASE_SEL	PROG_SEL	OP					START

Bits Type Reset Name Description

0x0

START

Start flash transaction. This bit shall only be set at the same time or after the other fields of the CONTROL register and ADDR have been programmed.

3:1 Reserved

5:4

0x0

Flash operation selection

0x0

Read

Flash Read.

Read desired number of flash words

0x1

Prog

Flash Program.

Program desired number of flash words

0x2

Erase

Flash Erase Operation.

See ERASE_SEL for details on erase operation

Other values are reserved.

0x0

PROG_SEL

Flash program operation type selection

0x0	Normal program	Normal program operation to the flash
0x1	Program repair	Repair program operation to the flash. Whether this is actually supported depends on the underlying flash memory.

0x0

ERASE_SEL

Flash erase operation type selection

0x0	Page Erase	Erase 1 page of flash
0x1	Bank Erase	Erase 1 bank of flash

0x0

PARTITION_SEL

When doing a read, program or page erase operation, selects either info or data partition for operation. When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller. When 1, select info partition - this is the portion of flash that is only accessible by the controller.

When doing a bank erase operation, selects info partition also for erase. When 0, bank erase only erases data partition. When 1, bank erase erases data partition and info partition.

10:9

0x0

INFO_SEL

Informational partions can have multiple types.

This field selects the info type to be accessed.

15:11 Reserved

27:16

0x0

NUM

One fewer than the number of bus words the flash operation should read or program. For example, to read 10 words, software should program this field with the value 9.

flash_ctrl.ADDR @ 0x24

Address for flash operation

Reset default = 0x0, mask 0xfffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												START...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...START

Bits

Type

Reset

Name

Description

19:0

0x0

START

Start address of a flash transaction. This is a byte address relative to the flash only. Ie, an address of 0 will access address 0 of the requested partition.

For read operations, the flash controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10.

Program operations behave similarly, the controller does not have read modified write support.

For page erases, the controller will truncate to the closest lower page aligned address. Similarly for bank erases, the controller will truncate to the closest lower bank aligned address.

flash_ctrl.PROG_TYPE_EN @ 0x28

Enable different program types

Reset default = 0x3, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														REPAIR	NORMAL

Bits

Type

Reset

Name

Description

rw0c

0x1

NORMAL

Normal prog type available

rw0c

0x1

REPAIR

Repair prog type available

flash_ctrl.ERASE_SUSPEND @ 0x2c

Suspend erase

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REQ

Bits

Type

Reset

Name

Description

0x0

REQ

When 1, request erase suspend. If no erase ongoing, the request is immediately cleared by hardware If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled.

flash_ctrl.REGION_CFG_REGWEN_0 @ 0x30

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_0

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_0

Region register write enable. Once set to 0, it can longer be configured to 1

0x0	Region locked	Region can no longer be configured until next reset
0x1	Region enabled	Region can be configured

flash_ctrl.REGION_CFG_REGWEN_1 @ 0x34

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_1

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_1

For FLASH_CTRL1

flash_ctrl.REGION_CFG_REGWEN_2 @ 0x38

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_2

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_2

For FLASH_CTRL2

flash_ctrl.REGION_CFG_REGWEN_3 @ 0x3c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_3

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_3

For FLASH_CTRL3

flash_ctrl.REGION_CFG_REGWEN_4 @ 0x40

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_4

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_4

For FLASH_CTRL4

flash_ctrl.REGION_CFG_REGWEN_5 @ 0x44

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_5

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_5

For FLASH_CTRL5

flash_ctrl.REGION_CFG_REGWEN_6 @ 0x48

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_6

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_6

For FLASH_CTRL6

flash_ctrl.REGION_CFG_REGWEN_7 @ 0x4c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_7

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_7

For FLASH_CTRL7

flash_ctrl.MP_REGION_CFG_0 @ 0x50

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_0				ECC_EN_0				SCRAMBLE_EN_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_0				PROG_EN_0				RD_EN_0				EN_0

Bits

Type

Reset

Name

Description

3:0

0x9

EN_0

Region enabled, following fields apply. If region is disabled, it is not matched against any incoming transaction.

7:4

0x9

RD_EN_0

Region can be read

11:8

0x9

PROG_EN_0

Region can be programmed

15:12

0x9

ERASE_EN_0

Region can be erased

19:16

0x9

SCRAMBLE_EN_0

Region is scramble enabled.

23:20

0x9

ECC_EN_0

Region is integrity checked and reliability ECC enabled.

27:24

0x9

HE_EN_0

Region is high endurance enabled.

flash_ctrl.MP_REGION_CFG_1 @ 0x54

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_1				ECC_EN_1				SCRAMBLE_EN_1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_1				PROG_EN_1				RD_EN_1				EN_1

Bits

Type

Reset

Name

Description

3:0

0x9

EN_1

For FLASH_CTRL1

7:4

0x9

RD_EN_1

For FLASH_CTRL1

11:8

0x9

PROG_EN_1

For FLASH_CTRL1

15:12

0x9

ERASE_EN_1

For FLASH_CTRL1

19:16

0x9

SCRAMBLE_EN_1

For FLASH_CTRL1

23:20

0x9

ECC_EN_1

For FLASH_CTRL1

27:24

0x9

HE_EN_1

For FLASH_CTRL1

flash_ctrl.MP_REGION_CFG_2 @ 0x58

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_2				ECC_EN_2				SCRAMBLE_EN_2
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_2				PROG_EN_2				RD_EN_2				EN_2

Bits

Type

Reset

Name

Description

3:0

0x9

EN_2

For FLASH_CTRL2

7:4

0x9

RD_EN_2

For FLASH_CTRL2

11:8

0x9

PROG_EN_2

For FLASH_CTRL2

15:12

0x9

ERASE_EN_2

For FLASH_CTRL2

19:16

0x9

SCRAMBLE_EN_2

For FLASH_CTRL2

23:20

0x9

ECC_EN_2

For FLASH_CTRL2

27:24

0x9

HE_EN_2

For FLASH_CTRL2

flash_ctrl.MP_REGION_CFG_3 @ 0x5c

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_3				ECC_EN_3				SCRAMBLE_EN_3
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_3				PROG_EN_3				RD_EN_3				EN_3

Bits

Type

Reset

Name

Description

3:0

0x9

EN_3

For FLASH_CTRL3

7:4

0x9

RD_EN_3

For FLASH_CTRL3

11:8

0x9

PROG_EN_3

For FLASH_CTRL3

15:12

0x9

ERASE_EN_3

For FLASH_CTRL3

19:16

0x9

SCRAMBLE_EN_3

For FLASH_CTRL3

23:20

0x9

ECC_EN_3

For FLASH_CTRL3

27:24

0x9

HE_EN_3

For FLASH_CTRL3

flash_ctrl.MP_REGION_CFG_4 @ 0x60

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_4				ECC_EN_4				SCRAMBLE_EN_4
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_4				PROG_EN_4				RD_EN_4				EN_4

Bits

Type

Reset

Name

Description

3:0

0x9

EN_4

For FLASH_CTRL4

7:4

0x9

RD_EN_4

For FLASH_CTRL4

11:8

0x9

PROG_EN_4

For FLASH_CTRL4

15:12

0x9

ERASE_EN_4

For FLASH_CTRL4

19:16

0x9

SCRAMBLE_EN_4

For FLASH_CTRL4

23:20

0x9

ECC_EN_4

For FLASH_CTRL4

27:24

0x9

HE_EN_4

For FLASH_CTRL4

flash_ctrl.MP_REGION_CFG_5 @ 0x64

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_5				ECC_EN_5				SCRAMBLE_EN_5
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_5				PROG_EN_5				RD_EN_5				EN_5

Bits

Type

Reset

Name

Description

3:0

0x9

EN_5

For FLASH_CTRL5

7:4

0x9

RD_EN_5

For FLASH_CTRL5

11:8

0x9

PROG_EN_5

For FLASH_CTRL5

15:12

0x9

ERASE_EN_5

For FLASH_CTRL5

19:16

0x9

SCRAMBLE_EN_5

For FLASH_CTRL5

23:20

0x9

ECC_EN_5

For FLASH_CTRL5

27:24

0x9

HE_EN_5

For FLASH_CTRL5

flash_ctrl.MP_REGION_CFG_6 @ 0x68

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_6				ECC_EN_6				SCRAMBLE_EN_6
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_6				PROG_EN_6				RD_EN_6				EN_6

Bits

Type

Reset

Name

Description

3:0

0x9

EN_6

For FLASH_CTRL6

7:4

0x9

RD_EN_6

For FLASH_CTRL6

11:8

0x9

PROG_EN_6

For FLASH_CTRL6

15:12

0x9

ERASE_EN_6

For FLASH_CTRL6

19:16

0x9

SCRAMBLE_EN_6

For FLASH_CTRL6

23:20

0x9

ECC_EN_6

For FLASH_CTRL6

27:24

0x9

HE_EN_6

For FLASH_CTRL6

flash_ctrl.MP_REGION_CFG_7 @ 0x6c

Memory property configuration for data partition

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_7				ECC_EN_7				SCRAMBLE_EN_7
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_7				PROG_EN_7				RD_EN_7				EN_7

Bits

Type

Reset

Name

Description

3:0

0x9

EN_7

For FLASH_CTRL7

7:4

0x9

RD_EN_7

For FLASH_CTRL7

11:8

0x9

PROG_EN_7

For FLASH_CTRL7

15:12

0x9

ERASE_EN_7

For FLASH_CTRL7

19:16

0x9

SCRAMBLE_EN_7

For FLASH_CTRL7

23:20

0x9

ECC_EN_7

For FLASH_CTRL7

27:24

0x9

HE_EN_7

For FLASH_CTRL7

flash_ctrl.MP_REGION_0 @ 0x70

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SIZE_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...SIZE_0							BASE_0

Bits

Type

Reset

Name

Description

8:0

0x0

BASE_0

Region base page. Note the granularity is page, not byte or word

18:9

0x0

SIZE_0

Region size in number of pages. For example, if base is 0 and size is 1, then the region is defined by page 0. If base is 0 and size is 2, then the region is defined by pages 0 and 1.

flash_ctrl.MP_REGION_1 @ 0x74

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SIZE_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...SIZE_1							BASE_1

Bits

Type

Reset

Name

Description

8:0

0x0

BASE_1

For FLASH_CTRL1

18:9

0x0

SIZE_1

For FLASH_CTRL1

flash_ctrl.MP_REGION_2 @ 0x78

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SIZE_2...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...SIZE_2							BASE_2

Bits

Type

Reset

Name

Description

8:0

0x0

BASE_2

For FLASH_CTRL2

18:9

0x0

SIZE_2

For FLASH_CTRL2

flash_ctrl.MP_REGION_3 @ 0x7c

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SIZE_3...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...SIZE_3							BASE_3

Bits

Type

Reset

Name

Description

8:0

0x0

BASE_3

For FLASH_CTRL3

18:9

0x0

SIZE_3

For FLASH_CTRL3

flash_ctrl.MP_REGION_4 @ 0x80

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SIZE_4...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...SIZE_4							BASE_4

Bits

Type

Reset

Name

Description

8:0

0x0

BASE_4

For FLASH_CTRL4

18:9

0x0

SIZE_4

For FLASH_CTRL4

flash_ctrl.MP_REGION_5 @ 0x84

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SIZE_5...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...SIZE_5							BASE_5

Bits

Type

Reset

Name

Description

8:0

0x0

BASE_5

For FLASH_CTRL5

18:9

0x0

SIZE_5

For FLASH_CTRL5

flash_ctrl.MP_REGION_6 @ 0x88

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SIZE_6...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...SIZE_6							BASE_6

Bits

Type

Reset

Name

Description

8:0

0x0

BASE_6

For FLASH_CTRL6

18:9

0x0

SIZE_6

For FLASH_CTRL6

flash_ctrl.MP_REGION_7 @ 0x8c

Memory base and size configuration for data partition

Reset default = 0x0, mask 0x7ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													SIZE_7...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...SIZE_7							BASE_7

Bits

Type

Reset

Name

Description

8:0

0x0

BASE_7

For FLASH_CTRL7

18:9

0x0

SIZE_7

For FLASH_CTRL7

flash_ctrl.DEFAULT_REGION @ 0x90

Default region properties

Reset default = 0x999999, mask 0xffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								HE_EN				ECC_EN
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCRAMBLE_EN				ERASE_EN				PROG_EN				RD_EN

Bits

Type

Reset

Name

Description

3:0

0x9

RD_EN

Region can be read

7:4

0x9

PROG_EN

Region can be programmed

11:8

0x9

ERASE_EN

Region can be erased

15:12

0x9

SCRAMBLE_EN

Region is scramble enabled.

19:16

0x9

ECC_EN

Region is ECC enabled (both integrity and reliability ECC).

23:20

0x9

HE_EN

Region is high endurance enabled.

flash_ctrl.BANK0_INFO0_REGWEN_0 @ 0x94

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_0

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_0

Info0 page write enable. Once set to 0, it can longer be configured to 1

0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

flash_ctrl.BANK0_INFO0_REGWEN_1 @ 0x98

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_1

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_1

For FLASH_CTRL1

flash_ctrl.BANK0_INFO0_REGWEN_2 @ 0x9c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_2

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_2

For FLASH_CTRL2

flash_ctrl.BANK0_INFO0_REGWEN_3 @ 0xa0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_3

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_3

For FLASH_CTRL3

flash_ctrl.BANK0_INFO0_REGWEN_4 @ 0xa4

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_4

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_4

For FLASH_CTRL4

flash_ctrl.BANK0_INFO0_REGWEN_5 @ 0xa8

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_5

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_5

For FLASH_CTRL5

flash_ctrl.BANK0_INFO0_REGWEN_6 @ 0xac

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_6

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_6

For FLASH_CTRL6

flash_ctrl.BANK0_INFO0_REGWEN_7 @ 0xb0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_7

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_7

For FLASH_CTRL7

flash_ctrl.BANK0_INFO0_REGWEN_8 @ 0xb4

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_8

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_8

For FLASH_CTRL8

flash_ctrl.BANK0_INFO0_REGWEN_9 @ 0xb8

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_9

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_9

For FLASH_CTRL9

flash_ctrl.BANK0_INFO0_PAGE_CFG_0 @ 0xbc

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_0				ECC_EN_0				SCRAMBLE_EN_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_0				PROG_EN_0				RD_EN_0				EN_0

Bits

Type

Reset

Name

Description

3:0

0x9

EN_0

Region enabled, following fields apply

7:4

0x9

RD_EN_0

Region can be read

11:8

0x9

PROG_EN_0

Region can be programmed

15:12

0x9

ERASE_EN_0

Region can be erased

19:16

0x9

SCRAMBLE_EN_0

Region is scramble enabled.

23:20

0x9

ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24

0x9

HE_EN_0

Region is high endurance enabled.

flash_ctrl.BANK0_INFO0_PAGE_CFG_1 @ 0xc0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_1				ECC_EN_1				SCRAMBLE_EN_1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_1				PROG_EN_1				RD_EN_1				EN_1

Bits

Type

Reset

Name

Description

3:0

0x9

EN_1

For FLASH_CTRL1

7:4

0x9

RD_EN_1

For FLASH_CTRL1

11:8

0x9

PROG_EN_1

For FLASH_CTRL1

15:12

0x9

ERASE_EN_1

For FLASH_CTRL1

19:16

0x9

SCRAMBLE_EN_1

For FLASH_CTRL1

23:20

0x9

ECC_EN_1

For FLASH_CTRL1

27:24

0x9

HE_EN_1

For FLASH_CTRL1

flash_ctrl.BANK0_INFO0_PAGE_CFG_2 @ 0xc4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_2				ECC_EN_2				SCRAMBLE_EN_2
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_2				PROG_EN_2				RD_EN_2				EN_2

Bits

Type

Reset

Name

Description

3:0

0x9

EN_2

For FLASH_CTRL2

7:4

0x9

RD_EN_2

For FLASH_CTRL2

11:8

0x9

PROG_EN_2

For FLASH_CTRL2

15:12

0x9

ERASE_EN_2

For FLASH_CTRL2

19:16

0x9

SCRAMBLE_EN_2

For FLASH_CTRL2

23:20

0x9

ECC_EN_2

For FLASH_CTRL2

27:24

0x9

HE_EN_2

For FLASH_CTRL2

flash_ctrl.BANK0_INFO0_PAGE_CFG_3 @ 0xc8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_3				ECC_EN_3				SCRAMBLE_EN_3
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_3				PROG_EN_3				RD_EN_3				EN_3

Bits

Type

Reset

Name

Description

3:0

0x9

EN_3

For FLASH_CTRL3

7:4

0x9

RD_EN_3

For FLASH_CTRL3

11:8

0x9

PROG_EN_3

For FLASH_CTRL3

15:12

0x9

ERASE_EN_3

For FLASH_CTRL3

19:16

0x9

SCRAMBLE_EN_3

For FLASH_CTRL3

23:20

0x9

ECC_EN_3

For FLASH_CTRL3

27:24

0x9

HE_EN_3

For FLASH_CTRL3

flash_ctrl.BANK0_INFO0_PAGE_CFG_4 @ 0xcc

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_4				ECC_EN_4				SCRAMBLE_EN_4
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_4				PROG_EN_4				RD_EN_4				EN_4

Bits

Type

Reset

Name

Description

3:0

0x9

EN_4

For FLASH_CTRL4

7:4

0x9

RD_EN_4

For FLASH_CTRL4

11:8

0x9

PROG_EN_4

For FLASH_CTRL4

15:12

0x9

ERASE_EN_4

For FLASH_CTRL4

19:16

0x9

SCRAMBLE_EN_4

For FLASH_CTRL4

23:20

0x9

ECC_EN_4

For FLASH_CTRL4

27:24

0x9

HE_EN_4

For FLASH_CTRL4

flash_ctrl.BANK0_INFO0_PAGE_CFG_5 @ 0xd0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_5				ECC_EN_5				SCRAMBLE_EN_5
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_5				PROG_EN_5				RD_EN_5				EN_5

Bits

Type

Reset

Name

Description

3:0

0x9

EN_5

For FLASH_CTRL5

7:4

0x9

RD_EN_5

For FLASH_CTRL5

11:8

0x9

PROG_EN_5

For FLASH_CTRL5

15:12

0x9

ERASE_EN_5

For FLASH_CTRL5

19:16

0x9

SCRAMBLE_EN_5

For FLASH_CTRL5

23:20

0x9

ECC_EN_5

For FLASH_CTRL5

27:24

0x9

HE_EN_5

For FLASH_CTRL5

flash_ctrl.BANK0_INFO0_PAGE_CFG_6 @ 0xd4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_6				ECC_EN_6				SCRAMBLE_EN_6
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_6				PROG_EN_6				RD_EN_6				EN_6

Bits

Type

Reset

Name

Description

3:0

0x9

EN_6

For FLASH_CTRL6

7:4

0x9

RD_EN_6

For FLASH_CTRL6

11:8

0x9

PROG_EN_6

For FLASH_CTRL6

15:12

0x9

ERASE_EN_6

For FLASH_CTRL6

19:16

0x9

SCRAMBLE_EN_6

For FLASH_CTRL6

23:20

0x9

ECC_EN_6

For FLASH_CTRL6

27:24

0x9

HE_EN_6

For FLASH_CTRL6

flash_ctrl.BANK0_INFO0_PAGE_CFG_7 @ 0xd8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_7				ECC_EN_7				SCRAMBLE_EN_7
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_7				PROG_EN_7				RD_EN_7				EN_7

Bits

Type

Reset

Name

Description

3:0

0x9

EN_7

For FLASH_CTRL7

7:4

0x9

RD_EN_7

For FLASH_CTRL7

11:8

0x9

PROG_EN_7

For FLASH_CTRL7

15:12

0x9

ERASE_EN_7

For FLASH_CTRL7

19:16

0x9

SCRAMBLE_EN_7

For FLASH_CTRL7

23:20

0x9

ECC_EN_7

For FLASH_CTRL7

27:24

0x9

HE_EN_7

For FLASH_CTRL7

flash_ctrl.BANK0_INFO0_PAGE_CFG_8 @ 0xdc

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_8				ECC_EN_8				SCRAMBLE_EN_8
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_8				PROG_EN_8				RD_EN_8				EN_8

Bits

Type

Reset

Name

Description

3:0

0x9

EN_8

For FLASH_CTRL8

7:4

0x9

RD_EN_8

For FLASH_CTRL8

11:8

0x9

PROG_EN_8

For FLASH_CTRL8

15:12

0x9

ERASE_EN_8

For FLASH_CTRL8

19:16

0x9

SCRAMBLE_EN_8

For FLASH_CTRL8

23:20

0x9

ECC_EN_8

For FLASH_CTRL8

27:24

0x9

HE_EN_8

For FLASH_CTRL8

flash_ctrl.BANK0_INFO0_PAGE_CFG_9 @ 0xe0

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_9				ECC_EN_9				SCRAMBLE_EN_9
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_9				PROG_EN_9				RD_EN_9				EN_9

Bits

Type

Reset

Name

Description

3:0

0x9

EN_9

For FLASH_CTRL9

7:4

0x9

RD_EN_9

For FLASH_CTRL9

11:8

0x9

PROG_EN_9

For FLASH_CTRL9

15:12

0x9

ERASE_EN_9

For FLASH_CTRL9

19:16

0x9

SCRAMBLE_EN_9

For FLASH_CTRL9

23:20

0x9

ECC_EN_9

For FLASH_CTRL9

27:24

0x9

HE_EN_9

For FLASH_CTRL9

flash_ctrl.BANK0_INFO1_REGWEN @ 0xe4

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_0

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_0

Info1 page write enable. Once set to 0, it can longer be configured to 1

0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

flash_ctrl.BANK0_INFO1_PAGE_CFG @ 0xe8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_0				ECC_EN_0				SCRAMBLE_EN_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_0				PROG_EN_0				RD_EN_0				EN_0

Bits

Type

Reset

Name

Description

3:0

0x9

EN_0

Region enabled, following fields apply

7:4

0x9

RD_EN_0

Region can be read

11:8

0x9

PROG_EN_0

Region can be programmed

15:12

0x9

ERASE_EN_0

Region can be erased

19:16

0x9

SCRAMBLE_EN_0

Region is scramble enabled.

23:20

0x9

ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24

0x9

HE_EN_0

Region is high endurance enabled.

flash_ctrl.BANK0_INFO2_REGWEN_0 @ 0xec

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_0

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_0

Info2 page write enable. Once set to 0, it can longer be configured to 1

0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

flash_ctrl.BANK0_INFO2_REGWEN_1 @ 0xf0

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_1

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_1

For FLASH_CTRL1

flash_ctrl.BANK0_INFO2_PAGE_CFG_0 @ 0xf4

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_0				ECC_EN_0				SCRAMBLE_EN_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_0				PROG_EN_0				RD_EN_0				EN_0

Bits

Type

Reset

Name

Description

3:0

0x9

EN_0

Region enabled, following fields apply

7:4

0x9

RD_EN_0

Region can be read

11:8

0x9

PROG_EN_0

Region can be programmed

15:12

0x9

ERASE_EN_0

Region can be erased

19:16

0x9

SCRAMBLE_EN_0

Region is scramble enabled.

23:20

0x9

ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24

0x9

HE_EN_0

Region is high endurance enabled.

flash_ctrl.BANK0_INFO2_PAGE_CFG_1 @ 0xf8

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_1				ECC_EN_1				SCRAMBLE_EN_1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_1				PROG_EN_1				RD_EN_1				EN_1

Bits

Type

Reset

Name

Description

3:0

0x9

EN_1

For FLASH_CTRL1

7:4

0x9

RD_EN_1

For FLASH_CTRL1

11:8

0x9

PROG_EN_1

For FLASH_CTRL1

15:12

0x9

ERASE_EN_1

For FLASH_CTRL1

19:16

0x9

SCRAMBLE_EN_1

For FLASH_CTRL1

23:20

0x9

ECC_EN_1

For FLASH_CTRL1

27:24

0x9

HE_EN_1

For FLASH_CTRL1

flash_ctrl.BANK1_INFO0_REGWEN_0 @ 0xfc

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_0

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_0

Info0 page write enable. Once set to 0, it can longer be configured to 1

0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

flash_ctrl.BANK1_INFO0_REGWEN_1 @ 0x100

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_1

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_1

For FLASH_CTRL1

flash_ctrl.BANK1_INFO0_REGWEN_2 @ 0x104

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_2

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_2

For FLASH_CTRL2

flash_ctrl.BANK1_INFO0_REGWEN_3 @ 0x108

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_3

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_3

For FLASH_CTRL3

flash_ctrl.BANK1_INFO0_REGWEN_4 @ 0x10c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_4

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_4

For FLASH_CTRL4

flash_ctrl.BANK1_INFO0_REGWEN_5 @ 0x110

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_5

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_5

For FLASH_CTRL5

flash_ctrl.BANK1_INFO0_REGWEN_6 @ 0x114

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_6

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_6

For FLASH_CTRL6

flash_ctrl.BANK1_INFO0_REGWEN_7 @ 0x118

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_7

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_7

For FLASH_CTRL7

flash_ctrl.BANK1_INFO0_REGWEN_8 @ 0x11c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_8

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_8

For FLASH_CTRL8

flash_ctrl.BANK1_INFO0_REGWEN_9 @ 0x120

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_9

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_9

For FLASH_CTRL9

flash_ctrl.BANK1_INFO0_PAGE_CFG_0 @ 0x124

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_0				ECC_EN_0				SCRAMBLE_EN_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_0				PROG_EN_0				RD_EN_0				EN_0

Bits

Type

Reset

Name

Description

3:0

0x9

EN_0

Region enabled, following fields apply

7:4

0x9

RD_EN_0

Region can be read

11:8

0x9

PROG_EN_0

Region can be programmed

15:12

0x9

ERASE_EN_0

Region can be erased

19:16

0x9

SCRAMBLE_EN_0

Region is scramble enabled.

23:20

0x9

ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24

0x9

HE_EN_0

Region is high endurance enabled.

flash_ctrl.BANK1_INFO0_PAGE_CFG_1 @ 0x128

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_1				ECC_EN_1				SCRAMBLE_EN_1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_1				PROG_EN_1				RD_EN_1				EN_1

Bits

Type

Reset

Name

Description

3:0

0x9

EN_1

For FLASH_CTRL1

7:4

0x9

RD_EN_1

For FLASH_CTRL1

11:8

0x9

PROG_EN_1

For FLASH_CTRL1

15:12

0x9

ERASE_EN_1

For FLASH_CTRL1

19:16

0x9

SCRAMBLE_EN_1

For FLASH_CTRL1

23:20

0x9

ECC_EN_1

For FLASH_CTRL1

27:24

0x9

HE_EN_1

For FLASH_CTRL1

flash_ctrl.BANK1_INFO0_PAGE_CFG_2 @ 0x12c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_2				ECC_EN_2				SCRAMBLE_EN_2
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_2				PROG_EN_2				RD_EN_2				EN_2

Bits

Type

Reset

Name

Description

3:0

0x9

EN_2

For FLASH_CTRL2

7:4

0x9

RD_EN_2

For FLASH_CTRL2

11:8

0x9

PROG_EN_2

For FLASH_CTRL2

15:12

0x9

ERASE_EN_2

For FLASH_CTRL2

19:16

0x9

SCRAMBLE_EN_2

For FLASH_CTRL2

23:20

0x9

ECC_EN_2

For FLASH_CTRL2

27:24

0x9

HE_EN_2

For FLASH_CTRL2

flash_ctrl.BANK1_INFO0_PAGE_CFG_3 @ 0x130

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_3				ECC_EN_3				SCRAMBLE_EN_3
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_3				PROG_EN_3				RD_EN_3				EN_3

Bits

Type

Reset

Name

Description

3:0

0x9

EN_3

For FLASH_CTRL3

7:4

0x9

RD_EN_3

For FLASH_CTRL3

11:8

0x9

PROG_EN_3

For FLASH_CTRL3

15:12

0x9

ERASE_EN_3

For FLASH_CTRL3

19:16

0x9

SCRAMBLE_EN_3

For FLASH_CTRL3

23:20

0x9

ECC_EN_3

For FLASH_CTRL3

27:24

0x9

HE_EN_3

For FLASH_CTRL3

flash_ctrl.BANK1_INFO0_PAGE_CFG_4 @ 0x134

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_4				ECC_EN_4				SCRAMBLE_EN_4
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_4				PROG_EN_4				RD_EN_4				EN_4

Bits

Type

Reset

Name

Description

3:0

0x9

EN_4

For FLASH_CTRL4

7:4

0x9

RD_EN_4

For FLASH_CTRL4

11:8

0x9

PROG_EN_4

For FLASH_CTRL4

15:12

0x9

ERASE_EN_4

For FLASH_CTRL4

19:16

0x9

SCRAMBLE_EN_4

For FLASH_CTRL4

23:20

0x9

ECC_EN_4

For FLASH_CTRL4

27:24

0x9

HE_EN_4

For FLASH_CTRL4

flash_ctrl.BANK1_INFO0_PAGE_CFG_5 @ 0x138

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_5				ECC_EN_5				SCRAMBLE_EN_5
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_5				PROG_EN_5				RD_EN_5				EN_5

Bits

Type

Reset

Name

Description

3:0

0x9

EN_5

For FLASH_CTRL5

7:4

0x9

RD_EN_5

For FLASH_CTRL5

11:8

0x9

PROG_EN_5

For FLASH_CTRL5

15:12

0x9

ERASE_EN_5

For FLASH_CTRL5

19:16

0x9

SCRAMBLE_EN_5

For FLASH_CTRL5

23:20

0x9

ECC_EN_5

For FLASH_CTRL5

27:24

0x9

HE_EN_5

For FLASH_CTRL5

flash_ctrl.BANK1_INFO0_PAGE_CFG_6 @ 0x13c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_6				ECC_EN_6				SCRAMBLE_EN_6
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_6				PROG_EN_6				RD_EN_6				EN_6

Bits

Type

Reset

Name

Description

3:0

0x9

EN_6

For FLASH_CTRL6

7:4

0x9

RD_EN_6

For FLASH_CTRL6

11:8

0x9

PROG_EN_6

For FLASH_CTRL6

15:12

0x9

ERASE_EN_6

For FLASH_CTRL6

19:16

0x9

SCRAMBLE_EN_6

For FLASH_CTRL6

23:20

0x9

ECC_EN_6

For FLASH_CTRL6

27:24

0x9

HE_EN_6

For FLASH_CTRL6

flash_ctrl.BANK1_INFO0_PAGE_CFG_7 @ 0x140

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_7				ECC_EN_7				SCRAMBLE_EN_7
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_7				PROG_EN_7				RD_EN_7				EN_7

Bits

Type

Reset

Name

Description

3:0

0x9

EN_7

For FLASH_CTRL7

7:4

0x9

RD_EN_7

For FLASH_CTRL7

11:8

0x9

PROG_EN_7

For FLASH_CTRL7

15:12

0x9

ERASE_EN_7

For FLASH_CTRL7

19:16

0x9

SCRAMBLE_EN_7

For FLASH_CTRL7

23:20

0x9

ECC_EN_7

For FLASH_CTRL7

27:24

0x9

HE_EN_7

For FLASH_CTRL7

flash_ctrl.BANK1_INFO0_PAGE_CFG_8 @ 0x144

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_8				ECC_EN_8				SCRAMBLE_EN_8
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_8				PROG_EN_8				RD_EN_8				EN_8

Bits

Type

Reset

Name

Description

3:0

0x9

EN_8

For FLASH_CTRL8

7:4

0x9

RD_EN_8

For FLASH_CTRL8

11:8

0x9

PROG_EN_8

For FLASH_CTRL8

15:12

0x9

ERASE_EN_8

For FLASH_CTRL8

19:16

0x9

SCRAMBLE_EN_8

For FLASH_CTRL8

23:20

0x9

ECC_EN_8

For FLASH_CTRL8

27:24

0x9

HE_EN_8

For FLASH_CTRL8

flash_ctrl.BANK1_INFO0_PAGE_CFG_9 @ 0x148

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_9				ECC_EN_9				SCRAMBLE_EN_9
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_9				PROG_EN_9				RD_EN_9				EN_9

Bits

Type

Reset

Name

Description

3:0

0x9

EN_9

For FLASH_CTRL9

7:4

0x9

RD_EN_9

For FLASH_CTRL9

11:8

0x9

PROG_EN_9

For FLASH_CTRL9

15:12

0x9

ERASE_EN_9

For FLASH_CTRL9

19:16

0x9

SCRAMBLE_EN_9

For FLASH_CTRL9

23:20

0x9

ECC_EN_9

For FLASH_CTRL9

27:24

0x9

HE_EN_9

For FLASH_CTRL9

flash_ctrl.BANK1_INFO1_REGWEN @ 0x14c

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_0

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_0

Info1 page write enable. Once set to 0, it can longer be configured to 1

0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

flash_ctrl.BANK1_INFO1_PAGE_CFG @ 0x150

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_0				ECC_EN_0				SCRAMBLE_EN_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_0				PROG_EN_0				RD_EN_0				EN_0

Bits

Type

Reset

Name

Description

3:0

0x9

EN_0

Region enabled, following fields apply

7:4

0x9

RD_EN_0

Region can be read

11:8

0x9

PROG_EN_0

Region can be programmed

15:12

0x9

ERASE_EN_0

Region can be erased

19:16

0x9

SCRAMBLE_EN_0

Region is scramble enabled.

23:20

0x9

ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24

0x9

HE_EN_0

Region is high endurance enabled.

flash_ctrl.BANK1_INFO2_REGWEN_0 @ 0x154

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_0

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_0

Info2 page write enable. Once set to 0, it can longer be configured to 1

0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

flash_ctrl.BANK1_INFO2_REGWEN_1 @ 0x158

Memory region registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															REGION_1

Bits

Type

Reset

Name

Description

rw0c

0x1

REGION_1

For FLASH_CTRL1

flash_ctrl.BANK1_INFO2_PAGE_CFG_0 @ 0x15c

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_0				ECC_EN_0				SCRAMBLE_EN_0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_0				PROG_EN_0				RD_EN_0				EN_0

Bits

Type

Reset

Name

Description

3:0

0x9

EN_0

Region enabled, following fields apply

7:4

0x9

RD_EN_0

Region can be read

11:8

0x9

PROG_EN_0

Region can be programmed

15:12

0x9

ERASE_EN_0

Region can be erased

19:16

0x9

SCRAMBLE_EN_0

Region is scramble enabled.

23:20

0x9

ECC_EN_0

Region is ECC enabled (both integrity and reliability ECC).

27:24

0x9

HE_EN_0

Region is high endurance enabled.

flash_ctrl.BANK1_INFO2_PAGE_CFG_1 @ 0x160

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default = 0x9999999, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HE_EN_1				ECC_EN_1				SCRAMBLE_EN_1
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ERASE_EN_1				PROG_EN_1				RD_EN_1				EN_1

Bits

Type

Reset

Name

Description

3:0

0x9

EN_1

For FLASH_CTRL1

7:4

0x9

RD_EN_1

For FLASH_CTRL1

11:8

0x9

PROG_EN_1

For FLASH_CTRL1

15:12

0x9

ERASE_EN_1

For FLASH_CTRL1

19:16

0x9

SCRAMBLE_EN_1

For FLASH_CTRL1

23:20

0x9

ECC_EN_1

For FLASH_CTRL1

27:24

0x9

HE_EN_1

For FLASH_CTRL1

flash_ctrl.HW_INFO_CFG_OVERRIDE @ 0x164

HW interface info configuration rule overrides

Reset default = 0x99, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								ECC_DIS				SCRAMBLE_DIS

Bits

Type

Reset

Name

Description

3:0

0x9

SCRAMBLE_DIS

The hardwired hardware info configuration rules for scramble enable are logically AND'd with this field. If the hardware rules hardwires scramble to enable, we can disable via software if needed.

By default this field if false.

7:4

0x9

ECC_DIS

The hardwired hardware info configuration rules for ECC enable are logically AND'd with this field. If the hardware rules hardwires ECC to enable, we can disable via software if needed.

By default this field if false.

flash_ctrl.BANK_CFG_REGWEN @ 0x168

Bank configuration registers configuration enable.

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															BANK

Bits

Type

Reset

Name

Description

rw0c

0x1

BANK

Bank register write enable. Once set to 0, it can longer be configured to 1

0x0	Bank locked	Bank can no longer be configured until next reset
0x1	Bank enabled	Bank can be configured

flash_ctrl.MP_BANK_CFG_SHADOWED @ 0x16c

Memory properties bank configuration

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														ERASE_EN_1	ERASE_EN_0

Bits

Type

Reset

Name

Description

0x0

ERASE_EN_0

Bank wide erase enable

0x0

ERASE_EN_1

Bank wide erase enable

flash_ctrl.OP_STATUS @ 0x170

Flash Operation Status

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														err	done

Bits Type Reset Name Description

0x0

done

Flash operation done. Set by HW, cleared by SW

0x0

err

Flash operation error. Set by HW, cleared by SW. See ERR_CODE for more details.

flash_ctrl.STATUS @ 0x174

Flash Controller Status

Reset default = 0xa, mask 0x3f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										initialized	init_wip	prog_empty	prog_full	rd_empty	rd_full

Bits

Type

Reset

Name

Description

0x0

rd_full

Flash read FIFO full, software must consume data

0x1

rd_empty

Flash read FIFO empty

0x0

prog_full

Flash program FIFO full

0x1

prog_empty

Flash program FIFO empty, software must provide data

0x0

init_wip

Flash controller undergoing init, inclusive of phy init

0x0

initialized

Flash controller initialized

flash_ctrl.DEBUG_STATE @ 0x178

Current flash fsm state

Reset default = 0x0, mask 0x7ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					lcmgr_state

Bits

Type

Reset

Name

Description

10:0

lcmgr_state

Current lcmgr interface staet

flash_ctrl.ERR_CODE @ 0x17c

Flash error code register. This register tabulates detailed error status of the flash. This is separate from OP_STATUS, which is used to indicate the current state of the software initiated flash operation.

Reset default = 0x0, mask 0xff

Note, all errors in this register are considered recoverable errors, ie, errors that could have been generated by software.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								macro_err	update_err	prog_type_err	prog_win_err	prog_err	rd_err	mp_err	op_err

Bits Type Reset Name Description

rw1c

0x0

op_err

Software has supplied an undefined operation. See CONTROL.OP for list of valid operations.

rw1c

0x0

mp_err

Flash access has encountered an access permission error. Please see ERR_ADDR for exact address. This is a synchronous error.

rw1c

0x0

rd_err

Flash read has an error. This could be a reliability ECC error or an storage integrity error encountered during a software issued controller read, see STD_FAULT_STATUS. See ERR_ADDR for exact address. This is a synchronous error.

rw1c

0x0

prog_err

Flash program has an error. This could be a program integrity error, see STD_FAULT_STATUS. This is a synchronous error.

rw1c

0x0

prog_win_err

Flash program has a window resolution error. Ie, the start of program and end of program are in different windows. Please check ERR_ADDR. This is a synchronous error.

rw1c

0x0

prog_type_err

Flash program selected unavailable type, see PROG_TYPE_EN. This is a synchronous error.

rw1c

0x0

update_err

A shadow register encountered an update error. This is an asynchronous error.

rw1c

0x0

macro_err

A recoverable error has been encountered in the flash macro. Please read the flash macro status registers for more details.

flash_ctrl.STD_FAULT_STATUS @ 0x180

This register tabulates standard fault status of the flash.

Reset default = 0x0, mask 0x1ff

These represent errors that occur in the standard structures of the design. For example fsm integrity, counter integrity and tlul integrity.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							fifo_err	ctrl_cnt_err	phy_fsm_err	storage_err	arb_fsm_err	lcmgr_intg_err	lcmgr_err	prog_intg_err	reg_intg_err

Bits

Type

Reset

Name

Description

0x0

reg_intg_err

The flash controller encountered a register integrity error.

0x0

prog_intg_err

The flash controller encountered a program data transmission integrity error.

0x0

lcmgr_err

The life cycle management interface has encountered a fatal error. The error is either an FSM sparse encoding error or a count error.

0x0

lcmgr_intg_err

The life cycle management interface has encountered a transmission integrity error. This is an integrity error on the generated integrity during a life cycle management interface read.

0x0

arb_fsm_err

The arbiter fsm has encountered a sparse encoding error.

0x0

storage_err

A shadow register encountered a storage error.

0x0

phy_fsm_err

A flash phy fsm has encountered a sparse encoding error.

0x0

ctrl_cnt_err

Flash ctrl read/prog has encountered a count error.

0x0

fifo_err

Flash primitive fifo's have encountered a count error.

flash_ctrl.FAULT_STATUS @ 0x184

This register tabulates customized fault status of the flash.

Reset default = 0x0, mask 0xfff

These are errors that are impossible to have been caused by software or unrecoverable in nature.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				host_gnt_err	arb_err	spurious_ack	phy_storage_err	phy_relbl_err	seed_err	prog_type_err	prog_win_err	prog_err	rd_err	mp_err	op_err

Bits Type Reset Name Description

0x0

op_err

The flash life cycle management interface has supplied an undefined operation. See CONTROL.OP for list of valid operations.

0x0

mp_err

The flash life cycle management interface encountered a memory permission error.

0x0

rd_err

The flash life cycle management interface encountered a read error. This could be a reliability ECC error or an integrity ECC error encountered during a read, see STD_FAULT_STATUS for more details.

0x0

prog_err

The flash life cycle management interface encountered a program error. This could be a program integirty eror, see STD_FAULT_STATUS for more details.

0x0

prog_win_err

The flash life cycle management interface encountered a program resolution error.

0x0

prog_type_err

The flash life cycle management interface encountered a program type error. A program type not supported by the flash macro was issued.

0x0

seed_err

The seed reading process encountered an unexpected error.

0x0

phy_relbl_err

The flash macro encountered a storage reliability ECC error.

0x0

phy_storage_err

The flash macro encountered a storage integrity ECC error.

0x0

spurious_ack

The flash emitted an unexpected acknowledgement.

0x0

arb_err

The phy arbiter encountered inconsistent results.

0x0

host_gnt_err

A host transaction was granted with illegal properties.

flash_ctrl.ERR_ADDR @ 0x188

Synchronous error address

Reset default = 0x0, mask 0xfffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												ERR_ADDR...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...ERR_ADDR

Bits

Type

Reset

Name

Description

19:0

0x0

ERR_ADDR

flash_ctrl.ECC_SINGLE_ERR_CNT @ 0x18c

Total number of single bit ECC error count

Reset default = 0x0, mask 0xffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ECC_SINGLE_ERR_CNT_1								ECC_SINGLE_ERR_CNT_0

Bits

Type

Reset

Name

Description

7:0

0x0

ECC_SINGLE_ERR_CNT_0

This count will not wrap when saturated

15:8

0x0

ECC_SINGLE_ERR_CNT_1

This count will not wrap when saturated

flash_ctrl.ECC_SINGLE_ERR_ADDR_0 @ 0x190

Latest address of ECC single err

Reset default = 0x0, mask 0xfffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												ECC_SINGLE_ERR_ADDR_0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...ECC_SINGLE_ERR_ADDR_0

Bits

Type

Reset

Name

Description

19:0

0x0

ECC_SINGLE_ERR_ADDR_0

Latest single error address for this bank

flash_ctrl.ECC_SINGLE_ERR_ADDR_1 @ 0x194

Latest address of ECC single err

Reset default = 0x0, mask 0xfffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												ECC_SINGLE_ERR_ADDR_1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...ECC_SINGLE_ERR_ADDR_1

Bits

Type

Reset

Name

Description

19:0

0x0

ECC_SINGLE_ERR_ADDR_1

For ECC_SINGLE_ERR1

flash_ctrl.PHY_ALERT_CFG @ 0x198

Phy alert configuration

Reset default = 0x0, mask 0x3

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														alert_trig	alert_ack

Bits

Type

Reset

Name

Description

0x0

alert_ack

Acknowledge flash phy alert

0x0

alert_trig

Trigger flash phy alert

flash_ctrl.PHY_STATUS @ 0x19c

Flash Phy Status

Reset default = 0x6, mask 0x7

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													prog_repair_avail	prog_normal_avail	init_wip

Bits

Type

Reset

Name

Description

0x0

init_wip

Flash phy controller initializing

0x1

prog_normal_avail

Normal program supported

0x1

prog_repair_avail

Program repair supported

flash_ctrl.Scratch @ 0x1a0

Flash Controller Scratch

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
data...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...data

Bits

Type

Reset

Name

Description

31:0

0x0

data

Flash ctrl scratch register

flash_ctrl.FIFO_LVL @ 0x1a4

Programmable depth where FIFOs should generate interrupts

Reset default = 0xf0f, mask 0x1f1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			RD								PROG

Bits

Type

Reset

Name

Description

4:0

0xf

PROG

When the program FIFO drains to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.

7:5

Reserved

12:8

0xf

When the read FIFO fills to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.

flash_ctrl.FIFO_RST @ 0x1a8

Reset for flash controller FIFOs

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EN

Bits

Type

Reset

Name

Description

0x0

Active high resets for both program and read FIFOs. This is especially useful after the controller encounters an error of some kind. This bit will hold the FIFO in reset as long as it is set.

flash_ctrl.CURR_FIFO_LVL @ 0x1ac

Current program and read fifo depth

Reset default = 0x0, mask 0x1f1f

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			RD								PROG

Bits

Type

Reset

Name

Description

4:0

0x0

PROG

Current program fifo depth

7:5

Reserved

12:8

0x0

Current read fifo depth

flash_ctrl.prog_fifo @ + 0x1b0

1 item wo window

Byte writes are not supported

+0x1b0

Flash program FIFO.

The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed by software after a program operation has been initiated via the CONTROL register. This ensures accidental programming of the program FIFO cannot lock up the system.

flash_ctrl.rd_fifo @ + 0x1b4

1 item ro window

Byte writes are not supported

+0x1b4

Flash read FIFO.

The FIFO is 16 entries of 4B flash words

Registers visible under device interface `prim`

Summary
Name	Offset	Length	Description
flash_ctrl.CSR0_REGWEN	0x0	4
flash_ctrl.CSR1	0x4	4
flash_ctrl.CSR2	0x8	4
flash_ctrl.CSR3	0xc	4
flash_ctrl.CSR4	0x10	4
flash_ctrl.CSR5	0x14	4
flash_ctrl.CSR6	0x18	4
flash_ctrl.CSR7	0x1c	4
flash_ctrl.CSR8	0x20	4
flash_ctrl.CSR9	0x24	4
flash_ctrl.CSR10	0x28	4
flash_ctrl.CSR11	0x2c	4
flash_ctrl.CSR12	0x30	4
flash_ctrl.CSR13	0x34	4
flash_ctrl.CSR14	0x38	4
flash_ctrl.CSR15	0x3c	4
flash_ctrl.CSR16	0x40	4
flash_ctrl.CSR17	0x44	4
flash_ctrl.CSR18	0x48	4
flash_ctrl.CSR19	0x4c	4
flash_ctrl.CSR20	0x50	4

flash_ctrl.CSR0_REGWEN @ 0x0

Reset default = 0x1, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															field0

Bits

Type

Reset

Name

Description

rw0c

0x1

field0

Other values are reserved.

flash_ctrl.CSR1 @ 0x4

Reset default = 0x0, mask 0x1fff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			field1					field0

Bits

Type

Reset

Name

Description

7:0

0x0

field0

Other values are reserved.

12:8

0x0

field1

Other values are reserved.

flash_ctrl.CSR2 @ 0x8

Reset default = 0x0, mask 0xff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								field7	field6	field5	field4	field3	field2	field1	field0

Bits

Type

Reset

Name

Description

rw1c

0x0

field0

Other values are reserved.

rw1c

0x0

field1

Other values are reserved.

rw1c

0x0

field2

Other values are reserved.

0x0

field3

Other values are reserved.

rw1c

0x0

field4

Other values are reserved.

rw1c

0x0

field5

Other values are reserved.

rw1c

0x0

field6

Other values are reserved.

0x0

field7

Other values are reserved.

flash_ctrl.CSR3 @ 0xc

Reset default = 0x0, mask 0xfffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				field9		field8		field7			field6	field5			field4...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field4		field3			field2			field1				field0

Bits

Type

Reset

Name

Description

3:0

0x0

field0

Other values are reserved.

7:4

0x0

field1

Other values are reserved.

10:8

0x0

field2

Other values are reserved.

13:11

0x0

field3

Other values are reserved.

16:14

0x0

field4

Other values are reserved.

19:17

0x0

field5

Other values are reserved.

0x0

field6

Other values are reserved.

23:21

0x0

field7

Other values are reserved.

25:24

0x0

field8

Other values are reserved.

27:26

0x0

field9

Other values are reserved.

flash_ctrl.CSR4 @ 0x10

Reset default = 0x0, mask 0xfff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				field3			field2			field1			field0

Bits

Type

Reset

Name

Description

2:0

0x0

field0

Other values are reserved.

5:3

0x0

field1

Other values are reserved.

8:6

0x0

field2

Other values are reserved.

11:9

0x0

field3

Other values are reserved.

flash_ctrl.CSR5 @ 0x14

Reset default = 0x0, mask 0x7fffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									field4				field3...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field3		field2									field1		field0

Bits

Type

Reset

Name

Description

2:0

0x0

field0

Other values are reserved.

4:3

0x0

field1

Other values are reserved.

13:5

0x0

field2

Other values are reserved.

18:14

0x0

field3

Other values are reserved.

22:19

0x0

field4

Other values are reserved.

flash_ctrl.CSR6 @ 0x18

Reset default = 0x0, mask 0x1ffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							field8	field7	field6		field5		field4		field3...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field3		field2								field1			field0

Bits

Type

Reset

Name

Description

2:0

0x0

field0

Other values are reserved.

5:3

0x0

field1

Other values are reserved.

13:6

0x0

field2

Other values are reserved.

16:14

0x0

field3

Other values are reserved.

18:17

0x0

field4

Other values are reserved.

20:19

0x0

field5

Other values are reserved.

22:21

0x0

field6

Other values are reserved.

0x0

field7

Other values are reserved.

0x0

field8

Other values are reserved.

flash_ctrl.CSR7 @ 0x1c

Reset default = 0x0, mask 0x1ffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															field1...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field1								field0

Bits

Type

Reset

Name

Description

7:0

0x0

field0

Other values are reserved.

16:8

0x0

field1

Other values are reserved.

flash_ctrl.CSR8 @ 0x20

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
field0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field0

Bits

Type

Reset

Name

Description

31:0

0x0

field0

Other values are reserved.

flash_ctrl.CSR9 @ 0x24

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
field0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field0

Bits

Type

Reset

Name

Description

31:0

0x0

field0

Other values are reserved.

flash_ctrl.CSR10 @ 0x28

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
field0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field0

Bits

Type

Reset

Name

Description

31:0

0x0

field0

Other values are reserved.

flash_ctrl.CSR11 @ 0x2c

Reset default = 0x0, mask 0xffffffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
field0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field0

Bits

Type

Reset

Name

Description

31:0

0x0

field0

Other values are reserved.

flash_ctrl.CSR12 @ 0x30

Reset default = 0x0, mask 0x3ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						field0

Bits

Type

Reset

Name

Description

9:0

0x0

field0

Other values are reserved.

flash_ctrl.CSR13 @ 0x34

Reset default = 0x0, mask 0x1fffff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											field1	field0...
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
...field0

Bits

Type

Reset

Name

Description

19:0

0x0

field0

Other values are reserved.

0x0

field1

Other values are reserved.

flash_ctrl.CSR14 @ 0x38

Reset default = 0x0, mask 0x1ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							field1	field0

Bits

Type

Reset

Name

Description

7:0

0x0

field0

Other values are reserved.

0x0

field1

Other values are reserved.

flash_ctrl.CSR15 @ 0x3c

Reset default = 0x0, mask 0x1ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							field1	field0

Bits

Type

Reset

Name

Description

7:0

0x0

field0

Other values are reserved.

0x0

field1

Other values are reserved.

flash_ctrl.CSR16 @ 0x40

Reset default = 0x0, mask 0x1ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							field1	field0

Bits

Type

Reset

Name

Description

7:0

0x0

field0

Other values are reserved.

0x0

field1

Other values are reserved.

flash_ctrl.CSR17 @ 0x44

Reset default = 0x0, mask 0x1ff

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							field1	field0

Bits

Type

Reset

Name

Description

7:0

0x0

field0

Other values are reserved.

0x0

field1

Other values are reserved.

flash_ctrl.CSR18 @ 0x48

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															field0

Bits

Type

Reset

Name

Description

0x0

field0

Other values are reserved.

flash_ctrl.CSR19 @ 0x4c

Reset default = 0x0, mask 0x1

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															field0

Bits

Type

Reset

Name

Description

0x0

field0

Other values are reserved.

flash_ctrl.CSR20 @ 0x50

Reset default = 0x0, mask 0x7

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													field2	field1	field0

Bits

Type

Reset

Name

Description

rw1c

0x0

field0

Other values are reserved.

rw1c

0x0

field1

Other values are reserved.

0x0

field2

Other values are reserved.

Registers visible under device interface `mem`

This interface does not expose any registers.

OpenTitan Documentation

Hardware Interfaces and Registers

Interfaces

Registers

Registers visible under device interface core

Registers visible under device interface prim

Registers visible under device interface mem

Registers visible under device interface `core`

Registers visible under device interface `prim`

Registers visible under device interface `mem`