Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module flash_ctrl has the following hardware interfaces defined

Primary Clock: clk_i
Other Clocks: clk_otp_i
Bus Device Interfaces (TL-UL): core_tl, prim_tl, mem_tl
Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO

Pin name	Direction	Description
tck	input	jtag clock
tms	input	jtag tms
tdi	input	jtag input
tdo	output	jtag output

Inter-Module Signals

Port Name	Package::Struct	Type	Act	Width
otp	otp_ctrl_pkg::flash_otp_key	req_rsp	req	1
lc_nvm_debug_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
flash_bist_enable	prim_mubi_pkg::mubi4	uni	rcv	1
flash_power_down_h	logic	uni	rcv	1
flash_power_ready_h	logic	uni	rcv	1
flash_test_mode_a		io	none	2
flash_test_voltage_h		io	none	1
lc_creator_seed_sw_rw_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_owner_seed_sw_rw_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_iso_part_sw_rd_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_iso_part_sw_wr_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_seed_hw_rd_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
lc_escalate_en	lc_ctrl_pkg::lc_tx	uni	rcv	1
rma_req	lc_ctrl_pkg::lc_tx	uni	rcv	1
rma_ack	lc_ctrl_pkg::lc_tx	uni	req	1
rma_seed	lc_ctrl_pkg::lc_flash_rma_seed	uni	rcv	1
pwrmgr	pwrmgr_pkg::pwr_flash	uni	req	1
keymgr	flash_ctrl_pkg::keymgr_flash	uni	req	1
obs_ctrl	ast_pkg::ast_obs_ctrl	uni	rcv	1
fla_obs	logic	uni	req	8
core_tl	tlul_pkg::tl	req_rsp	rsp	1
prim_tl	tlul_pkg::tl	req_rsp	rsp	1
mem_tl	tlul_pkg::tl	req_rsp	rsp	1

Interrupts

Interrupt Name	Type	Description
prog_empty	Event	Program FIFO empty
prog_lvl	Event	Program FIFO drained to level
rd_full	Event	Read FIFO full
rd_lvl	Event	Read FIFO filled to level
op_done	Event	Operation complete
corr_err	Event	Correctable error encountered

Security Alerts

Alert Name	Description
recov_err	flash recoverable errors
fatal_std_err	flash standard fatal errors
fatal_err	flash fatal errors
fatal_prim_flash_alert	Fatal alert triggered inside the flash primitive, including fatal TL-UL bus integrity faults of the test interface.
recov_prim_flash_alert	Recoverable alert triggered inside the flash primitive.

Security Countermeasures

Countermeasure ID	Description
FLASH_CTRL.REG.BUS.INTEGRITY	End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules.
FLASH_CTRL.HOST.BUS.INTEGRITY	End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules.
FLASH_CTRL.MEM.BUS.INTEGRITY	End-to-end bus integrity scheme. Since there are multiple access points for flash, please see Transmission Integrity Faults in the documentation for more details. The bus integrity scheme for flash is different from other comportable modules.
FLASH_CTRL.SCRAMBLE.KEY.SIDELOAD	The scrambling key is sideloaded from OTP and thus unreadable by SW.
FLASH_CTRL.LC_CTRL.INTERSIG.MUBI	Life cycle control signals are used control information partition access and flash debug access. See secret information partition, isolated information partitions and jtag connection in documentation for more details.
FLASH_CTRL.CTRL.CONFIG.REGWEN	Configurations cannot be changed when an operation is ongoing.
FLASH_CTRL.DATA_REGIONS.CONFIG.REGWEN	Each data region has a configurable regwen.
FLASH_CTRL.DATA_REGIONS.CONFIG.SHADOW	Data region configuration is shadowed.
FLASH_CTRL.INFO_REGIONS.CONFIG.REGWEN	Each info page of each type in each bank has separate regwen.
FLASH_CTRL.INFO_REGIONS.CONFIG.SHADOW	Each info page is shadowed.
FLASH_CTRL.BANK.CONFIG.REGWEN	Each bank has separate regwen for bank erase.
FLASH_CTRL.BANK.CONFIG.SHADOW	Each bank has separate regwen for bank erase.
FLASH_CTRL.MEM.CTRL.GLOBAL_ESC	Global escalation causes memory to no longer be accessible.
FLASH_CTRL.MEM.CTRL.LOCAL_ESC	A subset of fatal errors cause memory to no longer be accessible. This subset is defined in `STD_FAULT_STATUS.`
FLASH_CTRL.MEM_DISABLE.CONFIG.MUBI	Software control for flash disable is multibit. The register is `DIS.`
FLASH_CTRL.EXEC.CONFIG.REDUN	Software control for flash enable is 32-bit constant. The register is `EXEC.`
FLASH_CTRL.MEM.SCRAMBLE	The flash supports XEX scrambling. The cipher used is PRINCE. The scrambling scheme is enabled by software, please see flash scrambling in documentation for more details.
FLASH_CTRL.MEM.INTEGRITY	The flash supports two layers of ECC integrity: one layer is for integrity, and the other layer is for reliability. These ECCs are enabled and disabled together by software. Please see Flash ECC in the documentation for more details.
FLASH_CTRL.RMA_ENTRY.MEM.SEC_WIPE	RMA entry entry wipes flash memory with random data.
FLASH_CTRL.CTRL.FSM.SPARSE	RMA handling FSMs in flash_ctrl_lcmgr are sparsely encoded. FSM in flash_ctrl_arb is sparsely encoded.
FLASH_CTRL.PHY.FSM.SPARSE	PHY FSMs are sparsely encoded.
FLASH_CTRL.PHY_PROG.FSM.SPARSE	PHY program FSMs are sparsely encoded.
FLASH_CTRL.CTR.REDUN	flash_ctrl_lcmgr handling counters are redundantly encoded. This includes seed count and address count used during seed reading phase, as well as word count, page count and wipe index in RMA entry phase.
FLASH_CTRL.PHY_ARBITER.CTRL.REDUN	The phy arbiter for controller and host is redundant. The arbiter has two instance underneath that are constantly compared to each other.
FLASH_CTRL.PHY_HOST_GRANT.CTRL.CONSISTENCY	The host grant is consistency checked. If the host is ever granted with info partition access, it is an error. If the host is ever granted at the same time as a program/erase operation, it is an error.
FLASH_CTRL.PHY_ACK.CTRL.CONSISTENCY	If the host or controller ever receive an unexpeced transaction acknowledge, it is an error.
FLASH_CTRL.FIFO.CTR.REDUN	The FIFO pointers of several FIFOs are implemented with duplicate counters.
FLASH_CTRL.MEM_TL_LC_GATE.FSM.SPARSE	The control FSM inside the TL-UL gating primitive is sparsely encoded.
FLASH_CTRL.PROG_TL_LC_GATE.FSM.SPARSE	The control FSM inside the TL-UL gating primitive is sparsely encoded.

Registers

Summary of the `core` interface’s registers

Name	Offset	Length	Description
flash_ctrl.`CIP_ID`	0x0	4	Comportable IP ID.
flash_ctrl.`REVISION`	0x4	4	Comportable IP semantic version.
flash_ctrl.`PARAMETER_BLOCK_TYPE`	0x8	4	Parameter block type.
flash_ctrl.`PARAMETER_BLOCK_LENGTH`	0xc	4	Parameter block length.
flash_ctrl.`NEXT_PARAMETER_BLOCK`	0x10	4	Next parameter block offset.
flash_ctrl.`INTR_STATE`	0x40	4	Interrupt State Register
flash_ctrl.`INTR_ENABLE`	0x44	4	Interrupt Enable Register
flash_ctrl.`INTR_TEST`	0x48	4	Interrupt Test Register
flash_ctrl.`ALERT_TEST`	0x4c	4	Alert Test Register
flash_ctrl.`DIS`	0x50	4	Disable flash functionality
flash_ctrl.`EXEC`	0x54	4	Controls whether flash can be used for code execution fetches
flash_ctrl.`INIT`	0x58	4	Controller init register
flash_ctrl.`CTRL_REGWEN`	0x5c	4	Controls the configurability of the !!CONTROL register.
flash_ctrl.`CONTROL`	0x60	4	Control register
flash_ctrl.`ADDR`	0x64	4	Address for flash operation
flash_ctrl.`PROG_TYPE_EN`	0x68	4	Enable different program types
flash_ctrl.`ERASE_SUSPEND`	0x6c	4	Suspend erase
flash_ctrl.`REGION_CFG_REGWEN_0`	0x70	4	Memory region registers configuration enable.
flash_ctrl.`REGION_CFG_REGWEN_1`	0x74	4	Memory region registers configuration enable.
flash_ctrl.`REGION_CFG_REGWEN_2`	0x78	4	Memory region registers configuration enable.
flash_ctrl.`REGION_CFG_REGWEN_3`	0x7c	4	Memory region registers configuration enable.
flash_ctrl.`REGION_CFG_REGWEN_4`	0x80	4	Memory region registers configuration enable.
flash_ctrl.`REGION_CFG_REGWEN_5`	0x84	4	Memory region registers configuration enable.
flash_ctrl.`REGION_CFG_REGWEN_6`	0x88	4	Memory region registers configuration enable.
flash_ctrl.`REGION_CFG_REGWEN_7`	0x8c	4	Memory region registers configuration enable.
flash_ctrl.`MP_REGION_CFG_0`	0x90	4	Memory property configuration for data partition
flash_ctrl.`MP_REGION_CFG_1`	0x94	4	Memory property configuration for data partition
flash_ctrl.`MP_REGION_CFG_2`	0x98	4	Memory property configuration for data partition
flash_ctrl.`MP_REGION_CFG_3`	0x9c	4	Memory property configuration for data partition
flash_ctrl.`MP_REGION_CFG_4`	0xa0	4	Memory property configuration for data partition
flash_ctrl.`MP_REGION_CFG_5`	0xa4	4	Memory property configuration for data partition
flash_ctrl.`MP_REGION_CFG_6`	0xa8	4	Memory property configuration for data partition
flash_ctrl.`MP_REGION_CFG_7`	0xac	4	Memory property configuration for data partition
flash_ctrl.`MP_REGION_0`	0xb0	4	Memory base and size configuration for data partition
flash_ctrl.`MP_REGION_1`	0xb4	4	Memory base and size configuration for data partition
flash_ctrl.`MP_REGION_2`	0xb8	4	Memory base and size configuration for data partition
flash_ctrl.`MP_REGION_3`	0xbc	4	Memory base and size configuration for data partition
flash_ctrl.`MP_REGION_4`	0xc0	4	Memory base and size configuration for data partition
flash_ctrl.`MP_REGION_5`	0xc4	4	Memory base and size configuration for data partition
flash_ctrl.`MP_REGION_6`	0xc8	4	Memory base and size configuration for data partition
flash_ctrl.`MP_REGION_7`	0xcc	4	Memory base and size configuration for data partition
flash_ctrl.`DEFAULT_REGION`	0xd0	4	Default region properties
flash_ctrl.`BANK0_INFO0_REGWEN_0`	0xd4	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_1`	0xd8	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_2`	0xdc	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_3`	0xe0	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_4`	0xe4	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_5`	0xe8	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_6`	0xec	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_7`	0xf0	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_8`	0xf4	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_REGWEN_9`	0xf8	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO0_PAGE_CFG_0`	0xfc	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_1`	0x100	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_2`	0x104	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_3`	0x108	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_4`	0x10c	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_5`	0x110	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_6`	0x114	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_7`	0x118	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_8`	0x11c	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO0_PAGE_CFG_9`	0x120	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO1_REGWEN`	0x124	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO1_PAGE_CFG`	0x128	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO2_REGWEN_0`	0x12c	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO2_REGWEN_1`	0x130	4	Memory region registers configuration enable.
flash_ctrl.`BANK0_INFO2_PAGE_CFG_0`	0x134	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK0_INFO2_PAGE_CFG_1`	0x138	4	Memory property configuration for info partition in bank0,
flash_ctrl.`BANK1_INFO0_REGWEN_0`	0x13c	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_1`	0x140	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_2`	0x144	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_3`	0x148	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_4`	0x14c	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_5`	0x150	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_6`	0x154	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_7`	0x158	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_8`	0x15c	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_REGWEN_9`	0x160	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO0_PAGE_CFG_0`	0x164	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_1`	0x168	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_2`	0x16c	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_3`	0x170	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_4`	0x174	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_5`	0x178	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_6`	0x17c	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_7`	0x180	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_8`	0x184	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO0_PAGE_CFG_9`	0x188	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO1_REGWEN`	0x18c	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO1_PAGE_CFG`	0x190	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO2_REGWEN_0`	0x194	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO2_REGWEN_1`	0x198	4	Memory region registers configuration enable.
flash_ctrl.`BANK1_INFO2_PAGE_CFG_0`	0x19c	4	Memory property configuration for info partition in bank1,
flash_ctrl.`BANK1_INFO2_PAGE_CFG_1`	0x1a0	4	Memory property configuration for info partition in bank1,
flash_ctrl.`HW_INFO_CFG_OVERRIDE`	0x1a4	4	HW interface info configuration rule overrides
flash_ctrl.`BANK_CFG_REGWEN`	0x1a8	4	Bank configuration registers configuration enable.
flash_ctrl.`MP_BANK_CFG_SHADOWED`	0x1ac	4	Memory properties bank configuration
flash_ctrl.`OP_STATUS`	0x1b0	4	Flash Operation Status
flash_ctrl.`STATUS`	0x1b4	4	Flash Controller Status
flash_ctrl.`DEBUG_STATE`	0x1b8	4	Current flash fsm state
flash_ctrl.`ERR_CODE`	0x1bc	4	Flash error code register.
flash_ctrl.`STD_FAULT_STATUS`	0x1c0	4	This register tabulates standard fault status of the flash.
flash_ctrl.`FAULT_STATUS`	0x1c4	4	This register tabulates customized fault status of the flash.
flash_ctrl.`ERR_ADDR`	0x1c8	4	Synchronous error address
flash_ctrl.`ECC_SINGLE_ERR_CNT`	0x1cc	4	Total number of single bit ECC error count
flash_ctrl.`ECC_SINGLE_ERR_ADDR_0`	0x1d0	4	Latest address of ECC single err
flash_ctrl.`ECC_SINGLE_ERR_ADDR_1`	0x1d4	4	Latest address of ECC single err
flash_ctrl.`PHY_ALERT_CFG`	0x1d8	4	Phy alert configuration
flash_ctrl.`PHY_STATUS`	0x1dc	4	Flash Phy Status
flash_ctrl.`Scratch`	0x1e0	4	Flash Controller Scratch
flash_ctrl.`FIFO_LVL`	0x1e4	4	Programmable depth where FIFOs should generate interrupts
flash_ctrl.`FIFO_RST`	0x1e8	4	Reset for flash controller FIFOs
flash_ctrl.`CURR_FIFO_LVL`	0x1ec	4	Current program and read fifo depth
flash_ctrl.`prog_fifo`	0x1f0	4	Flash program FIFO.
flash_ctrl.`rd_fifo`	0x1f4	4	Flash read FIFO.

CIP_ID

Comportable IP ID.

Offset: 0x0
Reset default: 0x8
Reset mask: 0xffffffff

Fields

Bits	Type	Reset	Name	Description
31:0	ro	0x8	CIP_ID	This value is a unique comportable IP identifier.

REVISION

Comportable IP semantic version.

Offset: 0x4
Reset default: 0x2000000
Reset mask: 0xffffffff

Fields

Bits	Type	Reset	Name	Description
31:24	ro	0x2	MAJOR	Major version number.
23:16	ro	0x0	MINOR	Minor version number.
15:8	ro	0x0	SUBMINOR	Subminor (patch) version number.
7:0	ro	0x0	RESERVED	Reserved version number.

PARAMETER_BLOCK_TYPE

Parameter block type.

Offset: 0x8
Reset default: 0x0
Reset mask: 0xffffffff

Fields

Bits	Type	Reset	Name	Description
31:0	ro	0x0	BLOCK_TYPE	Parameter block type.

PARAMETER_BLOCK_LENGTH

Parameter block length.

Offset: 0xc
Reset default: 0xc
Reset mask: 0xffffffff

Fields

Bits	Type	Reset	Name	Description
31:0	ro	0xc	BLOCK_LENGTH	Parameter block length in bytes.

NEXT_PARAMETER_BLOCK

Next parameter block offset.

Offset: 0x10
Reset default: 0x0
Reset mask: 0xffffffff

Fields

Bits	Type	Reset	Name	Description
31:0	ro	0x0	BLOCK_OFFSET	This offset value is zero if there is no other parameter block.

INTR_STATE

Interrupt State Register

Offset: 0x40
Reset default: 0x0
Reset mask: 0x3f

Fields

Bits	Type	Reset	Name	Description
31:6				Reserved
5	rw1c	0x0	corr_err	Correctable error encountered
4	rw1c	0x0	op_done	Operation complete
3	rw1c	0x0	rd_lvl	Read FIFO filled to level
2	rw1c	0x0	rd_full	Read FIFO full
1	rw1c	0x0	prog_lvl	Program FIFO drained to level
0	rw1c	0x0	prog_empty	Program FIFO empty

INTR_ENABLE

Interrupt Enable Register

Offset: 0x44
Reset default: 0x0
Reset mask: 0x3f

Fields

Bits	Type	Reset	Name	Description
31:6				Reserved
5	rw	0x0	corr_err	Enable interrupt when `INTR_STATE.corr_err` is set.
4	rw	0x0	op_done	Enable interrupt when `INTR_STATE.op_done` is set.
3	rw	0x0	rd_lvl	Enable interrupt when `INTR_STATE.rd_lvl` is set.
2	rw	0x0	rd_full	Enable interrupt when `INTR_STATE.rd_full` is set.
1	rw	0x0	prog_lvl	Enable interrupt when `INTR_STATE.prog_lvl` is set.
0	rw	0x0	prog_empty	Enable interrupt when `INTR_STATE.prog_empty` is set.

INTR_TEST

Interrupt Test Register

Offset: 0x48
Reset default: 0x0
Reset mask: 0x3f

Fields

Bits	Type	Reset	Name	Description
31:6				Reserved
5	wo	0x0	corr_err	Write 1 to force `INTR_STATE.corr_err` to 1.
4	wo	0x0	op_done	Write 1 to force `INTR_STATE.op_done` to 1.
3	wo	0x0	rd_lvl	Write 1 to force `INTR_STATE.rd_lvl` to 1.
2	wo	0x0	rd_full	Write 1 to force `INTR_STATE.rd_full` to 1.
1	wo	0x0	prog_lvl	Write 1 to force `INTR_STATE.prog_lvl` to 1.
0	wo	0x0	prog_empty	Write 1 to force `INTR_STATE.prog_empty` to 1.

ALERT_TEST

Alert Test Register

Offset: 0x4c
Reset default: 0x0
Reset mask: 0x1f

Fields

Bits	Type	Reset	Name	Description
31:5				Reserved
4	wo	0x0	recov_prim_flash_alert	Write 1 to trigger one alert event of this kind.
3	wo	0x0	fatal_prim_flash_alert	Write 1 to trigger one alert event of this kind.
2	wo	0x0	fatal_err	Write 1 to trigger one alert event of this kind.
1	wo	0x0	fatal_std_err	Write 1 to trigger one alert event of this kind.
0	wo	0x0	recov_err	Write 1 to trigger one alert event of this kind.

DIS

Disable flash functionality

Offset: 0x50
Reset default: 0x9
Reset mask: 0xf

Fields

Bits	Type	Reset	Name
31:4			Reserved
3:0	rw0c	0x9	VAL

DIS . VAL

Disables flash functionality completely. This is a shortcut mechanism used by the software to completely kill flash in case of emergency.

Since this register is rw0c instead of rw, to disable, write any value in the form of 0xxx or xxx0, where x could be either 0 or 1.

EXEC

Controls whether flash can be used for code execution fetches

Offset: 0x54
Reset default: 0x0
Reset mask: 0xffffffff

Fields

Bits	Type	Reset	Name	Description
31:0	rw	0x0	EN	A value of 0xa26a38f7 allows flash to be used for code execution. Any other value prevents code execution.

INIT

Controller init register

Offset: 0x58
Reset default: 0x0
Reset mask: 0x1

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw1s	0x0	VAL

INIT . VAL

Initializes the flash controller.

During the initialization process, the flash controller requests the address and data scramble keys and reads out the root seeds stored in flash before allowing other usage of the flash controller.

When the initialization sequence is complete, the flash read buffers are enabled and turned on.

CTRL_REGWEN

Controls the configurability of the CONTROL register.

This register ensures the contents of CONTROL cannot be changed by software once a flash operation has begun.

It unlocks whenever the existing flash operation completes, regardless of success or error.

Offset: 0x5c
Reset default: 0x1
Reset mask: 0x1

Fields

Bits	Type	Reset	Name	Description
31:1				Reserved
0	ro	0x1	EN	Configuration enable. This bit defaults to 1 and is set to 0 by hardware when flash operation is initiated. When the controller completes the flash operation, this bit is set back to 1 to allow software configuration of `CONTROL`

CONTROL

Control register

Offset: 0x60
Reset default: 0x0
Reset mask: 0xfff07f1
Register enable: CTRL_REGWEN

Fields

Bits	Type	Reset	Name
31:28			Reserved
27:16	rw	0x0	NUM
15:11			Reserved
10:9	rw	0x0	INFO_SEL
8	rw	0x0	PARTITION_SEL
7	rw	0x0	ERASE_SEL
6	rw	0x0	PROG_SEL
5:4	rw	0x0	OP
3:1			Reserved
0	rw	0x0	START

CONTROL . NUM

One fewer than the number of bus words the flash operation should read or program. For example, to read 10 words, software should program this field with the value 9.

CONTROL . INFO_SEL

Informational partions can have multiple types.

This field selects the info type to be accessed.

When doing a read, program or page erase operation, selects either info or data partition for operation. When 0, select data partition - this is the portion of flash that is accessible both by the host and by the controller. When 1, select info partition - this is the portion of flash that is only accessible by the controller.

When doing a bank erase operation, selects info partition also for erase. When 0, bank erase only erases data partition. When 1, bank erase erases data partition and info partition.

CONTROL . ERASE_SEL

Flash erase operation type selection

Value	Name	Description
0x0	Page Erase	Erase 1 page of flash
0x1	Bank Erase	Erase 1 bank of flash

CONTROL . PROG_SEL

Flash program operation type selection

Value	Name	Description
0x0	Normal program	Normal program operation to the flash
0x1	Program repair	Repair program operation to the flash. Whether this is actually supported depends on the underlying flash memory.

CONTROL . OP

Flash operation selection

Value	Name	Description
0x0	Read	Flash Read. Read desired number of flash words
0x1	Prog	Flash Program. Program desired number of flash words
0x2	Erase	Flash Erase Operation. See ERASE_SEL for details on erase operation

Other values are reserved.

CONTROL . START

Start flash transaction. This bit shall only be set at the same time or after the other fields of the CONTROL register and ADDR have been programmed.

ADDR

Address for flash operation

Offset: 0x64
Reset default: 0x0
Reset mask: 0xfffff
Register enable: CTRL_REGWEN

Fields

Bits	Type	Reset	Name
31:20			Reserved
19:0	rw	0x0	START

ADDR . START

Start address of a flash transaction. This is a byte address relative to the flash only. Ie, an address of 0 will access address 0 of the requested partition.

For read operations, the flash controller will truncate to the closest, lower word aligned address. For example, if 0x13 is supplied, the controller will perform a read at address 0x10.

Program operations behave similarly, the controller does not have read modified write support.

For page erases, the controller will truncate to the closest lower page aligned address. Similarly for bank erases, the controller will truncate to the closest lower bank aligned address.

PROG_TYPE_EN

Enable different program types

Offset: 0x68
Reset default: 0x3
Reset mask: 0x3
Register enable: CTRL_REGWEN

Fields

Bits	Type	Reset	Name	Description
31:2				Reserved
1	rw0c	0x1	REPAIR	Repair prog type available
0	rw0c	0x1	NORMAL	Normal prog type available

ERASE_SUSPEND

Suspend erase

Offset: 0x6c
Reset default: 0x0
Reset mask: 0x1

Fields

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw	0x0	REQ	When 1, request erase suspend. If no erase ongoing, the request is immediately cleared by hardware If erase ongoing, the request is fed to the flash_phy and cleared when the suspend is handled.

REGION_CFG_REGWEN

Memory region registers configuration enable.

Reset default: 0x1
Reset mask: 0x1

Instances

Name	Offset
REGION_CFG_REGWEN_0	0x70
REGION_CFG_REGWEN_1	0x74
REGION_CFG_REGWEN_2	0x78
REGION_CFG_REGWEN_3	0x7c
REGION_CFG_REGWEN_4	0x80
REGION_CFG_REGWEN_5	0x84
REGION_CFG_REGWEN_6	0x88
REGION_CFG_REGWEN_7	0x8c

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	REGION

REGION_CFG_REGWEN . REGION

Region register write enable. Once set to 0, it can longer be configured to 1

Value	Name	Description
0x0	Region locked	Region can no longer be configured until next reset
0x1	Region enabled	Region can be configured

MP_REGION_CFG

Memory property configuration for data partition

Reset default: 0x9999999
Reset mask: 0xfffffff

Instances

Name	Offset
MP_REGION_CFG_0	0x90
MP_REGION_CFG_1	0x94
MP_REGION_CFG_2	0x98
MP_REGION_CFG_3	0x9c
MP_REGION_CFG_4	0xa0
MP_REGION_CFG_5	0xa4
MP_REGION_CFG_6	0xa8
MP_REGION_CFG_7	0xac

Fields

Bits	Type	Reset	Name	Description
31:28				Reserved
27:24	rw	0x9	HE_EN	Region is high endurance enabled.
23:20	rw	0x9	ECC_EN	Region is integrity checked and reliability ECC enabled.
19:16	rw	0x9	SCRAMBLE_EN	Region is scramble enabled.
15:12	rw	0x9	ERASE_EN	Region can be erased
11:8	rw	0x9	PROG_EN	Region can be programmed
7:4	rw	0x9	RD_EN	Region can be read
3:0	rw	0x9	EN	Region enabled, following fields apply. If region is disabled, it is not matched against any incoming transaction.

MP_REGION

Memory base and size configuration for data partition

Reset default: 0x0
Reset mask: 0x7ffff

Instances

Name	Offset
MP_REGION_0	0xb0
MP_REGION_1	0xb4
MP_REGION_2	0xb8
MP_REGION_3	0xbc
MP_REGION_4	0xc0
MP_REGION_5	0xc4
MP_REGION_6	0xc8
MP_REGION_7	0xcc

Fields

Bits	Type	Reset	Name	Description
31:19				Reserved
18:9	rw	0x0	SIZE	Region size in number of pages. For example, if base is 0 and size is 1, then the region is defined by page 0. If base is 0 and size is 2, then the region is defined by pages 0 and 1.
8:0	rw	0x0	BASE	Region base page. Note the granularity is page, not byte or word

DEFAULT_REGION

Default region properties

Offset: 0xd0
Reset default: 0x999999
Reset mask: 0xffffff

Fields

Bits	Type	Reset	Name	Description
31:24				Reserved
23:20	rw	0x9	HE_EN	Region is high endurance enabled.
19:16	rw	0x9	ECC_EN	Region is ECC enabled (both integrity and reliability ECC).
15:12	rw	0x9	SCRAMBLE_EN	Region is scramble enabled.
11:8	rw	0x9	ERASE_EN	Region can be erased
7:4	rw	0x9	PROG_EN	Region can be programmed
3:0	rw	0x9	RD_EN	Region can be read

BANK0_INFO0_REGWEN

Memory region registers configuration enable.

Reset default: 0x1
Reset mask: 0x1

Instances

Name	Offset
BANK0_INFO0_REGWEN_0	0xd4
BANK0_INFO0_REGWEN_1	0xd8
BANK0_INFO0_REGWEN_2	0xdc
BANK0_INFO0_REGWEN_3	0xe0
BANK0_INFO0_REGWEN_4	0xe4
BANK0_INFO0_REGWEN_5	0xe8
BANK0_INFO0_REGWEN_6	0xec
BANK0_INFO0_REGWEN_7	0xf0
BANK0_INFO0_REGWEN_8	0xf4
BANK0_INFO0_REGWEN_9	0xf8

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	REGION

BANK0_INFO0_REGWEN . REGION

Info0 page write enable. Once set to 0, it can longer be configured to 1

Value	Name	Description
0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

BANK0_INFO0_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default: 0x9999999
Reset mask: 0xfffffff

Instances

Name	Offset
BANK0_INFO0_PAGE_CFG_0	0xfc
BANK0_INFO0_PAGE_CFG_1	0x100
BANK0_INFO0_PAGE_CFG_2	0x104
BANK0_INFO0_PAGE_CFG_3	0x108
BANK0_INFO0_PAGE_CFG_4	0x10c
BANK0_INFO0_PAGE_CFG_5	0x110
BANK0_INFO0_PAGE_CFG_6	0x114
BANK0_INFO0_PAGE_CFG_7	0x118
BANK0_INFO0_PAGE_CFG_8	0x11c
BANK0_INFO0_PAGE_CFG_9	0x120

Fields

Bits	Type	Reset	Name	Description
31:28				Reserved
27:24	rw	0x9	HE_EN	Region is high endurance enabled.
23:20	rw	0x9	ECC_EN	Region is ECC enabled (both integrity and reliability ECC).
19:16	rw	0x9	SCRAMBLE_EN	Region is scramble enabled.
15:12	rw	0x9	ERASE_EN	Region can be erased
11:8	rw	0x9	PROG_EN	Region can be programmed
7:4	rw	0x9	RD_EN	Region can be read
3:0	rw	0x9	EN	Region enabled, following fields apply

BANK0_INFO1_REGWEN

Memory region registers configuration enable.

Reset default: 0x1
Reset mask: 0x1

Instances

Name	Offset
BANK0_INFO1_REGWEN	0x124

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	REGION

BANK0_INFO1_REGWEN . REGION

Info1 page write enable. Once set to 0, it can longer be configured to 1

Value	Name	Description
0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

BANK0_INFO1_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default: 0x9999999
Reset mask: 0xfffffff

Instances

Name	Offset
BANK0_INFO1_PAGE_CFG	0x128

Fields

Bits	Type	Reset	Name	Description
31:28				Reserved
27:24	rw	0x9	HE_EN	Region is high endurance enabled.
23:20	rw	0x9	ECC_EN	Region is ECC enabled (both integrity and reliability ECC).
19:16	rw	0x9	SCRAMBLE_EN	Region is scramble enabled.
15:12	rw	0x9	ERASE_EN	Region can be erased
11:8	rw	0x9	PROG_EN	Region can be programmed
7:4	rw	0x9	RD_EN	Region can be read
3:0	rw	0x9	EN	Region enabled, following fields apply

BANK0_INFO2_REGWEN

Memory region registers configuration enable.

Reset default: 0x1
Reset mask: 0x1

Instances

Name	Offset
BANK0_INFO2_REGWEN_0	0x12c
BANK0_INFO2_REGWEN_1	0x130

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	REGION

BANK0_INFO2_REGWEN . REGION

Info2 page write enable. Once set to 0, it can longer be configured to 1

Value	Name	Description
0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

BANK0_INFO2_PAGE_CFG

Memory property configuration for info partition in bank0, Unlike data partition, each page is individually configured.

Reset default: 0x9999999
Reset mask: 0xfffffff

Instances

Name	Offset
BANK0_INFO2_PAGE_CFG_0	0x134
BANK0_INFO2_PAGE_CFG_1	0x138

Fields

Bits	Type	Reset	Name	Description
31:28				Reserved
27:24	rw	0x9	HE_EN	Region is high endurance enabled.
23:20	rw	0x9	ECC_EN	Region is ECC enabled (both integrity and reliability ECC).
19:16	rw	0x9	SCRAMBLE_EN	Region is scramble enabled.
15:12	rw	0x9	ERASE_EN	Region can be erased
11:8	rw	0x9	PROG_EN	Region can be programmed
7:4	rw	0x9	RD_EN	Region can be read
3:0	rw	0x9	EN	Region enabled, following fields apply

BANK1_INFO0_REGWEN

Memory region registers configuration enable.

Reset default: 0x1
Reset mask: 0x1

Instances

Name	Offset
BANK1_INFO0_REGWEN_0	0x13c
BANK1_INFO0_REGWEN_1	0x140
BANK1_INFO0_REGWEN_2	0x144
BANK1_INFO0_REGWEN_3	0x148
BANK1_INFO0_REGWEN_4	0x14c
BANK1_INFO0_REGWEN_5	0x150
BANK1_INFO0_REGWEN_6	0x154
BANK1_INFO0_REGWEN_7	0x158
BANK1_INFO0_REGWEN_8	0x15c
BANK1_INFO0_REGWEN_9	0x160

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	REGION

BANK1_INFO0_REGWEN . REGION

Info0 page write enable. Once set to 0, it can longer be configured to 1

Value	Name	Description
0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

BANK1_INFO0_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default: 0x9999999
Reset mask: 0xfffffff

Instances

Name	Offset
BANK1_INFO0_PAGE_CFG_0	0x164
BANK1_INFO0_PAGE_CFG_1	0x168
BANK1_INFO0_PAGE_CFG_2	0x16c
BANK1_INFO0_PAGE_CFG_3	0x170
BANK1_INFO0_PAGE_CFG_4	0x174
BANK1_INFO0_PAGE_CFG_5	0x178
BANK1_INFO0_PAGE_CFG_6	0x17c
BANK1_INFO0_PAGE_CFG_7	0x180
BANK1_INFO0_PAGE_CFG_8	0x184
BANK1_INFO0_PAGE_CFG_9	0x188

Fields

Bits	Type	Reset	Name	Description
31:28				Reserved
27:24	rw	0x9	HE_EN	Region is high endurance enabled.
23:20	rw	0x9	ECC_EN	Region is ECC enabled (both integrity and reliability ECC).
19:16	rw	0x9	SCRAMBLE_EN	Region is scramble enabled.
15:12	rw	0x9	ERASE_EN	Region can be erased
11:8	rw	0x9	PROG_EN	Region can be programmed
7:4	rw	0x9	RD_EN	Region can be read
3:0	rw	0x9	EN	Region enabled, following fields apply

BANK1_INFO1_REGWEN

Memory region registers configuration enable.

Reset default: 0x1
Reset mask: 0x1

Instances

Name	Offset
BANK1_INFO1_REGWEN	0x18c

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	REGION

BANK1_INFO1_REGWEN . REGION

Info1 page write enable. Once set to 0, it can longer be configured to 1

Value	Name	Description
0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

BANK1_INFO1_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default: 0x9999999
Reset mask: 0xfffffff

Instances

Name	Offset
BANK1_INFO1_PAGE_CFG	0x190

Fields

Bits	Type	Reset	Name	Description
31:28				Reserved
27:24	rw	0x9	HE_EN	Region is high endurance enabled.
23:20	rw	0x9	ECC_EN	Region is ECC enabled (both integrity and reliability ECC).
19:16	rw	0x9	SCRAMBLE_EN	Region is scramble enabled.
15:12	rw	0x9	ERASE_EN	Region can be erased
11:8	rw	0x9	PROG_EN	Region can be programmed
7:4	rw	0x9	RD_EN	Region can be read
3:0	rw	0x9	EN	Region enabled, following fields apply

BANK1_INFO2_REGWEN

Memory region registers configuration enable.

Reset default: 0x1
Reset mask: 0x1

Instances

Name	Offset
BANK1_INFO2_REGWEN_0	0x194
BANK1_INFO2_REGWEN_1	0x198

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	REGION

BANK1_INFO2_REGWEN . REGION

Info2 page write enable. Once set to 0, it can longer be configured to 1

Value	Name	Description
0x0	Page locked	Region can no longer be configured until next reset
0x1	Page enabled	Region can be configured

BANK1_INFO2_PAGE_CFG

Memory property configuration for info partition in bank1, Unlike data partition, each page is individually configured.

Reset default: 0x9999999
Reset mask: 0xfffffff

Instances

Name	Offset
BANK1_INFO2_PAGE_CFG_0	0x19c
BANK1_INFO2_PAGE_CFG_1	0x1a0

Fields

Bits	Type	Reset	Name	Description
31:28				Reserved
27:24	rw	0x9	HE_EN	Region is high endurance enabled.
23:20	rw	0x9	ECC_EN	Region is ECC enabled (both integrity and reliability ECC).
19:16	rw	0x9	SCRAMBLE_EN	Region is scramble enabled.
15:12	rw	0x9	ERASE_EN	Region can be erased
11:8	rw	0x9	PROG_EN	Region can be programmed
7:4	rw	0x9	RD_EN	Region can be read
3:0	rw	0x9	EN	Region enabled, following fields apply

HW_INFO_CFG_OVERRIDE

HW interface info configuration rule overrides

Offset: 0x1a4
Reset default: 0x99
Reset mask: 0xff

Fields

Bits	Type	Reset	Name	Description
31:8				Reserved
7:4	rw	0x9	ECC_DIS	The hardwired hardware info configuration rules for ECC enable are logically AND’d with this field. If the hardware rules hardwires ECC to enable, we can disable via software if needed. By default this field is false.
3:0	rw	0x9	SCRAMBLE_DIS	The hardwired hardware info configuration rules for scramble enable are logically AND’d with this field. If the hardware rules hardwires scramble to enable, we can disable via software if needed. By default this field is false.

BANK_CFG_REGWEN

Bank configuration registers configuration enable.

Offset: 0x1a8
Reset default: 0x1
Reset mask: 0x1

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	BANK

BANK_CFG_REGWEN . BANK

Bank register write enable. Once set to 0, it can longer be configured to 1

Value	Name	Description
0x0	Bank locked	Bank can no longer be configured until next reset
0x1	Bank enabled	Bank can be configured

MP_BANK_CFG_SHADOWED

Memory properties bank configuration

Offset: 0x1ac
Reset default: 0x0
Reset mask: 0x3
Register enable: BANK_CFG_REGWEN

Fields

Bits	Type	Reset	Name	Description
31:2				Reserved
1	rw	0x0	ERASE_EN_1	Bank wide erase enable
0	rw	0x0	ERASE_EN_0	Bank wide erase enable

OP_STATUS

Flash Operation Status

Offset: 0x1b0
Reset default: 0x0
Reset mask: 0x3

Fields

Bits	Type	Reset	Name	Description
31:2				Reserved
1	rw	0x0	err	Flash operation error. Set by HW, cleared by SW. See `ERR_CODE` for more details.
0	rw	0x0	done	Flash operation done. Set by HW, cleared by SW

STATUS

Flash Controller Status

Offset: 0x1b4
Reset default: 0xa
Reset mask: 0x3f

Fields

Bits	Type	Reset	Name	Description
31:6				Reserved
5	ro	0x0	initialized	Flash controller initialized
4	ro	0x0	init_wip	Flash controller undergoing init, inclusive of phy init
3	ro	0x1	prog_empty	Flash program FIFO empty, software must provide data
2	ro	0x0	prog_full	Flash program FIFO full
1	ro	0x1	rd_empty	Flash read FIFO empty
0	ro	0x0	rd_full	Flash read FIFO full, software must consume data

DEBUG_STATE

Current flash fsm state

Offset: 0x1b8
Reset default: 0x0
Reset mask: 0x7ff

Fields

Bits	Type	Reset	Name	Description
31:11				Reserved
10:0	ro	x	lcmgr_state	Current lcmgr interface staet

ERR_CODE

Flash error code register. This register tabulates detailed error status of the flash. This is separate from OP_STATUS, which is used to indicate the current state of the software initiated flash operation.

Note, all errors in this register are considered recoverable errors, ie, errors that could have been generated by software.

Offset: 0x1bc
Reset default: 0x0
Reset mask: 0xff

Fields

Bits	Type	Reset	Name	Description
31:8				Reserved
7	rw1c	0x0	macro_err	A recoverable error has been encountered in the flash macro. Please read the flash macro status registers for more details.
6	rw1c	0x0	update_err	A shadow register encountered an update error. This is an asynchronous error.
5	rw1c	0x0	prog_type_err	Flash program selected unavailable type, see `PROG_TYPE_EN.` This is a synchronous error.
4	rw1c	0x0	prog_win_err	Flash program has a window resolution error. Ie, the start of program and end of program are in different windows. Please check `ERR_ADDR.` This is a synchronous error.
3	rw1c	0x0	prog_err	Flash program has an error. This could be a program integrity error, see `STD_FAULT_STATUS.` This is a synchronous error.
2	rw1c	0x0	rd_err	Flash read has an error. This could be a reliability ECC error or an storage integrity error encountered during a software issued controller read, see `STD_FAULT_STATUS.` See `ERR_ADDR` for exact address. This is a synchronous error.
1	rw1c	0x0	mp_err	Flash access has encountered an access permission error. Please see `ERR_ADDR` for exact address. This is a synchronous error.
0	rw1c	0x0	op_err	Software has supplied an undefined operation. See `CONTROL.OP` for list of valid operations.

STD_FAULT_STATUS

This register tabulates standard fault status of the flash.

These represent errors that occur in the standard structures of the design. For example fsm integrity, counter integrity and tlul integrity.

Offset: 0x1c0
Reset default: 0x0
Reset mask: 0x1ff

Fields

Bits	Type	Reset	Name	Description
31:9				Reserved
8	ro	0x0	fifo_err	Flash primitive fifo’s have encountered a count error.
7	ro	0x0	ctrl_cnt_err	Flash ctrl read/prog has encountered a count error.
6	ro	0x0	phy_fsm_err	A flash phy fsm has encountered a sparse encoding error.
5	ro	0x0	storage_err	A shadow register encountered a storage error.
4	ro	0x0	arb_fsm_err	The arbiter fsm has encountered a sparse encoding error.
3	ro	0x0	lcmgr_intg_err	The life cycle management interface has encountered a transmission integrity error. This is an integrity error on the generated integrity during a life cycle management interface read.
2	ro	0x0	lcmgr_err	The life cycle management interface has encountered a fatal error. The error is either an FSM sparse encoding error or a count error.
1	ro	0x0	prog_intg_err	The flash controller encountered a program data transmission integrity error.
0	ro	0x0	reg_intg_err	The flash controller encountered a register integrity error.

FAULT_STATUS

This register tabulates customized fault status of the flash.

These are errors that are impossible to have been caused by software or unrecoverable in nature.

Offset: 0x1c4
Reset default: 0x0
Reset mask: 0xfff

Fields

Bits	Type	Reset	Name	Description
31:12				Reserved
11	ro	0x0	host_gnt_err	A host transaction was granted with illegal properties.
10	ro	0x0	arb_err	The phy arbiter encountered inconsistent results.
9	ro	0x0	spurious_ack	The flash emitted an unexpected acknowledgement.
8	ro	0x0	phy_storage_err	The flash macro encountered a storage integrity ECC error.
7	ro	0x0	phy_relbl_err	The flash macro encountered a storage reliability ECC error.
6	ro	0x0	seed_err	The seed reading process encountered an unexpected error.
5	ro	0x0	prog_type_err	The flash life cycle management interface encountered a program type error. A program type not supported by the flash macro was issued.
4	ro	0x0	prog_win_err	The flash life cycle management interface encountered a program resolution error.
3	ro	0x0	prog_err	The flash life cycle management interface encountered a program error. This could be a program integirty eror, see `STD_FAULT_STATUS` for more details.
2	ro	0x0	rd_err	The flash life cycle management interface encountered a read error. This could be a reliability ECC error or an integrity ECC error encountered during a read, see `STD_FAULT_STATUS` for more details.
1	ro	0x0	mp_err	The flash life cycle management interface encountered a memory permission error.
0	ro	0x0	op_err	The flash life cycle management interface has supplied an undefined operation. See `CONTROL.OP` for list of valid operations.

ERR_ADDR

Synchronous error address

Offset: 0x1c8
Reset default: 0x0
Reset mask: 0xfffff

Fields

Bits	Type	Reset	Name	Description
31:20				Reserved
19:0	ro	0x0	ERR_ADDR

ECC_SINGLE_ERR_CNT

Total number of single bit ECC error count

Offset: 0x1cc
Reset default: 0x0
Reset mask: 0xffff

Fields

Bits	Type	Reset	Name	Description
31:16				Reserved
15:8	rw	0x0	ECC_SINGLE_ERR_CNT_1	This count will not wrap when saturated
7:0	rw	0x0	ECC_SINGLE_ERR_CNT_0	This count will not wrap when saturated

ECC_SINGLE_ERR_ADDR

Latest address of ECC single err

Reset default: 0x0
Reset mask: 0xfffff

Instances

Name	Offset
ECC_SINGLE_ERR_ADDR_0	0x1d0
ECC_SINGLE_ERR_ADDR_1	0x1d4

Fields

Bits	Type	Reset	Name	Description
31:20				Reserved
19:0	ro	0x0	ECC_SINGLE_ERR_ADDR	Latest single error address for this bank

PHY_ALERT_CFG

Phy alert configuration

Offset: 0x1d8
Reset default: 0x0
Reset mask: 0x3

Fields

Bits	Type	Reset	Name	Description
31:2				Reserved
1	rw	0x0	alert_trig	Trigger flash phy alert
0	rw	0x0	alert_ack	Acknowledge flash phy alert

PHY_STATUS

Flash Phy Status

Offset: 0x1dc
Reset default: 0x6
Reset mask: 0x7

Fields

Bits	Type	Reset	Name	Description
31:3				Reserved
2	ro	0x1	prog_repair_avail	Program repair supported
1	ro	0x1	prog_normal_avail	Normal program supported
0	ro	0x0	init_wip	Flash phy controller initializing

Scratch

Flash Controller Scratch

Offset: 0x1e0
Reset default: 0x0
Reset mask: 0xffffffff

Fields

Bits	Type	Reset	Name	Description
31:0	rw	0x0	data	Flash ctrl scratch register

FIFO_LVL

Programmable depth where FIFOs should generate interrupts

Offset: 0x1e4
Reset default: 0xf0f
Reset mask: 0x1f1f

Fields

Bits	Type	Reset	Name	Description
31:13				Reserved
12:8	rw	0xf	RD	When the read FIFO fills to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.
7:5				Reserved
4:0	rw	0xf	PROG	When the program FIFO drains to this level, trigger an interrupt. Default value is set such that interrupt does not trigger at reset.

FIFO_RST

Reset for flash controller FIFOs

Offset: 0x1e8
Reset default: 0x0
Reset mask: 0x1

Fields

Bits	Type	Reset	Name	Description
31:1				Reserved
0	rw	0x0	EN	Active high resets for both program and read FIFOs. This is especially useful after the controller encounters an error of some kind. This bit will hold the FIFO in reset as long as it is set.

CURR_FIFO_LVL

Current program and read fifo depth

Offset: 0x1ec
Reset default: 0x0
Reset mask: 0x1f1f

Fields

Bits	Type	Reset	Name	Description
31:13				Reserved
12:8	ro	0x0	RD	Current read fifo depth
7:5				Reserved
4:0	ro	0x0	PROG	Current program fifo depth

prog_fifo

Flash program FIFO.

The FIFO is 16 entries of 4B flash words. This FIFO can only be programmed by software after a program operation has been initiated via the !!CONTROL register. This ensures accidental programming of the program FIFO cannot lock up the system.

Word Aligned Offset Range: 0x1f0to0x1f0
Size (words): 1
Access: wo
Byte writes are not supported.

rd_fifo

Flash read FIFO.

The FIFO is 16 entries of 4B flash words

Word Aligned Offset Range: 0x1f4to0x1f4
Size (words): 1
Access: ro
Byte writes are not supported.

Summary of the `prim` interface’s registers

Name	Offset	Length
flash_ctrl.`CSR0_REGWEN`	0x0	4
flash_ctrl.`CSR1`	0x4	4
flash_ctrl.`CSR2`	0x8	4
flash_ctrl.`CSR3`	0xc	4
flash_ctrl.`CSR4`	0x10	4
flash_ctrl.`CSR5`	0x14	4
flash_ctrl.`CSR6`	0x18	4
flash_ctrl.`CSR7`	0x1c	4
flash_ctrl.`CSR8`	0x20	4
flash_ctrl.`CSR9`	0x24	4
flash_ctrl.`CSR10`	0x28	4
flash_ctrl.`CSR11`	0x2c	4
flash_ctrl.`CSR12`	0x30	4
flash_ctrl.`CSR13`	0x34	4
flash_ctrl.`CSR14`	0x38	4
flash_ctrl.`CSR15`	0x3c	4
flash_ctrl.`CSR16`	0x40	4
flash_ctrl.`CSR17`	0x44	4
flash_ctrl.`CSR18`	0x48	4
flash_ctrl.`CSR19`	0x4c	4
flash_ctrl.`CSR20`	0x50	4

CSR0_REGWEN

Offset: 0x0
Reset default: 0x1
Reset mask: 0x1

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw0c	0x1	field0

CSR0_REGWEN . field0

All values are reserved.

CSR1

Offset: 0x4
Reset default: 0x0
Reset mask: 0x1fff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:13			Reserved
12:8	rw	0x0	field1
7:0	rw	0x0	field0

Offset: 0x8
Reset default: 0x0
Reset mask: 0xff

Fields

Bits	Type	Reset	Name
31:8			Reserved
7	rw	0x0	field7
6	rw1c	0x0	field6
5	rw1c	0x0	field5
4	rw1c	0x0	field4
3	rw	0x0	field3
2	rw1c	0x0	field2
1	rw1c	0x0	field1
0	rw1c	0x0	field0

Offset: 0xc
Reset default: 0x0
Reset mask: 0xfffffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:28			Reserved
27:26	rw	0x0	field9
25:24	rw	0x0	field8
23:21	rw	0x0	field7
20	rw	0x0	field6
19:17	rw	0x0	field5
16:14	rw	0x0	field4
13:11	rw	0x0	field3
10:8	rw	0x0	field2
7:4	rw	0x0	field1
3:0	rw	0x0	field0

Offset: 0x10
Reset default: 0x0
Reset mask: 0xfff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:12			Reserved
11:9	rw	0x0	field3
8:6	rw	0x0	field2
5:3	rw	0x0	field1
2:0	rw	0x0	field0

Offset: 0x14
Reset default: 0x0
Reset mask: 0x7fffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:23			Reserved
22:19	rw	0x0	field4
18:14	rw	0x0	field3
13:5	rw	0x0	field2
4:3	rw	0x0	field1
2:0	rw	0x0	field0

Offset: 0x18
Reset default: 0x0
Reset mask: 0x1ffffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:25			Reserved
24	rw	0x0	field8
23	rw	0x0	field7
22:21	rw	0x0	field6
20:19	rw	0x0	field5
18:17	rw	0x0	field4
16:14	rw	0x0	field3
13:6	rw	0x0	field2
5:3	rw	0x0	field1
2:0	rw	0x0	field0

Offset: 0x1c
Reset default: 0x0
Reset mask: 0x1ffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:17			Reserved
16:8	rw	0x0	field1
7:0	rw	0x0	field0

Offset: 0x20
Reset default: 0x0
Reset mask: 0xffffffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:0	rw	0x0	field0

CSR8 . field0

All values are reserved.

CSR9

Offset: 0x24
Reset default: 0x0
Reset mask: 0xffffffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:0	rw	0x0	field0

CSR9 . field0

All values are reserved.

CSR10

Offset: 0x28
Reset default: 0x0
Reset mask: 0xffffffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:0	rw	0x0	field0

CSR10 . field0

All values are reserved.

CSR11

Offset: 0x2c
Reset default: 0x0
Reset mask: 0xffffffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:0	rw	0x0	field0

CSR11 . field0

All values are reserved.

CSR12

Offset: 0x30
Reset default: 0x0
Reset mask: 0x3ff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:10			Reserved
9:0	rw	0x0	field0

CSR12 . field0

All values are reserved.

CSR13

Offset: 0x34
Reset default: 0x0
Reset mask: 0x1fffff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:21			Reserved
20	rw	0x0	field1
19:0	rw	0x0	field0

Offset: 0x38
Reset default: 0x0
Reset mask: 0x1ff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:9			Reserved
8	rw	0x0	field1
7:0	rw	0x0	field0

Offset: 0x3c
Reset default: 0x0
Reset mask: 0x1ff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:9			Reserved
8	rw	0x0	field1
7:0	rw	0x0	field0

Offset: 0x40
Reset default: 0x0
Reset mask: 0x1ff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:9			Reserved
8	rw	0x0	field1
7:0	rw	0x0	field0

Offset: 0x44
Reset default: 0x0
Reset mask: 0x1ff
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:9			Reserved
8	rw	0x0	field1
7:0	rw	0x0	field0

Offset: 0x48
Reset default: 0x0
Reset mask: 0x1
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw	0x0	field0

CSR18 . field0

All values are reserved.

CSR19

Offset: 0x4c
Reset default: 0x0
Reset mask: 0x1
Register enable: CSR0_REGWEN

Fields

Bits	Type	Reset	Name
31:1			Reserved
0	rw	0x0	field0

CSR19 . field0

All values are reserved.

CSR20

Offset: 0x50
Reset default: 0x0
Reset mask: 0x7

Fields

Bits	Type	Reset	Name
31:3			Reserved
2	ro	0x0	field2
1	rw1c	0x0	field1
0	rw1c	0x0	field0