Asserted when entropy source bits are available.

Asserted when the alert count has been met.

Asserted when the observe FIFO has filled to the threshold level.

Asserted when a FIFO error occurs, or if an illegal state machine state is reached.

Enable interrupt when INTR_STATE.es_entropy_valid is set.

Enable interrupt when INTR_STATE.es_health_test_failed is set.

Enable interrupt when INTR_STATE.es_observe_fifo_ready is set.

Enable interrupt when INTR_STATE.es_fatal_err is set.

Write 1 to force INTR_STATE.es_entropy_valid to 1.

Write 1 to force INTR_STATE.es_health_test_failed to 1.

Write 1 to force INTR_STATE.es_observe_fifo_ready to 1.

Write 1 to force INTR_STATE.es_fatal_err to 1.

Write 1 to trigger one alert event of this kind.

Write 1 to trigger one alert event of this kind.

When true, the MODULE_ENABLE register can be modified. When false, it becomes read-only.

When this bit true and the MODULE_ENABLE field is false, the REGWEN write enable bit read as true, and is distributed to all associated control and threshold registers. When false, these registers become read-only.

This read-only write enable bit will allow write access to control and theshold registers that are associated with this bit, but only when the MODULE_ENABLE field is set to kMultiBitBool4False and the SW_REGUPD write enable bit is set to true. When read as false, these registers become read-only.

Read of this register shows the ABI of this block.

Read of this register shows the revision of this block.

Read of this register shows the type of chip using this block.

Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting this field to kMultiBitBool4False will effectively reset the module. The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details.

Setting this field to kMultiBitBool4True will enable FIPS qualified entropy to be generated.

Setting this field to kMultiBitBool4True will enable reading entropy values from the ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read input vector is set to the enable encoding.

This field controls the scope (either by-line or by-sum) of the health checks. If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all RNG input lines into a single score, and thresholds will be applied to the sum all the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored individually. A statistical deviation in any one input line, be it due to coincidence or failure, will force rejection of the sample, and count toward the total alert count.

Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only one bit is sampled.

When the above bit iset, this field selects which bit from the RNG bus will be processed when in single RNG bit mode. This two bit field selects the RNG bit stream: 0b00: RNG bit 0 0b01: RNG bit 1 0b10: RNG bit 2 0b11: RNG bit 3

Setting this field to kMultiBitBool4True routes the generated entropy value to the ENTROPY_DATA register to be read by firmware. When this field is kMultiBitBool4False, the generated entropy will be forwarded out of this module to the hardware interface.

Setting this field to kMultiBitBool4True will bypass the conditioning logic and bring raw entropy data to the ENTROPY_DATA register. When kMultiBitBool4False, FIPS compliant entropy will be brought the ENTROPY_DATA register, after being conditioned.

A read of this register provides generated entropy bits to firmware.

This is the window size for all health tests. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is (2048 bits * 1 clock/4 bits);

This is the window size for all health tests when running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is (384 bits * 1 clock/4 bits);

Note that currently only a window size of 384 is supported and tested (this corresponds to the register default value 0x60). Do not use any other values, unless you know what you are doing.

This is the threshold size for the repetition count health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the repetition count health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the repetition count symbol health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the repetition count symbol health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the adaptive proportion health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the adaptive proportion health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the bucket health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the bucket health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the Markov health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the Markov health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the external health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the external health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

High watermark value of the REPCNT test in FIPS mode.

High watermark value of the REPCNT test in bypass mode.

High watermark value of the REPCNTS test in FIPS mode.

High watermark value of the REPCNTS test in bypass mode.

High watermark value of the adaptive proportion test in FIPS mode.

High watermark value of the adaptive proportion test in bypass mode.

Low watermark value of the adaptive proportion test in FIPS mode.

Low watermark value of the adaptive proportion test in bypass mode.

High watermark value of the external health test in FIPS mode.

High watermark value of the external health test in bypass mode.

Low watermark value of the external health test in FIPS mode.

Low watermark value of the external health test in bypass mode.

High watermark value of the bucket test in FIPS mode.

High watermark value of the bucket test in bypass mode.

High watermark value of the Markov test in FIPS mode.

High watermark value of the Markov test in bypass mode.

Low watermark value of the Markov test in FIPS mode.

Low watermark value of the Markov test in bypass mode.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This register will hold a running count of test failures observed during normal operation. It will persist until cleared.

This is the threshold size that will signal an alert when value is reached. A value of zero will disable alerts. The default value is 2.

This should be set to the value above, but inverted.

This field will hold a running count of the total alert count, which is a sum of all of the other counters in the ALERT_FAIL_COUNTS register. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared.

Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. In this mode, firmware can monitor the post-health test entropy by reading the observe FIFO. This function also requires that the otp_en_entropy_src_fw_over input vector is set to the enable encoding.

Setting this field to kMultiBitBool4True will switch the input into the pre-conditioner packer FIFO. Firmware can directly write into the packer FIFO, enabling the ability to insert entropy bits back into the hardware flow. Firmware can read data from the health check packer FIFO, then do optional health checks or optional conditioning, then insert the results back into the flow. Also, the FW_OV_CONTROL.FW_OV_MODE bit must be set.

Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine to start the SHA3 process and be ready to accept entropy data. This field should be set prior to writting the FW_OV_WR_DATA register. Once all data has been written, this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish processing and push the result into the ESFINAL FIFO.

Note that clearing this bit to kMultiBitBool4False while there is still unprocessed entropy in the FW_OV_WR_DATA will start the SHA3 engine before data can be added to the input message, and will also signal a recoverable alert in RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False.

"When this bit is clear, writes to the FW_OV_WR_DATA register are allowed. If this bit is set, it is the equivalent to a FIFO full condition, and writes to the FW_OV_WR_DATA register must be delayed until this bit is reset.

This bit is set by hardware whenever RNG data is lost due to an overflow condition in the Observe FIFO. The RNG data rate is slow enough that firmware should always be able to keep up. This register meanwhile provides an additional check to confirm that bytes read from the FW_OV_RD_DATA register represent contiguous RNG samples. If an overflow event occurs, this bit must be cleared by software.

A read of this register pops and returns the top of the Observe FIFO.

A write to this register will insert entropy back into the entropy source module flow. Both FW_OV_CONTROL.FW_OV_MODE and FW_OV_CONTROL.FW_OV_ENTROPY_INSERT bits need to be set to enable the insertion.

This field will set the threshold that the depth of the Observe FIFO will be compared with when setting the interrupt status bit. Note: a value of zero is reserved and not to be used.

This field will hold the current depth of the Observe FIFO.

This is the depth of the entropy source FIFO.

This is the SHA3 finite state machine current state.

This is the SHA3 block processed signal current state.

This is the SHA3 squeezing signal current state.

This is the SHA3 absorbed signal current state.

This is a logic-or of all of the SHA3 error signals.

The entropy_src main state machine is in the idle state.

The entropy_src main state machine is in the boot phase done state.

This bit is set when the FIPS_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the ENTROPY_DATA_REG_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the MODULE_ENABLE field in the MODULE_ENABLE register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the THRESHOLD_SCOPE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the RNG_BIT_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the FW_OV_SHA3_START field in the FW_OV_SHA3_START register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the FW_OV_MODE field in the FW_OV_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the FW_OV_ENTROPY_INSERT field in the FW_OV_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the ES_ROUTE field in the ENTROPY_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the ES_TYPE field in the ENTROPY_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

This bit is set when the main state machine detects a threshhold failure state. Writing a zero resets this status bit.

This bit is set when the interal entropy bus value is equal to the prior valid value on the bus, indicating a possible attack. Writing a zero resets this status bit.

This bit is set when the ALERT_THRESHOLD register is not configured properly. The upper field must be the exact inverse of the lower field. Writing a zero resets this status bit.

This bit is set when the packer FIFO has been written but was full at the time, and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes. This alert would normally be the result of not monitoring the FW_OV_WR_FIFO_FULL register before each write to the FW_OV_WR_DATA register. Writing a zero resets this status bit.

This bit is set when FW_OV_SHA3_START has been set to MuBi4 False, without waiting for the FW_OV packer FIFO to clear. The final entropy entry in the FIFO will not be included in the SHA3 digest. (Rather it will be added to the subsequent SHA3 digest.) To avoid this alert, monitor FW_OV_WR_FIFO_FULL before clearing FW_OV_SHA3_START. This alert only applies when both FW_OV_MODE and FW_OV_ENTROPY_INSERT are set to MuBi4True. Writing a zero resets this status bit.

This bit will be set to one when an error has been detected for the esrng FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

This bit will be set to one when an error has been detected for the observe FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

This bit will be set to one when an error has been detected for the esfinal FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

This bit will be set to one when an illegal state has been detected for the ES ack stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

This bit will be set to one when an illegal state has been detected for the ES main stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

This bit will be set to one when a hardened counter has detected an error condition. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

This bit will be set to one when a SHA3 state error has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being active has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any full FIFO that has been recieved a write pulse. This bit will stay set until the next reset.

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any empty FIFO that has recieved a read pulse. This bit will stay set until the next reset.

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any FIFO where both the empty and full status bits are set. This bit will stay set until the next reset.

Setting this field will set the bit number for which an error will be forced in the hardware. This bit number is that same one found in the ERR_CODE register. The action of writing this register will force an error pulse. The sole purpose of this register is to test that any error properly propagates to either an interrupt or an alert.

This is the state of the ENTROPY_SRC main state machine. See the RTL file entropy_src_main_sm for the meaning of the values.