Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module entropy_src has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: none
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
entropy_src_hw_ifentropy_src_pkg::entropy_src_hw_ifreq_rsprsp1
cs_aes_haltentropy_src_pkg::cs_aes_haltreq_rspreq1Coordinate activity between CSRNG’s AES and Entropy Source’s SHA3. The idea is that Entropy Source requests CSRNG’s AES to halt and waits for CSRNG to acknowledge before it starts its SHA3. While SHA3 runs, Entropy Source keeps the request high. CSRNG may not drop the acknowledge before Entropy Source drops the request. Current limitations: 1. During startup and in Firmware Override - Extract & Insert mode, Entropy Source makes no AES Halt requests but still activates its SHA3 engine. 2. Outside Firmware Override - Extract & Insert mode, Entropy Source may activate its SHA3 engine without requesting AES Halt, but no more than for 24 Keccak rounds (24 clock cycles) every 512 clock cycles.
entropy_src_rngentropy_src_pkg::entropy_src_rngreq_rspreq1
entropy_src_xhtentropy_src_pkg::entropy_src_xhtreq_rspreq1
otp_en_entropy_src_fw_readprim_mubi_pkg::mubi8unircv1
otp_en_entropy_src_fw_overprim_mubi_pkg::mubi8unircv1
rng_fipslogicunireq1
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
es_entropy_validEventAsserted when entropy source bits are available.
es_health_test_failedEventAsserted when the alert count has been met.
es_observe_fifo_readyEventAsserted when the observe FIFO has filled to the threshold level.
es_fatal_errEventAsserted when a FIFO error occurs, or if an illegal state machine state is reached.

Security Alerts

Alert NameDescription
recov_alertThis alert is triggered upon the alert health test threshold criteria not met.
fatal_alertThis alert triggers for any condition detected in the ERR_CODE register, which includes FIFO errors, COUNTER errors, FSM state errors, and also when integrity failures are detected on the TL-UL bus.

Security Countermeasures

Countermeasure IDDescription
ENTROPY_SRC.CONFIG.REGWENRegisters are protected from writes.
ENTROPY_SRC.CONFIG.MUBIRegisters have multi-bit encoded fields.
ENTROPY_SRC.CONFIG.REDUNThreshold register has an inverted copy to compare against.
ENTROPY_SRC.INTERSIG.MUBIOTP signal used to enable software access to registers.
ENTROPY_SRC.MAIN_SM.FSM.SPARSEThe ENTROPY_SRC main state machine uses a sparse state encoding.
ENTROPY_SRC.ACK_SM.FSM.SPARSEThe ENTROPY_SRC ack state machine uses a sparse state encoding.
ENTROPY_SRC.RNG.BKGN_CHKRandom number generator is protected with continuous background health checks.
ENTROPY_SRC.CTR.REDUNCounter hardening for all health test counters.
ENTROPY_SRC.CTR.LOCAL_ESCRedundant counter failures will cause a local escalation to the main state machine.
ENTROPY_SRC.ESFINAL_RDATA.BUS.CONSISTENCYComparison on successive bus values for the post-conditioned entropy seed bus.
ENTROPY_SRC.TILE_LINK.BUS.INTEGRITYTilelink end-to-end bus integrity scheme.

Registers

Summary

NameOffsetLengthDescription
entropy_src.CIP_ID0x04Comportable IP ID.
entropy_src.REVISION0x44Comportable IP semantic version.
entropy_src.PARAMETER_BLOCK_TYPE0x84Parameter block type.
entropy_src.PARAMETER_BLOCK_LENGTH0xc4Parameter block length.
entropy_src.NEXT_PARAMETER_BLOCK0x104Next parameter block offset.
entropy_src.INTR_STATE0x404Interrupt State Register
entropy_src.INTR_ENABLE0x444Interrupt Enable Register
entropy_src.INTR_TEST0x484Interrupt Test Register
entropy_src.ALERT_TEST0x4c4Alert Test Register
entropy_src.ME_REGWEN0x504Register write enable for module enable register
entropy_src.SW_REGUPD0x544Register write enable for control and threshold registers
entropy_src.REGWEN0x584Register write enable for all control registers
entropy_src.REV0x5c4Revision register
entropy_src.MODULE_ENABLE0x604Module enable register
entropy_src.CONF0x644Configuration register
entropy_src.ENTROPY_CONTROL0x684Entropy control register
entropy_src.ENTROPY_DATA0x6c4Entropy data bits
entropy_src.HEALTH_TEST_WINDOWS0x704Health test windows register
entropy_src.REPCNT_THRESHOLDS0x744Repetition count test thresholds register
entropy_src.REPCNTS_THRESHOLDS0x784Repetition count symbol test thresholds register
entropy_src.ADAPTP_HI_THRESHOLDS0x7c4Adaptive proportion test high thresholds register
entropy_src.ADAPTP_LO_THRESHOLDS0x804Adaptive proportion test low thresholds register
entropy_src.BUCKET_THRESHOLDS0x844Bucket test thresholds register
entropy_src.MARKOV_HI_THRESHOLDS0x884Markov test high thresholds register
entropy_src.MARKOV_LO_THRESHOLDS0x8c4Markov test low thresholds register
entropy_src.EXTHT_HI_THRESHOLDS0x904External health test high thresholds register
entropy_src.EXTHT_LO_THRESHOLDS0x944External health test low thresholds register
entropy_src.REPCNT_HI_WATERMARKS0x984Repetition count test high watermarks register
entropy_src.REPCNTS_HI_WATERMARKS0x9c4Repetition count symbol test high watermarks register
entropy_src.ADAPTP_HI_WATERMARKS0xa04Adaptive proportion test high watermarks register
entropy_src.ADAPTP_LO_WATERMARKS0xa44Adaptive proportion test low watermarks register
entropy_src.EXTHT_HI_WATERMARKS0xa84External health test high watermarks register
entropy_src.EXTHT_LO_WATERMARKS0xac4External health test low watermarks register
entropy_src.BUCKET_HI_WATERMARKS0xb04Bucket test high watermarks register
entropy_src.MARKOV_HI_WATERMARKS0xb44Markov test high watermarks register
entropy_src.MARKOV_LO_WATERMARKS0xb84Markov test low watermarks register
entropy_src.REPCNT_TOTAL_FAILS0xbc4Repetition count test failure counter register
entropy_src.REPCNTS_TOTAL_FAILS0xc04Repetition count symbol test failure counter register
entropy_src.ADAPTP_HI_TOTAL_FAILS0xc44Adaptive proportion high test failure counter register
entropy_src.ADAPTP_LO_TOTAL_FAILS0xc84Adaptive proportion low test failure counter register
entropy_src.BUCKET_TOTAL_FAILS0xcc4Bucket test failure counter register
entropy_src.MARKOV_HI_TOTAL_FAILS0xd04Markov high test failure counter register
entropy_src.MARKOV_LO_TOTAL_FAILS0xd44Markov low test failure counter register
entropy_src.EXTHT_HI_TOTAL_FAILS0xd84External health test high threshold failure counter register
entropy_src.EXTHT_LO_TOTAL_FAILS0xdc4External health test low threshold failure counter register
entropy_src.ALERT_THRESHOLD0xe04Alert threshold register
entropy_src.ALERT_SUMMARY_FAIL_COUNTS0xe44Alert summary failure counts register
entropy_src.ALERT_FAIL_COUNTS0xe84Alert failure counts register
entropy_src.EXTHT_FAIL_COUNTS0xec4External health test alert failure counts register
entropy_src.FW_OV_CONTROL0xf04Firmware override control register
entropy_src.FW_OV_SHA3_START0xf44Firmware override sha3 block start control register
entropy_src.FW_OV_WR_FIFO_FULL0xf84Firmware override FIFO write full status register
entropy_src.FW_OV_RD_FIFO_OVERFLOW0xfc4Firmware override observe FIFO overflow status
entropy_src.FW_OV_RD_DATA0x1004Firmware override observe FIFO read register
entropy_src.FW_OV_WR_DATA0x1044Firmware override FIFO write register
entropy_src.OBSERVE_FIFO_THRESH0x1084Observe FIFO threshold register
entropy_src.OBSERVE_FIFO_DEPTH0x10c4Observe FIFO depth register
entropy_src.DEBUG_STATUS0x1104Debug status register
entropy_src.RECOV_ALERT_STS0x1144Recoverable alert status register
entropy_src.ERR_CODE0x1184Hardware detection of error conditions status register
entropy_src.ERR_CODE_TEST0x11c4Test error conditions register
entropy_src.MAIN_SM_STATE0x1204Main state machine state debug register

CIP_ID

Comportable IP ID.

  • Offset: 0x0
  • Reset default: 0x7
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x7CIP_IDThis value is a unique comportable IP identifier.

REVISION

Comportable IP semantic version.

  • Offset: 0x4
  • Reset default: 0x2000000
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:24ro0x2MAJORMajor version number.
23:16ro0x0MINORMinor version number.
15:8ro0x0SUBMINORSubminor (patch) version number.
7:0ro0x0RESERVEDReserved version number.

PARAMETER_BLOCK_TYPE

Parameter block type.

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x0BLOCK_TYPEParameter block type.

PARAMETER_BLOCK_LENGTH

Parameter block length.

  • Offset: 0xc
  • Reset default: 0xc
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0xcBLOCK_LENGTHParameter block length in bytes.

NEXT_PARAMETER_BLOCK

Next parameter block offset.

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x0BLOCK_OFFSETThis offset value is zero if there is no other parameter block.

INTR_STATE

Interrupt State Register

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw1c0x0es_fatal_errAsserted when a FIFO error occurs, or if an illegal state machine state is reached.
2rw1c0x0es_observe_fifo_readyAsserted when the observe FIFO has filled to the threshold level.
1rw1c0x0es_health_test_failedAsserted when the alert count has been met.
0rw1c0x0es_entropy_validAsserted when entropy source bits are available.

INTR_ENABLE

Interrupt Enable Register

  • Offset: 0x44
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3rw0x0es_fatal_errEnable interrupt when INTR_STATE.es_fatal_err is set.
2rw0x0es_observe_fifo_readyEnable interrupt when INTR_STATE.es_observe_fifo_ready is set.
1rw0x0es_health_test_failedEnable interrupt when INTR_STATE.es_health_test_failed is set.
0rw0x0es_entropy_validEnable interrupt when INTR_STATE.es_entropy_valid is set.

INTR_TEST

Interrupt Test Register

  • Offset: 0x48
  • Reset default: 0x0
  • Reset mask: 0xf

Fields

BitsTypeResetNameDescription
31:4Reserved
3wo0x0es_fatal_errWrite 1 to force INTR_STATE.es_fatal_err to 1.
2wo0x0es_observe_fifo_readyWrite 1 to force INTR_STATE.es_observe_fifo_ready to 1.
1wo0x0es_health_test_failedWrite 1 to force INTR_STATE.es_health_test_failed to 1.
0wo0x0es_entropy_validWrite 1 to force INTR_STATE.es_entropy_valid to 1.

ALERT_TEST

Alert Test Register

  • Offset: 0x4c
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1wo0x0fatal_alertWrite 1 to trigger one alert event of this kind.
0wo0x0recov_alertWrite 1 to trigger one alert event of this kind.

ME_REGWEN

Register write enable for module enable register

  • Offset: 0x50
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1ME_REGWENWhen true, the MODULE_ENABLE register can be modified. When false, it becomes read-only.

SW_REGUPD

Register write enable for control and threshold registers

  • Offset: 0x54
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1SW_REGUPDWhen this bit true and the MODULE_ENABLE field is false, the REGWEN write enable bit read as true, and is distributed to all associated control and threshold registers. When false, these registers become read-only.

REGWEN

Register write enable for all control registers

  • Offset: 0x58
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetName
31:1Reserved
0ro0x1REGWEN

REGWEN . REGWEN

This read-only write enable bit will allow write access to control and threshold registers that are associated with this bit, but only when the MODULE_ENABLE register is set to kMultiBitBool4False and the SW_REGUPD write enable bit is set to true. When read as false, these registers become read-only.

REV

Revision register

  • Offset: 0x5c
  • Reset default: 0x10303
  • Reset mask: 0xffffff

Fields

BitsTypeResetNameDescription
31:24Reserved
23:16ro0x1CHIP_TYPERead of this register shows the type of chip using this block.
15:8ro0x3HW_REVISIONRead of this register shows the revision of this block.
7:0ro0x3ABI_REVISIONRead of this register shows the ABI of this block.

MODULE_ENABLE

Module enable register

  • Offset: 0x60
  • Reset default: 0x9
  • Reset mask: 0xf
  • Register enable: ME_REGWEN

Fields

BitsTypeResetName
31:4Reserved
3:0rw0x9MODULE_ENABLE

MODULE_ENABLE . MODULE_ENABLE

Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting this field to kMultiBitBool4False will effectively reset the module. The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details.

CONF

Configuration register

  • Offset: 0x64
  • Reset default: 0x909099
  • Reset mask: 0x3f0f0ff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:26Reserved
25:24rw0x0RNG_BIT_SEL
23:20rw0x9RNG_BIT_ENABLE
19:16Reserved
15:12rw0x9THRESHOLD_SCOPE
11:8Reserved
7:4rw0x9ENTROPY_DATA_REG_ENABLE
3:0rw0x9FIPS_ENABLE

CONF . RNG_BIT_SEL

When the above bit iset, this field selects which bit from the RNG bus will be processed when in single RNG bit mode. This two bit field selects the RNG bit stream: 0b00: RNG bit 0 0b01: RNG bit 1 0b10: RNG bit 2 0b11: RNG bit 3

CONF . RNG_BIT_ENABLE

Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only one bit is sampled. Note that the ENTROPY_SRC block can only generate FIPS qualified entropy if this field is set to kMultiBitBool4False. Additional requirements to generate FIPS qualified entropy are i) that CONF.FIPS_ENABLE is set to kMultiBitBool4True, and ii) that at most one of the ENTROPY_CONTROL.ES_ROUTE and ENTROPY_CONTROL.ES_TYPE fields but not both are set to kMultiBitBool4True.

CONF . THRESHOLD_SCOPE

This field controls the scope (either by-line or by-sum) of the health checks. If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all RNG input lines into a single score, and thresholds will be applied to the sum all the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored individually. A statistical deviation in any one input line, be it due to coincidence or failure, will force rejection of the sample, and count toward the total alert count.

CONF . ENTROPY_DATA_REG_ENABLE

Setting this field to kMultiBitBool4True will enable reading entropy values from the ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read input is set to kMultiBitBool8True.

CONF . FIPS_ENABLE

Setting this field to kMultiBitBool4True selects the FIPS/CC compliant mode (or short FIPS mode). In this mode, the ENTROPY_SRC block can generate FIPS qualified entropy. Additional requirements to generate FIPS qualified entropy are i) that at most one of the ENTROPY_CONTROL.ES_ROUTE and ENTROPY_CONTROL.ES_TYPE fields are set to kMultiBitBool4True but not both, and ii) that CONF.RNG_BIT_ENABLE is set to kMultiBitBool4False.

Setting this field to kMultiBitBool4False selects the boot-time / bypass mode in which the hardware conditioning is bypassed.

ENTROPY_CONTROL

Entropy control register

  • Offset: 0x68
  • Reset default: 0x99
  • Reset mask: 0xff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:8Reserved
7:4rw0x9ES_TYPE
3:0rw0x9ES_ROUTE

ENTROPY_CONTROL . ES_TYPE

When this field is kMultiBitBool4False, the hardware conditioning inside the ENTROPY_SRC block is enabled. Setting this field to kMultiBitBool4True will bypass the hardware conditioning. For this to work, also ENTROPY_CONTROL.ES_ROUTE needs to be set to kMultiBitBool4True to route the unconditioned, raw entropy to the ENTROPY_DATA register. Alternatively, the hardware conditioning can be bypassed by setting CONF.FIPS_ENABLE to kMultiBitBool4False to disable FIPS mode and enable bypass / boot-time mode. In both cases, the ENTROPY_SRC block will not generate FIPS qualified entropy.

To generate FIPS qualified entropy, i) CONF.FIPS_ENABLE needs to be set to kMultiBitBool4True, ii) CONF.RNG_BIT_ENABLE needs to be set to kMultiBitBool4False, and iii) at most one of the ENTROPY_CONTROL.ES_ROUTE and ENTROPY_CONTROL.ES_TYPE fields needs to be set to kMultiBitBool4True but not both.

ENTROPY_CONTROL . ES_ROUTE

When this field is kMultiBitBool4False, the generated entropy will be forwarded out of this module to the hardware interface. Setting this field to kMultiBitBool4True routes the generated entropy to the ENTROPY_DATA register to be read by firmware. Note that for ENTROPY_DATA to become readable, also CONF.ENTROPY_DATA_REG_ENABLE needs to be set to kMultiBitBool4True. In addition, the otp_en_entropy_src_fw_read input needs to be set to kMultiBitBool8True.

ENTROPY_DATA

Entropy data bits

  • Offset: 0x6c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0roxENTROPY_DATA

ENTROPY_DATA . ENTROPY_DATA

A read of this register provides generated entropy bits to firmware. For this to work also CONF.ENTROPY_DATA_REG_ENABLE needs to be set to kMultiBitBool4True. In addition, the otp_en_entropy_src_fw_read input needs to be set to kMultiBitBool8True.

HEALTH_TEST_WINDOWS

Health test windows register

  • Offset: 0x70
  • Reset default: 0x600200
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0x60BYPASS_WINDOW
15:0rw0x200FIPS_WINDOW

HEALTH_TEST_WINDOWS . BYPASS_WINDOW

This is the window size for all health tests when running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware by setting CONF.FIPS_ENABLE to kMultiBitBool4False. The default value is (384 bits * 1 clock/4 bits);

Note that currently only a window size of 384 is supported and tested (this corresponds to the register default value 0x60). Do not use any other values, unless you know what you are doing.

HEALTH_TEST_WINDOWS . FIPS_WINDOW

This is the window size for all health tests. This value is used when entropy is being tested in FIPS/CC compliance mode (for simplicity referred to as FIPS mode). The default value is (2048 bits * 1 clock/4 bits);

REPCNT_THRESHOLDS

Repetition count test thresholds register

  • Offset: 0x74
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0xffffBYPASS_THRESH
15:0rw0xffffFIPS_THRESH

REPCNT_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the repetition count health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

REPCNT_THRESHOLDS . FIPS_THRESH

This is the threshold size for the repetition count health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

REPCNTS_THRESHOLDS

Repetition count symbol test thresholds register

  • Offset: 0x78
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0xffffBYPASS_THRESH
15:0rw0xffffFIPS_THRESH

REPCNTS_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the repetition count symbol health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

REPCNTS_THRESHOLDS . FIPS_THRESH

This is the threshold size for the repetition count symbol health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

ADAPTP_HI_THRESHOLDS

Adaptive proportion test high thresholds register

  • Offset: 0x7c
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0xffffBYPASS_THRESH
15:0rw0xffffFIPS_THRESH

ADAPTP_HI_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

ADAPTP_HI_THRESHOLDS . FIPS_THRESH

This is the threshold size for the adaptive proportion health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

ADAPTP_LO_THRESHOLDS

Adaptive proportion test low thresholds register

  • Offset: 0x80
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0x0BYPASS_THRESH
15:0rw0x0FIPS_THRESH

ADAPTP_LO_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

ADAPTP_LO_THRESHOLDS . FIPS_THRESH

This is the threshold size for the adaptive proportion health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

BUCKET_THRESHOLDS

Bucket test thresholds register

  • Offset: 0x84
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0xffffBYPASS_THRESH
15:0rw0xffffFIPS_THRESH

BUCKET_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the bucket health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

BUCKET_THRESHOLDS . FIPS_THRESH

This is the threshold size for the bucket health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

MARKOV_HI_THRESHOLDS

Markov test high thresholds register

  • Offset: 0x88
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0xffffBYPASS_THRESH
15:0rw0xffffFIPS_THRESH

MARKOV_HI_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

MARKOV_HI_THRESHOLDS . FIPS_THRESH

This is the threshold size for the Markov health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

MARKOV_LO_THRESHOLDS

Markov test low thresholds register

  • Offset: 0x8c
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0x0BYPASS_THRESH
15:0rw0x0FIPS_THRESH

MARKOV_LO_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

MARKOV_LO_THRESHOLDS . FIPS_THRESH

This is the threshold size for the Markov health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

EXTHT_HI_THRESHOLDS

External health test high thresholds register

  • Offset: 0x90
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0xffffBYPASS_THRESH
15:0rw0xffffFIPS_THRESH

EXTHT_HI_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

EXTHT_HI_THRESHOLDS . FIPS_THRESH

This is the threshold size for the external health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value.

EXTHT_LO_THRESHOLDS

External health test low thresholds register

  • Offset: 0x94
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:16rw0x0BYPASS_THRESH
15:0rw0x0FIPS_THRESH

EXTHT_LO_THRESHOLDS . BYPASS_THRESH

This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

EXTHT_LO_THRESHOLDS . FIPS_THRESH

This is the threshold size for the external health test. This value is used in FIPS mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value.

REPCNT_HI_WATERMARKS

Repetition count test high watermarks register

  • Offset: 0x98
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16roxBYPASS_WATERMARKHigh watermark value of the REPCNT test in bypass mode.
15:0roxFIPS_WATERMARKHigh watermark value of the REPCNT test in FIPS mode.

REPCNTS_HI_WATERMARKS

Repetition count symbol test high watermarks register

  • Offset: 0x9c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16roxBYPASS_WATERMARKHigh watermark value of the REPCNTS test in bypass mode.
15:0roxFIPS_WATERMARKHigh watermark value of the REPCNTS test in FIPS mode.

ADAPTP_HI_WATERMARKS

Adaptive proportion test high watermarks register

  • Offset: 0xa0
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16roxBYPASS_WATERMARKHigh watermark value of the adaptive proportion test in bypass mode.
15:0roxFIPS_WATERMARKHigh watermark value of the adaptive proportion test in FIPS mode.

ADAPTP_LO_WATERMARKS

Adaptive proportion test low watermarks register

  • Offset: 0xa4
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16ro0xffffBYPASS_WATERMARKLow watermark value of the adaptive proportion test in bypass mode.
15:0ro0xffffFIPS_WATERMARKLow watermark value of the adaptive proportion test in FIPS mode.

EXTHT_HI_WATERMARKS

External health test high watermarks register

  • Offset: 0xa8
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16roxBYPASS_WATERMARKHigh watermark value of the external health test in bypass mode.
15:0roxFIPS_WATERMARKHigh watermark value of the external health test in FIPS mode.

EXTHT_LO_WATERMARKS

External health test low watermarks register

  • Offset: 0xac
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16ro0xffffBYPASS_WATERMARKLow watermark value of the external health test in bypass mode.
15:0ro0xffffFIPS_WATERMARKLow watermark value of the external health test in FIPS mode.

BUCKET_HI_WATERMARKS

Bucket test high watermarks register

  • Offset: 0xb0
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16roxBYPASS_WATERMARKHigh watermark value of the bucket test in bypass mode.
15:0roxFIPS_WATERMARKHigh watermark value of the bucket test in FIPS mode.

MARKOV_HI_WATERMARKS

Markov test high watermarks register

  • Offset: 0xb4
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16roxBYPASS_WATERMARKHigh watermark value of the Markov test in bypass mode.
15:0roxFIPS_WATERMARKHigh watermark value of the Markov test in FIPS mode.

MARKOV_LO_WATERMARKS

Markov test low watermarks register

  • Offset: 0xb8
  • Reset default: 0xffffffff
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:16ro0xffffBYPASS_WATERMARKLow watermark value of the Markov test in bypass mode.
15:0ro0xffffFIPS_WATERMARKLow watermark value of the Markov test in FIPS mode.

REPCNT_TOTAL_FAILS

Repetition count test failure counter register

  • Offset: 0xbc
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxREPCNT_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

REPCNTS_TOTAL_FAILS

Repetition count symbol test failure counter register

  • Offset: 0xc0
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxREPCNTS_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

ADAPTP_HI_TOTAL_FAILS

Adaptive proportion high test failure counter register

  • Offset: 0xc4
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxADAPTP_HI_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

ADAPTP_LO_TOTAL_FAILS

Adaptive proportion low test failure counter register

  • Offset: 0xc8
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxADAPTP_LO_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

BUCKET_TOTAL_FAILS

Bucket test failure counter register

  • Offset: 0xcc
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxBUCKET_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

MARKOV_HI_TOTAL_FAILS

Markov high test failure counter register

  • Offset: 0xd0
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxMARKOV_HI_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

MARKOV_LO_TOTAL_FAILS

Markov low test failure counter register

  • Offset: 0xd4
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxMARKOV_LO_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

EXTHT_HI_TOTAL_FAILS

External health test high threshold failure counter register

  • Offset: 0xd8
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxEXTHT_HI_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

EXTHT_LO_TOTAL_FAILS

External health test low threshold failure counter register

  • Offset: 0xdc
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0roxEXTHT_LO_TOTAL_FAILSThis register will hold a running count of test failures observed during normal operation. It will persist until cleared.

ALERT_THRESHOLD

Alert threshold register

  • Offset: 0xe0
  • Reset default: 0xfffd0002
  • Reset mask: 0xffffffff
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:16rw0xfffdALERT_THRESHOLD_INVThis should be set to the value above, but inverted.
15:0rw0x2ALERT_THRESHOLDThis is the threshold size that will signal an alert when value is reached. A value of zero will disable alerts. The default value is 2.

ALERT_SUMMARY_FAIL_COUNTS

Alert summary failure counts register

  • Offset: 0xe4
  • Reset default: 0x0
  • Reset mask: 0xffff

Fields

BitsTypeResetName
31:16Reserved
15:0roxANY_FAIL_COUNT

ALERT_SUMMARY_FAIL_COUNTS . ANY_FAIL_COUNT

This field will hold a running count of the total alert count, which is a sum of all of the other counters in the ALERT_FAIL_COUNTS register. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

ALERT_FAIL_COUNTS

Alert failure counts register

  • Offset: 0xe8
  • Reset default: 0x0
  • Reset mask: 0xfffffff0

Fields

BitsTypeResetName
31:28roxREPCNTS_FAIL_COUNT
27:24roxMARKOV_LO_FAIL_COUNT
23:20roxMARKOV_HI_FAIL_COUNT
19:16roxBUCKET_FAIL_COUNT
15:12roxADAPTP_LO_FAIL_COUNT
11:8roxADAPTP_HI_FAIL_COUNT
7:4roxREPCNT_FAIL_COUNT
3:0Reserved

ALERT_FAIL_COUNTS . REPCNTS_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

ALERT_FAIL_COUNTS . MARKOV_LO_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

ALERT_FAIL_COUNTS . MARKOV_HI_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

ALERT_FAIL_COUNTS . BUCKET_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

ALERT_FAIL_COUNTS . ADAPTP_LO_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

ALERT_FAIL_COUNTS . ADAPTP_HI_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

ALERT_FAIL_COUNTS . REPCNT_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

EXTHT_FAIL_COUNTS

External health test alert failure counts register

  • Offset: 0xec
  • Reset default: 0x0
  • Reset mask: 0xff

Fields

BitsTypeResetName
31:8Reserved
7:4roxEXTHT_LO_FAIL_COUNT
3:0roxEXTHT_HI_FAIL_COUNT

EXTHT_FAIL_COUNTS . EXTHT_LO_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

EXTHT_FAIL_COUNTS . EXTHT_HI_FAIL_COUNT

This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence unless in firmware override mode (extract and insert only). If an alert is signaled, this value will persist until it is cleared.

FW_OV_CONTROL

Firmware override control register

  • Offset: 0xf0
  • Reset default: 0x99
  • Reset mask: 0xff
  • Register enable: REGWEN

Fields

BitsTypeResetName
31:8Reserved
7:4rw0x9FW_OV_ENTROPY_INSERT
3:0rw0x9FW_OV_MODE

FW_OV_CONTROL . FW_OV_ENTROPY_INSERT

Setting this field to kMultiBitBool4True allows firmware to extract entropy bits by reading the observe FIFO (see FW_OV_RD_DATA) and insert entropy bits into the entropy flow by writing the FW_OV_WR_DATA register. This is useful e.g. for performing additional health tests and/or firmware-based conditioning. For this to work, FW_OV_CONTROL.FW_OV_MODE needs to be set to kMultiBitBool4True. In addition, the otp_en_entropy_src_fw_over input needs to be set to kMultiBitBool8True.

Firmware can use the hardware conditioning for the inserted entropy bits (see FW_OV_SHA3_START).

Note that if the field is set to kMultiBitBool4True, post-health test entropy bits do NOT continue to flow through the hardware pipeline. Also, the FW_OV_CONTROL.FW_OV_MODE bit must be set. The observe FIFO will collect 2 kBit of contiguous entropy bits. Any entropy bits arriving after the observe FIFO is full are being discarded. Firmware has to read out the entire observe FIFO to restart entropy collection. Only entropy bits inserted by firmware by writing FW_OV_WR_DATA may eventually reach the block hardware interface.

FW_OV_CONTROL . FW_OV_MODE

Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. In this mode, firmware can monitor the post-health test entropy by reading the observe FIFO (see FW_OV_RD_DATA). For this to work, the otp_en_entropy_src_fw_over input needs to be set to kMultiBitBool8True.

Note that the post-health test entropy bits collected in the observe FIFO continue to flow through the hardware pipeline and may eventually reach the block hardware interface.

FW_OV_SHA3_START

Firmware override sha3 block start control register

  • Offset: 0xf4
  • Reset default: 0x9
  • Reset mask: 0xf

Fields

BitsTypeResetName
31:4Reserved
3:0rw0x9FW_OV_INSERT_START

FW_OV_SHA3_START . FW_OV_INSERT_START

Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine to start the SHA3 process and be ready to accept entropy data. This field should be set prior to writing the FW_OV_WR_DATA register. Once all data has been written, this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish processing and push the result into the esfinal FIFO.

Note that clearing this bit to kMultiBitBool4False while there is still unprocessed entropy in FW_OV_WR_DATA will start the SHA3 engine before data can be added to the input message, and will also signal a recoverable alert in RECOV_ALERT_STS.ES_FW_OV_DISABLE_ALERT. To avoid this, check that FW_OV_WR_FIFO_FULL is clear before setting this field to kMultiBitBool4False.

FW_OV_WR_FIFO_FULL

Firmware override FIFO write full status register

  • Offset: 0xf8
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0roxFW_OV_WR_FIFO_FULL“When this bit is clear, writes to the FW_OV_WR_DATA register are allowed. If this bit is set, it is the equivalent to a FIFO full condition, and writes to the FW_OV_WR_DATA register must be delayed until this bit is reset.

FW_OV_RD_FIFO_OVERFLOW

Firmware override observe FIFO overflow status

  • Offset: 0xfc
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetName
31:1Reserved
0rw0c0x0FW_OV_RD_FIFO_OVERFLOW

FW_OV_RD_FIFO_OVERFLOW . FW_OV_RD_FIFO_OVERFLOW

This bit is set by hardware whenever RNG data is lost due to an overflow condition in the observe FIFO. The RNG data rate is slow enough that firmware should always be able to keep up. This register meanwhile provides an additional check to confirm that bytes read from the FW_OV_RD_DATA register represent contiguous RNG samples. If an overflow event occurs, this bit must be cleared by software.

FW_OV_RD_DATA

Firmware override observe FIFO read register

  • Offset: 0x100
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0roxFW_OV_RD_DATA

FW_OV_RD_DATA . FW_OV_RD_DATA

A read of this register pops and returns the top of the observe FIFO. For this to work, the FW_OV_CONTROL.FW_OV_MODE field needs to be set to kMultiBitBool4True In addition, the otp_en_entropy_src_fw_over input needs to be set to kMultiBitBool8True.

FW_OV_WR_DATA

Firmware override FIFO write register

  • Offset: 0x104
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetName
31:0woxFW_OV_WR_DATA

FW_OV_WR_DATA . FW_OV_WR_DATA

A write to this register will insert entropy back into the entropy source module flow. For this to work, both the FW_OV_CONTROL.FW_OV_MODE and FW_OV_CONTROL.FW_OV_ENTROPY_INSERT fields need to be set to kMultiBitBool4True. In addition, the otp_en_entropy_src_fw_over input needs to be set to kMultiBitBool8True.

OBSERVE_FIFO_THRESH

Observe FIFO threshold register

  • Offset: 0x108
  • Reset default: 0x20
  • Reset mask: 0x7f
  • Register enable: REGWEN

Fields

BitsTypeResetNameDescription
31:7Reserved
6:0rw0x20OBSERVE_FIFO_THRESHThis field will set the threshold that the depth of the observe FIFO will be compared with when setting the interrupt status bit. Note: a value of zero is reserved and not to be used.

OBSERVE_FIFO_DEPTH

Observe FIFO depth register

  • Offset: 0x10c
  • Reset default: 0x0
  • Reset mask: 0x7f

Fields

BitsTypeResetNameDescription
31:7Reserved
6:0roxOBSERVE_FIFO_DEPTHThis field will hold the current depth of the observe FIFO.

DEBUG_STATUS

Debug status register

  • Offset: 0x110
  • Reset default: 0x10000
  • Reset mask: 0x303ff

Fields

BitsTypeResetNameDescription
31:18Reserved
17roxMAIN_SM_BOOT_DONEThe entropy_src main state machine is in the boot phase done state.
16ro0x1MAIN_SM_IDLEThe entropy_src main state machine is in the idle state.
15:10Reserved
9roxSHA3_ERRThis is a logic-or of all of the SHA3 error signals.
8roxSHA3_ABSORBEDThis is the SHA3 absorbed signal current state.
7roxSHA3_SQUEEZINGThis is the SHA3 squeezing signal current state.
6roxSHA3_BLOCK_PRThis is the SHA3 block processed signal current state.
5:3roxSHA3_FSMThis is the SHA3 finite state machine current state.
2:0roxENTROPY_FIFO_DEPTHThis is the depth of the entropy source FIFO.

RECOV_ALERT_STS

Recoverable alert status register

  • Offset: 0x114
  • Reset default: 0x0
  • Reset mask: 0x1ffaf

Fields

RECOV_ALERT_STS . ES_FW_OV_DISABLE_ALERT

This bit is set when FW_OV_SHA3_START has been set to kMultiBitBool4False, without waiting for the bypass packer FIFO to clear. The final entropy entry in the FIFO will not be included in the SHA3 digest. (Rather it will be added to the subsequent SHA3 digest.) To avoid this alert, monitor FW_OV_WR_FIFO_FULL before clearing FW_OV_SHA3_START. This alert only applies when both FW_OV_CONTROL.FW_OV_MODE and FW_OV_CONTROL.FW_OV_ENTROPY_INSERT are set to kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_FW_OV_WR_ALERT

This bit is set when the packer FIFO has been written but was full at the time, and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes. This alert would normally be the result of not monitoring the FW_OV_WR_FIFO_FULL register before each write to the FW_OV_WR_DATA register. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_THRESH_CFG_ALERT

This bit is set when the ALERT_THRESHOLD register is not configured properly. The upper field must be the exact inverse of the lower field. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_BUS_CMP_ALERT

This bit is set when the interal entropy bus value is equal to the prior valid value on the bus, indicating a possible attack. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_MAIN_SM_ALERT

This bit is set when the main state machine detects a threshhold failure state. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_TYPE_FIELD_ALERT

This bit is set when the ES_TYPE field in the ENTROPY_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . ES_ROUTE_FIELD_ALERT

This bit is set when the ES_ROUTE field in the ENTROPY_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FW_OV_ENTROPY_INSERT_FIELD_ALERT

This bit is set when the FW_OV_ENTROPY_INSERT field in the FW_OV_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FW_OV_MODE_FIELD_ALERT

This bit is set when the FW_OV_MODE field in the FW_OV_CONTROL register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FW_OV_SHA3_START_FIELD_ALERT

This bit is set when the FW_OV_SHA3_START field in the FW_OV_SHA3_START register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . RNG_BIT_ENABLE_FIELD_ALERT

This bit is set when the RNG_BIT_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . THRESHOLD_SCOPE_FIELD_ALERT

This bit is set when the THRESHOLD_SCOPE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . MODULE_ENABLE_FIELD_ALERT

This bit is set when the MODULE_ENABLE field in the MODULE_ENABLE register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . ENTROPY_DATA_REG_EN_FIELD_ALERT

This bit is set when the ENTROPY_DATA_REG_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

RECOV_ALERT_STS . FIPS_ENABLE_FIELD_ALERT

This bit is set when the FIPS_ENABLE field in the CONF register is set to a value other than kMultiBitBool4False or kMultiBitBool4True. Writing a zero resets this status bit.

ERR_CODE

Hardware detection of error conditions status register

  • Offset: 0x118
  • Reset default: 0x0
  • Reset mask: 0x71f00007

Fields

BitsTypeResetName
31Reserved
30ro0x0FIFO_STATE_ERR
29ro0x0FIFO_READ_ERR
28ro0x0FIFO_WRITE_ERR
27:25Reserved
24ro0x0SHA3_RST_STORAGE_ERR
23ro0x0SHA3_STATE_ERR
22ro0x0ES_CNTR_ERR
21ro0x0ES_MAIN_SM_ERR
20ro0x0ES_ACK_SM_ERR
19:3Reserved
2ro0x0SFIFO_ESFINAL_ERR
1ro0x0SFIFO_OBSERVE_ERR
0ro0x0SFIFO_ESRNG_ERR

ERR_CODE . FIFO_STATE_ERR

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any FIFO where both the empty and full status bits are set. This bit will stay set until the next reset.

ERR_CODE . FIFO_READ_ERR

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any empty FIFO that has recieved a read pulse. This bit will stay set until the next reset.

ERR_CODE . FIFO_WRITE_ERR

This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any full FIFO that has been recieved a write pulse. This bit will stay set until the next reset.

ERR_CODE . SHA3_RST_STORAGE_ERR

This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being active has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . SHA3_STATE_ERR

This bit will be set to one when a SHA3 state error has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . ES_CNTR_ERR

This bit will be set to one when a hardened counter has detected an error condition. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . ES_MAIN_SM_ERR

This bit will be set to one when an illegal state has been detected for the ES main stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . ES_ACK_SM_ERR

This bit will be set to one when an illegal state has been detected for the ES ack stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset.

ERR_CODE . SFIFO_ESFINAL_ERR

This bit will be set to one when an error has been detected for the esfinal FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_OBSERVE_ERR

This bit will be set to one when an error has been detected for the observe FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE . SFIFO_ESRNG_ERR

This bit will be set to one when an error has been detected for the esrng FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset.

ERR_CODE_TEST

Test error conditions register

  • Offset: 0x11c
  • Reset default: 0x0
  • Reset mask: 0x1f

Fields

BitsTypeResetName
31:5Reserved
4:0rw0x0ERR_CODE_TEST

ERR_CODE_TEST . ERR_CODE_TEST

Setting this field will set the bit number for which an error will be forced in the hardware. This bit number is that same one found in the ERR_CODE register. The action of writing this register will force an error pulse. The sole purpose of this register is to test that any error properly propagates to either an interrupt or an alert.

MAIN_SM_STATE

Main state machine state debug register

  • Offset: 0x120
  • Reset default: 0xf5
  • Reset mask: 0x1ff

Fields

BitsTypeResetNameDescription
31:9Reserved
8:0ro0xf5MAIN_SM_STATEThis is the state of the ENTROPY_SRC main state machine. See the RTL file entropy_src_main_sm for the meaning of the values.