Hardware Interfaces and Registers
Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module entropy_src
has the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: none
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO: none
Inter-Module Signals: Reference
Port Name | Package::Struct | Type | Act | Width | Description |
---|---|---|---|---|---|
entropy_src_hw_if | entropy_src_pkg::entropy_src_hw_if | req_rsp | rsp | 1 | |
cs_aes_halt | entropy_src_pkg::cs_aes_halt | req_rsp | req | 1 | |
entropy_src_rng | entropy_src_pkg::entropy_src_rng | req_rsp | req | 1 | |
entropy_src_xht | entropy_src_pkg::entropy_src_xht | req_rsp | req | 1 | |
otp_en_entropy_src_fw_read | prim_mubi_pkg::mubi8 | uni | rcv | 1 | |
otp_en_entropy_src_fw_over | prim_mubi_pkg::mubi8 | uni | rcv | 1 | |
rng_fips | logic | uni | req | 1 | |
tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts:
Interrupt Name | Type | Description |
---|---|---|
es_entropy_valid | Event | Asserted when entropy source bits are available. |
es_health_test_failed | Event | Asserted when the alert count has been met. |
es_observe_fifo_ready | Event | Asserted when the observe FIFO has filled to the threshold level. |
es_fatal_err | Event | Asserted when a FIFO error occurs, or if an illegal state machine state is reached. |
Security Alerts:
Alert Name | Description |
---|---|
recov_alert | This alert is triggered upon the alert health test threshold criteria not met. |
fatal_alert | This alert triggers for any condition detected in the |
Security Countermeasures:
Countermeasure ID | Description |
---|---|
ENTROPY_SRC.CONFIG.REGWEN | Registers are protected from writes. |
ENTROPY_SRC.CONFIG.MUBI | Registers have multi-bit encoded fields. |
ENTROPY_SRC.CONFIG.REDUN | Threshold register has an inverted copy to compare against. |
ENTROPY_SRC.INTERSIG.MUBI | OTP signal used to enable software access to registers. |
ENTROPY_SRC.MAIN_SM.FSM.SPARSE | The ENTROPY_SRC main state machine uses a sparse state encoding. |
ENTROPY_SRC.ACK_SM.FSM.SPARSE | The ENTROPY_SRC ack state machine uses a sparse state encoding. |
ENTROPY_SRC.RNG.BKGN_CHK | Random number generator is protected with continuous background health checks. |
ENTROPY_SRC.CTR.REDUN | Counter hardening for all health test counters. |
ENTROPY_SRC.CTR.LOCAL_ESC | Redundant counter failures will cause a local escalation to the main state machine. |
ENTROPY_SRC.ESFINAL_RDATA.BUS.CONSISTENCY | Comparison on successive bus values for the post-conditioned entropy seed bus. |
ENTROPY_SRC.TILE_LINK.BUS.INTEGRITY | Tilelink end-to-end bus integrity scheme. |
Registers
Summary | |||
---|---|---|---|
Name | Offset | Length | Description |
entropy_src.INTR_STATE | 0x0 | 4 | Interrupt State Register |
entropy_src.INTR_ENABLE | 0x4 | 4 | Interrupt Enable Register |
entropy_src.INTR_TEST | 0x8 | 4 | Interrupt Test Register |
entropy_src.ALERT_TEST | 0xc | 4 | Alert Test Register |
entropy_src.ME_REGWEN | 0x10 | 4 | Register write enable for module enable register |
entropy_src.SW_REGUPD | 0x14 | 4 | Register write enable for control and threshold registers |
entropy_src.REGWEN | 0x18 | 4 | Register write enable for all control registers |
entropy_src.REV | 0x1c | 4 | Revision register |
entropy_src.MODULE_ENABLE | 0x20 | 4 | Module enable register |
entropy_src.CONF | 0x24 | 4 | Configuration register |
entropy_src.ENTROPY_CONTROL | 0x28 | 4 | Entropy control register |
entropy_src.ENTROPY_DATA | 0x2c | 4 | Entropy data bits |
entropy_src.HEALTH_TEST_WINDOWS | 0x30 | 4 | Health test windows register |
entropy_src.REPCNT_THRESHOLDS | 0x34 | 4 | Repetition count test thresholds register |
entropy_src.REPCNTS_THRESHOLDS | 0x38 | 4 | Repetition count symbol test thresholds register |
entropy_src.ADAPTP_HI_THRESHOLDS | 0x3c | 4 | Adaptive proportion test high thresholds register |
entropy_src.ADAPTP_LO_THRESHOLDS | 0x40 | 4 | Adaptive proportion test low thresholds register |
entropy_src.BUCKET_THRESHOLDS | 0x44 | 4 | Bucket test thresholds register |
entropy_src.MARKOV_HI_THRESHOLDS | 0x48 | 4 | Markov test high thresholds register |
entropy_src.MARKOV_LO_THRESHOLDS | 0x4c | 4 | Markov test low thresholds register |
entropy_src.EXTHT_HI_THRESHOLDS | 0x50 | 4 | External health test high thresholds register |
entropy_src.EXTHT_LO_THRESHOLDS | 0x54 | 4 | External health test low thresholds register |
entropy_src.REPCNT_HI_WATERMARKS | 0x58 | 4 | Repetition count test high watermarks register |
entropy_src.REPCNTS_HI_WATERMARKS | 0x5c | 4 | Repetition count symbol test high watermarks register |
entropy_src.ADAPTP_HI_WATERMARKS | 0x60 | 4 | Adaptive proportion test high watermarks register |
entropy_src.ADAPTP_LO_WATERMARKS | 0x64 | 4 | Adaptive proportion test low watermarks register |
entropy_src.EXTHT_HI_WATERMARKS | 0x68 | 4 | External health test high watermarks register |
entropy_src.EXTHT_LO_WATERMARKS | 0x6c | 4 | External health test low watermarks register |
entropy_src.BUCKET_HI_WATERMARKS | 0x70 | 4 | Bucket test high watermarks register |
entropy_src.MARKOV_HI_WATERMARKS | 0x74 | 4 | Markov test high watermarks register |
entropy_src.MARKOV_LO_WATERMARKS | 0x78 | 4 | Markov test low watermarks register |
entropy_src.REPCNT_TOTAL_FAILS | 0x7c | 4 | Repetition count test failure counter register |
entropy_src.REPCNTS_TOTAL_FAILS | 0x80 | 4 | Repetition count symbol test failure counter register |
entropy_src.ADAPTP_HI_TOTAL_FAILS | 0x84 | 4 | Adaptive proportion high test failure counter register |
entropy_src.ADAPTP_LO_TOTAL_FAILS | 0x88 | 4 | Adaptive proportion low test failure counter register |
entropy_src.BUCKET_TOTAL_FAILS | 0x8c | 4 | Bucket test failure counter register |
entropy_src.MARKOV_HI_TOTAL_FAILS | 0x90 | 4 | Markov high test failure counter register |
entropy_src.MARKOV_LO_TOTAL_FAILS | 0x94 | 4 | Markov low test failure counter register |
entropy_src.EXTHT_HI_TOTAL_FAILS | 0x98 | 4 | External health test high threshold failure counter register |
entropy_src.EXTHT_LO_TOTAL_FAILS | 0x9c | 4 | External health test low threshold failure counter register |
entropy_src.ALERT_THRESHOLD | 0xa0 | 4 | Alert threshold register |
entropy_src.ALERT_SUMMARY_FAIL_COUNTS | 0xa4 | 4 | Alert summary failure counts register |
entropy_src.ALERT_FAIL_COUNTS | 0xa8 | 4 | Alert failure counts register |
entropy_src.EXTHT_FAIL_COUNTS | 0xac | 4 | External health test alert failure counts register |
entropy_src.FW_OV_CONTROL | 0xb0 | 4 | Firmware override control register |
entropy_src.FW_OV_SHA3_START | 0xb4 | 4 | Firmware override sha3 block start control register |
entropy_src.FW_OV_WR_FIFO_FULL | 0xb8 | 4 | Firmware override FIFO write full status register |
entropy_src.FW_OV_RD_FIFO_OVERFLOW | 0xbc | 4 | Firmware override Observe FIFO overflow status |
entropy_src.FW_OV_RD_DATA | 0xc0 | 4 | Firmware override Observe FIFO read register |
entropy_src.FW_OV_WR_DATA | 0xc4 | 4 | Firmware override FIFO write register |
entropy_src.OBSERVE_FIFO_THRESH | 0xc8 | 4 | Observe FIFO threshold register |
entropy_src.OBSERVE_FIFO_DEPTH | 0xcc | 4 | Observe FIFO depth register |
entropy_src.DEBUG_STATUS | 0xd0 | 4 | Debug status register |
entropy_src.RECOV_ALERT_STS | 0xd4 | 4 | Recoverable alert status register |
entropy_src.ERR_CODE | 0xd8 | 4 | Hardware detection of error conditions status register |
entropy_src.ERR_CODE_TEST | 0xdc | 4 | Test error conditions register |
entropy_src.MAIN_SM_STATE | 0xe0 | 4 | Main state machine state debug register |
entropy_src.INTR_STATE @ 0x0
Interrupt State Register Reset default = 0x0, mask 0xf
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x0 | es_entropy_valid | Asserted when entropy source bits are available. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | es_health_test_failed | Asserted when the alert count has been met. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw1c | 0x0 | es_observe_fifo_ready | Asserted when the observe FIFO has filled to the threshold level. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw1c | 0x0 | es_fatal_err | Asserted when a FIFO error occurs, or if an illegal state machine state is reached. |
entropy_src.INTR_ENABLE @ 0x4
Interrupt Enable Register Reset default = 0x0, mask 0xf
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | es_entropy_valid | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | es_health_test_failed | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | es_observe_fifo_ready | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | es_fatal_err | Enable interrupt when |
entropy_src.INTR_TEST @ 0x8
Interrupt Test Register Reset default = 0x0, mask 0xf
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | es_entropy_valid | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | es_health_test_failed | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | wo | 0x0 | es_observe_fifo_ready | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | wo | 0x0 | es_fatal_err | Write 1 to force |
entropy_src.ALERT_TEST @ 0xc
Alert Test Register Reset default = 0x0, mask 0x3
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | recov_alert | Write 1 to trigger one alert event of this kind. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | fatal_alert | Write 1 to trigger one alert event of this kind. |
entropy_src.ME_REGWEN @ 0x10
Register write enable for module enable register Reset default = 0x1, mask 0x1
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | ME_REGWEN | When true, the |
entropy_src.SW_REGUPD @ 0x14
Register write enable for control and threshold registers Reset default = 0x1, mask 0x1
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | SW_REGUPD | When this bit true and the MODULE_ENABLE field is false, the REGWEN write enable bit read as true, and is distributed to all associated control and threshold registers. When false, these registers become read-only. |
entropy_src.REGWEN @ 0x18
Register write enable for all control registers Reset default = 0x1, mask 0x1
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x1 | REGWEN | This read-only write enable bit will allow write access to control and theshold registers that are associated with this bit, but only when the MODULE_ENABLE field is set to kMultiBitBool4False and the SW_REGUPD write enable bit is set to true. When read as false, these registers become read-only. |
entropy_src.REV @ 0x1c
Revision register Reset default = 0x10303, mask 0xffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:0 | ro | 0x3 | ABI_REVISION | Read of this register shows the ABI of this block. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:8 | ro | 0x3 | HW_REVISION | Read of this register shows the revision of this block. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:16 | ro | 0x1 | CHIP_TYPE | Read of this register shows the type of chip using this block. |
entropy_src.MODULE_ENABLE @ 0x20
Module enable register Reset default = 0x9, mask 0xf
Register enable = ME_REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x9 | MODULE_ENABLE | Setting this field to kMultiBitBool4True will enable the ENTROPY_SRC module. Setting this field to kMultiBitBool4False will effectively reset the module. The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details. |
entropy_src.CONF @ 0x24
Configuration register Reset default = 0x909099, mask 0x3f0f0ff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x9 | FIPS_ENABLE | Setting this field to kMultiBitBool4True will enable FIPS qualified entropy to be generated. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | rw | 0x9 | ENTROPY_DATA_REG_ENABLE | Setting this field to kMultiBitBool4True will enable reading entropy values from the ENTROPY_DATA register. This function also requires that the otp_en_entropy_src_fw_read input vector is set to the enable encoding. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:8 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:12 | rw | 0x9 | THRESHOLD_SCOPE | This field controls the scope (either by-line or by-sum) of the health checks. If set to kMultiBitBool4True, the Adaptive Proportion and Markov Tests will accumulate all RNG input lines into a single score, and thresholds will be applied to the sum all the entropy input lines. If set to kMultiBitBool4False, the RNG input lines are all scored individually. A statistical deviation in any one input line, be it due to coincidence or failure, will force rejection of the sample, and count toward the total alert count. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19:16 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:20 | rw | 0x9 | RNG_BIT_ENABLE | Setting this field to kMultiBitBool4True enables the single RNG bit mode, where only one bit is sampled. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
25:24 | rw | 0x0 | RNG_BIT_SEL | When the above bit iset, this field selects which bit from the RNG bus will be processed when in single RNG bit mode. This two bit field selects the RNG bit stream: 0b00: RNG bit 0 0b01: RNG bit 1 0b10: RNG bit 2 0b11: RNG bit 3 |
entropy_src.ENTROPY_CONTROL @ 0x28
Entropy control register Reset default = 0x99, mask 0xff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x9 | ES_ROUTE | Setting this field to kMultiBitBool4True routes the generated entropy value to the ENTROPY_DATA register to be read by firmware. When this field is kMultiBitBool4False, the generated entropy will be forwarded out of this module to the hardware interface. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | rw | 0x9 | ES_TYPE | Setting this field to kMultiBitBool4True will bypass the conditioning logic and bring raw entropy data to the ENTROPY_DATA register. When kMultiBitBool4False, FIPS compliant entropy will be brought the ENTROPY_DATA register, after being conditioned. |
entropy_src.ENTROPY_DATA @ 0x2c
Entropy data bits Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | ENTROPY_DATA | A read of this register provides generated entropy bits to firmware. |
entropy_src.HEALTH_TEST_WINDOWS @ 0x30
Health test windows register Reset default = 0x600200, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x200 | FIPS_WINDOW | This is the window size for all health tests. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. The default value is (2048 bits * 1 clock/4 bits); | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x60 | BYPASS_WINDOW | This is the window size for all health tests when running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. The default value is (384 bits * 1 clock/4 bits); Note that currently only a window size of 384 is supported and tested (this corresponds to the register default value 0x60). Do not use any other values, unless you know what you are doing. |
entropy_src.REPCNT_THRESHOLDS @ 0x34
Repetition count test thresholds register Reset default = 0xffffffff, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0xffff | FIPS_THRESH | This is the threshold size for the repetition count health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xffff | BYPASS_THRESH | This is the threshold size for the repetition count health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. |
entropy_src.REPCNTS_THRESHOLDS @ 0x38
Repetition count symbol test thresholds register Reset default = 0xffffffff, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0xffff | FIPS_THRESH | This is the threshold size for the repetition count symbol health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xffff | BYPASS_THRESH | This is the threshold size for the repetition count symbol health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. |
entropy_src.ADAPTP_HI_THRESHOLDS @ 0x3c
Adaptive proportion test high thresholds register Reset default = 0xffffffff, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0xffff | FIPS_THRESH | This is the threshold size for the adaptive proportion health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xffff | BYPASS_THRESH | This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. |
entropy_src.ADAPTP_LO_THRESHOLDS @ 0x40
Adaptive proportion test low thresholds register Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x0 | FIPS_THRESH | This is the threshold size for the adaptive proportion health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x0 | BYPASS_THRESH | This is the threshold size for the adaptive proportion health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value. |
entropy_src.BUCKET_THRESHOLDS @ 0x44
Bucket test thresholds register Reset default = 0xffffffff, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0xffff | FIPS_THRESH | This is the threshold size for the bucket health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xffff | BYPASS_THRESH | This is the threshold size for the bucket health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. |
entropy_src.MARKOV_HI_THRESHOLDS @ 0x48
Markov test high thresholds register Reset default = 0xffffffff, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0xffff | FIPS_THRESH | This is the threshold size for the Markov health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xffff | BYPASS_THRESH | This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. |
entropy_src.MARKOV_LO_THRESHOLDS @ 0x4c
Markov test low thresholds register Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x0 | FIPS_THRESH | This is the threshold size for the Markov health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x0 | BYPASS_THRESH | This is the threshold size for the Markov health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value. |
entropy_src.EXTHT_HI_THRESHOLDS @ 0x50
External health test high thresholds register Reset default = 0xffffffff, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0xffff | FIPS_THRESH | This is the threshold size for the external health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xffff | BYPASS_THRESH | This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is less than the current value of this register. A read from this register always reflects the current value. |
entropy_src.EXTHT_LO_THRESHOLDS @ 0x54
External health test low thresholds register Reset default = 0x0, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x0 | FIPS_THRESH | This is the threshold size for the external health test. This value is used in normal mode when entropy is being tested in FIPS/CC compliance mode. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0x0 | BYPASS_THRESH | This is the threshold size for the external health test running in bypass mode. This mode is active after reset for the first and only test run, or when this mode is programmed by firmware. This register must be written before the module is enabled. Writing to this register will only update the register if the written value is greater than the current value of this register. A read from this register always reflects the current value. |
entropy_src.REPCNT_HI_WATERMARKS @ 0x58
Repetition count test high watermarks register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_WATERMARK | High watermark value of the REPCNT test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_WATERMARK | High watermark value of the REPCNT test in bypass mode. |
entropy_src.REPCNTS_HI_WATERMARKS @ 0x5c
Repetition count symbol test high watermarks register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_WATERMARK | High watermark value of the REPCNTS test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_WATERMARK | High watermark value of the REPCNTS test in bypass mode. |
entropy_src.ADAPTP_HI_WATERMARKS @ 0x60
Adaptive proportion test high watermarks register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_WATERMARK | High watermark value of the adaptive proportion test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_WATERMARK | High watermark value of the adaptive proportion test in bypass mode. |
entropy_src.ADAPTP_LO_WATERMARKS @ 0x64
Adaptive proportion test low watermarks register Reset default = 0xffffffff, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | 0xffff | FIPS_WATERMARK | Low watermark value of the adaptive proportion test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | 0xffff | BYPASS_WATERMARK | Low watermark value of the adaptive proportion test in bypass mode. |
entropy_src.EXTHT_HI_WATERMARKS @ 0x68
External health test high watermarks register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_WATERMARK | High watermark value of the external health test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_WATERMARK | High watermark value of the external health test in bypass mode. |
entropy_src.EXTHT_LO_WATERMARKS @ 0x6c
External health test low watermarks register Reset default = 0xffffffff, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | 0xffff | FIPS_WATERMARK | Low watermark value of the external health test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | 0xffff | BYPASS_WATERMARK | Low watermark value of the external health test in bypass mode. |
entropy_src.BUCKET_HI_WATERMARKS @ 0x70
Bucket test high watermarks register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_WATERMARK | High watermark value of the bucket test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_WATERMARK | High watermark value of the bucket test in bypass mode. |
entropy_src.MARKOV_HI_WATERMARKS @ 0x74
Markov test high watermarks register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | FIPS_WATERMARK | High watermark value of the Markov test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | x | BYPASS_WATERMARK | High watermark value of the Markov test in bypass mode. |
entropy_src.MARKOV_LO_WATERMARKS @ 0x78
Markov test low watermarks register Reset default = 0xffffffff, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | 0xffff | FIPS_WATERMARK | Low watermark value of the Markov test in FIPS mode. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | ro | 0xffff | BYPASS_WATERMARK | Low watermark value of the Markov test in bypass mode. |
entropy_src.REPCNT_TOTAL_FAILS @ 0x7c
Repetition count test failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | REPCNT_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.REPCNTS_TOTAL_FAILS @ 0x80
Repetition count symbol test failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | REPCNTS_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.ADAPTP_HI_TOTAL_FAILS @ 0x84
Adaptive proportion high test failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | ADAPTP_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.ADAPTP_LO_TOTAL_FAILS @ 0x88
Adaptive proportion low test failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | ADAPTP_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.BUCKET_TOTAL_FAILS @ 0x8c
Bucket test failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | BUCKET_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.MARKOV_HI_TOTAL_FAILS @ 0x90
Markov high test failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MARKOV_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.MARKOV_LO_TOTAL_FAILS @ 0x94
Markov low test failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | MARKOV_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.EXTHT_HI_TOTAL_FAILS @ 0x98
External health test high threshold failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | EXTHT_HI_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.EXTHT_LO_TOTAL_FAILS @ 0x9c
External health test low threshold failure counter register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | EXTHT_LO_TOTAL_FAILS | This register will hold a running count of test failures observed during normal operation. It will persist until cleared. |
entropy_src.ALERT_THRESHOLD @ 0xa0
Alert threshold register Reset default = 0xfffd0002, mask 0xffffffff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw | 0x2 | ALERT_THRESHOLD | This is the threshold size that will signal an alert when value is reached. A value of zero will disable alerts. The default value is 2. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:16 | rw | 0xfffd | ALERT_THRESHOLD_INV | This should be set to the value above, but inverted. |
entropy_src.ALERT_SUMMARY_FAIL_COUNTS @ 0xa4
Alert summary failure counts register Reset default = 0x0, mask 0xffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | ro | x | ANY_FAIL_COUNT | This field will hold a running count of
the total alert count, which is a sum of all of the other
counters in the |
entropy_src.ALERT_FAIL_COUNTS @ 0xa8
Alert failure counts register Reset default = 0x0, mask 0xfffffff0
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | ro | x | REPCNT_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:8 | ro | x | ADAPTP_HI_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:12 | ro | x | ADAPTP_LO_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19:16 | ro | x | BUCKET_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23:20 | ro | x | MARKOV_HI_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:24 | ro | x | MARKOV_LO_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:28 | ro | x | REPCNTS_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. |
entropy_src.EXTHT_FAIL_COUNTS @ 0xac
External health test alert failure counts register Reset default = 0x0, mask 0xff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | ro | x | EXTHT_HI_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | ro | x | EXTHT_LO_FAIL_COUNT | This field will hold a running count of test failures that contribute to the total alert count. It will be reset after every passing test sequence. If an alert is signaled, this value will persist until it is cleared. |
entropy_src.FW_OV_CONTROL @ 0xb0
Firmware override control register Reset default = 0x99, mask 0xff
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x9 | FW_OV_MODE | Setting this field to kMultiBitBool4True will put the entropy flow in firmware override mode. In this mode, firmware can monitor the post-health test entropy by reading the observe FIFO. This function also requires that the otp_en_entropy_src_fw_over input vector is set to the enable encoding. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | rw | 0x9 | FW_OV_ENTROPY_INSERT | Setting this field to kMultiBitBool4True will switch the input into the pre-conditioner
packer FIFO. Firmware can directly write into the packer FIFO, enabling
the ability to insert entropy bits back into the hardware flow. Firmware
can read data from the health check packer FIFO, then do optional health
checks or optional conditioning, then insert the results back into the flow.
Also, the |
entropy_src.FW_OV_SHA3_START @ 0xb4
Firmware override sha3 block start control register Reset default = 0x9, mask 0xf
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x9 | FW_OV_INSERT_START | Setting this field to kMultiBitBool4True will instruct the ENTROPY_SRC main state machine to start the SHA3 process and be ready to accept entropy data. This field should be set prior to writting the FW_OV_WR_DATA register. Once all data has been written, this field should be set to kMultiBitBool4False. Once that happened, the SHA3 block will finish processing and push the result into the ESFINAL FIFO. Note that clearing this bit to kMultiBitBool4False while there is still unprocessed
entropy in the |
entropy_src.FW_OV_WR_FIFO_FULL @ 0xb8
Firmware override FIFO write full status register Reset default = 0x0, mask 0x1
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | x | FW_OV_WR_FIFO_FULL | "When this bit is clear, writes to the FW_OV_WR_DATA register are allowed. If this bit is set, it is the equivalent to a FIFO full condition, and writes to the FW_OV_WR_DATA register must be delayed until this bit is reset. |
entropy_src.FW_OV_RD_FIFO_OVERFLOW @ 0xbc
Firmware override Observe FIFO overflow status Reset default = 0x0, mask 0x1
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x0 | FW_OV_RD_FIFO_OVERFLOW | This bit is set by hardware whenever RNG data is lost due to an overflow condition
in the Observe FIFO. The RNG data rate is slow enough that firmware should always
be able to keep up. This register meanwhile provides an additional check to confirm
that bytes read from the |
entropy_src.FW_OV_RD_DATA @ 0xc0
Firmware override Observe FIFO read register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | FW_OV_RD_DATA | A read of this register pops and returns the top of the Observe FIFO. |
entropy_src.FW_OV_WR_DATA @ 0xc4
Firmware override FIFO write register Reset default = 0x0, mask 0xffffffff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | FW_OV_WR_DATA | A write to this register will insert entropy back into the entropy source
module flow. Both |
entropy_src.OBSERVE_FIFO_THRESH @ 0xc8
Observe FIFO threshold register Reset default = 0x20, mask 0x7f
Register enable = REGWEN |
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | rw | 0x20 | OBSERVE_FIFO_THRESH | This field will set the threshold that the depth of the Observe FIFO will be compared with when setting the interrupt status bit. Note: a value of zero is reserved and not to be used. |
entropy_src.OBSERVE_FIFO_DEPTH @ 0xcc
Observe FIFO depth register Reset default = 0x0, mask 0x7f
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6:0 | ro | x | OBSERVE_FIFO_DEPTH | This field will hold the current depth of the Observe FIFO. |
entropy_src.DEBUG_STATUS @ 0xd0
Debug status register Reset default = 0x10000, mask 0x303ff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2:0 | ro | x | ENTROPY_FIFO_DEPTH | This is the depth of the entropy source FIFO. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5:3 | ro | x | SHA3_FSM | This is the SHA3 finite state machine current state. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | ro | x | SHA3_BLOCK_PR | This is the SHA3 block processed signal current state. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | ro | x | SHA3_SQUEEZING | This is the SHA3 squeezing signal current state. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | ro | x | SHA3_ABSORBED | This is the SHA3 absorbed signal current state. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | ro | x | SHA3_ERR | This is a logic-or of all of the SHA3 error signals. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:10 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | ro | 0x1 | MAIN_SM_IDLE | The entropy_src main state machine is in the idle state. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
17 | ro | x | MAIN_SM_BOOT_DONE | The entropy_src main state machine is in the boot phase done state. |
entropy_src.RECOV_ALERT_STS @ 0xd4
Recoverable alert status register Reset default = 0x0, mask 0x1ffaf
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x0 | FIPS_ENABLE_FIELD_ALERT | This bit is set when the FIPS_ENABLE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw0c | 0x0 | ENTROPY_DATA_REG_EN_FIELD_ALERT | This bit is set when the ENTROPY_DATA_REG_ENABLE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw0c | 0x0 | MODULE_ENABLE_FIELD_ALERT | This bit is set when the MODULE_ENABLE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw0c | 0x0 | THRESHOLD_SCOPE_FIELD_ALERT | This bit is set when the THRESHOLD_SCOPE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | rw0c | 0x0 | RNG_BIT_ENABLE_FIELD_ALERT | This bit is set when the RNG_BIT_ENABLE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | rw0c | 0x0 | FW_OV_SHA3_START_FIELD_ALERT | This bit is set when the FW_OV_SHA3_START field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | rw0c | 0x0 | FW_OV_MODE_FIELD_ALERT | This bit is set when the FW_OV_MODE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | rw0c | 0x0 | FW_OV_ENTROPY_INSERT_FIELD_ALERT | This bit is set when the FW_OV_ENTROPY_INSERT field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | rw0c | 0x0 | ES_ROUTE_FIELD_ALERT | This bit is set when the ES_ROUTE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | rw0c | 0x0 | ES_TYPE_FIELD_ALERT | This bit is set when the ES_TYPE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | rw0c | 0x0 | ES_MAIN_SM_ALERT | This bit is set when the main state machine detects a threshhold failure state. Writing a zero resets this status bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 | rw0c | 0x0 | ES_BUS_CMP_ALERT | This bit is set when the interal entropy bus value is equal to the prior valid value on the bus, indicating a possible attack. Writing a zero resets this status bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14 | rw0c | 0x0 | ES_THRESH_CFG_ALERT | This bit is set when the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | rw0c | 0x0 | ES_FW_OV_WR_ALERT | This bit is set when the packer FIFO has been written but was full at the time,
and in both FW_OV_MODE and FW_OV_ENTROPY_INSERT modes.
This alert would normally be the result of not monitoring the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
16 | rw0c | 0x0 | ES_FW_OV_DISABLE_ALERT | This bit is set when |
entropy_src.ERR_CODE @ 0xd8
Hardware detection of error conditions status register Reset default = 0x0, mask 0x71f00007
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x0 | SFIFO_ESRNG_ERR | This bit will be set to one when an error has been detected for the esrng FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | 0x0 | SFIFO_OBSERVE_ERR | This bit will be set to one when an error has been detected for the observe FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | ro | 0x0 | SFIFO_ESFINAL_ERR | This bit will be set to one when an error has been detected for the esfinal FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19:3 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
20 | ro | 0x0 | ES_ACK_SM_ERR | This bit will be set to one when an illegal state has been detected for the ES ack stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
21 | ro | 0x0 | ES_MAIN_SM_ERR | This bit will be set to one when an illegal state has been detected for the ES main stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
22 | ro | 0x0 | ES_CNTR_ERR | This bit will be set to one when a hardened counter has detected an error condition. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23 | ro | 0x0 | SHA3_STATE_ERR | This bit will be set to one when a SHA3 state error has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
24 | ro | 0x0 | SHA3_RST_STORAGE_ERR | This bit will be set to one when a SHA3_RST_STORAGE_ERR signal being active has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:25 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28 | ro | 0x0 | FIFO_WRITE_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any full FIFO that has been recieved a write pulse. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29 | ro | 0x0 | FIFO_READ_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any empty FIFO that has recieved a read pulse. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | ro | 0x0 | FIFO_STATE_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any FIFO where both the empty and full status bits are set. This bit will stay set until the next reset. |
entropy_src.ERR_CODE_TEST @ 0xdc
Test error conditions register Reset default = 0x0, mask 0x1f
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | ERR_CODE_TEST | Setting this field will set the bit number for which an error
will be forced in the hardware. This bit number is that same one
found in the |
entropy_src.MAIN_SM_STATE @ 0xe0
Main state machine state debug register Reset default = 0xf5, mask 0x1ff
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8:0 | ro | 0xf5 | MAIN_SM_STATE | This is the state of the ENTROPY_SRC main state machine.
See the RTL file |