Hardware Interfaces and Registers
Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module edn
has the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: none
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO: none
Inter-Module Signals: Reference
Port Name | Package::Struct | Type | Act | Width | Description |
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csrng_cmd | csrng_pkg::csrng | req_rsp | req | 1 | EDN supports a signal CSRNG application interface. |
edn | edn_pkg::edn | req_rsp | rsp | 8 | The collection of peripheral ports supported by edn. The width (4) indicates the number of peripheral ports on a single instance. Due to limitations in the parametrization of top-level interconnects this value is not currently parameterizable. However, the number of peripheral ports may change in a future revision. |
tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts:
Interrupt Name | Type | Description |
---|---|---|
edn_cmd_req_done | Event | Asserted when a software CSRNG request has completed. |
edn_fatal_err | Event | Asserted when a FIFO error occurs. |
Security Alerts:
Alert Name | Description |
---|---|
recov_alert | This alert is triggered when entropy bus data matches on consecutive clock cycles. |
fatal_alert | This alert triggers (i) if an illegal state machine state is reached, or (ii) if a fatal integrity failure is detected on the TL-UL bus. |
Security Countermeasures:
Countermeasure ID | Description |
---|---|
EDN.CONFIG.REGWEN | Registers are protected from writes. |
EDN.CONFIG.MUBI | Registers have multi-bit encoded fields. |
EDN.MAIN_SM.FSM.SPARSE | The EDN main state machine uses a sparse state encoding. |
EDN.ACK_SM.FSM.SPARSE | The EDN ACK state machine uses a sparse state encoding. |
EDN.CTR.REDUN | Counter hardening on the generate command maximum requests counter. |
EDN.MAIN_SM.CTR.LOCAL_ESC | A mismatch detected inside any EDN counter moves the main state machine into a terminal error state. |
EDN.CS_RDATA.BUS.CONSISTENCY | Comparison on successive bus values for genbits returned from csrng that will distribute over the endpoint buses. |
EDN.TILE_LINK.BUS.INTEGRITY | Tilelink end-to-end bus integrity scheme. |
Registers
Summary | |||
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Name | Offset | Length | Description |
edn.INTR_STATE | 0x0 | 4 | Interrupt State Register |
edn.INTR_ENABLE | 0x4 | 4 | Interrupt Enable Register |
edn.INTR_TEST | 0x8 | 4 | Interrupt Test Register |
edn.ALERT_TEST | 0xc | 4 | Alert Test Register |
edn.REGWEN | 0x10 | 4 | Register write enable for all control registers |
edn.CTRL | 0x14 | 4 | EDN control register |
edn.BOOT_INS_CMD | 0x18 | 4 | EDN boot instantiate command register |
edn.BOOT_GEN_CMD | 0x1c | 4 | EDN boot generate command register |
edn.SW_CMD_REQ | 0x20 | 4 | EDN csrng app command request register |
edn.SW_CMD_STS | 0x24 | 4 | EDN command status register |
edn.RESEED_CMD | 0x28 | 4 | EDN csrng reseed command register |
edn.GENERATE_CMD | 0x2c | 4 | EDN csrng generate command register |
edn.MAX_NUM_REQS_BETWEEN_RESEEDS | 0x30 | 4 | EDN maximum number of requests between reseeds register |
edn.RECOV_ALERT_STS | 0x34 | 4 | Recoverable alert status register |
edn.ERR_CODE | 0x38 | 4 | Hardware detection of fatal error conditions status register |
edn.ERR_CODE_TEST | 0x3c | 4 | Test error conditions register |
edn.MAIN_SM_STATE | 0x40 | 4 | Main state machine state debug register |
edn.INTR_STATE @ 0x0
Interrupt State Register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x0 | edn_cmd_req_done | Asserted when a software CSRNG request has completed. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | edn_fatal_err | Asserted when a FIFO error occurs. |
edn.INTR_ENABLE @ 0x4
Interrupt Enable Register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | edn_cmd_req_done | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | edn_fatal_err | Enable interrupt when |
edn.INTR_TEST @ 0x8
Interrupt Test Register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | edn_cmd_req_done | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | edn_fatal_err | Write 1 to force |
edn.ALERT_TEST @ 0xc
Alert Test Register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | recov_alert | Write 1 to trigger one alert event of this kind. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | fatal_alert | Write 1 to trigger one alert event of this kind. |
edn.REGWEN @ 0x10
Register write enable for all control registers Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | REGWEN | When true, the CTRL can be written by software. When false, this field read-only. Defaults true, write zero to clear. Note that this needs to be cleared after initial configuration at boot in order to lock in the listed register settings. |
edn.CTRL @ 0x14
EDN control register Reset default = 0x9999, mask 0xffff
Register enable = REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x9 | EDN_ENABLE | Setting this field to kMultiBitBool4True enables the EDN module. The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | rw | 0x9 | BOOT_REQ_MODE | Setting this field to kMultiBitBool4True will enable the feature where the EDN block will automatically send a boot-time request to the CSRNG application interface. The purpose of this feature is to request entropy as fast as possible after reset, and during chip boot-time. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:8 | rw | 0x9 | AUTO_REQ_MODE | Setting this field to kMultiBitBool4True will enable the EDN block to automatically
send another request to CSRNG application interface. It is assumed that a CSRNG
instantiate command will be issued using the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:12 | rw | 0x9 | CMD_FIFO_RST | Setting this field to kMultiBitBool4True clears the two command FIFOs: the RESEED_CMD FIFO and the GENERATE_CMD FIFO. This field must be set to the reset state by software before any further commands can be issued to these FIFOs. |
edn.BOOT_INS_CMD @ 0x18
EDN boot instantiate command register Reset default = 0x901, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x901 | BOOT_INS_CMD | This field is used as the value for Instantiate command at boot time. |
edn.BOOT_GEN_CMD @ 0x1c
EDN boot generate command register Reset default = 0xfff003, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0xfff003 | BOOT_GEN_CMD | This field is used as the value for generate command at boot time. |
edn.SW_CMD_REQ @ 0x20
EDN csrng app command request register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | SW_CMD_REQ | Any CSRNG action can be initiated by writing a CSRNG command to this register. The application interface must wait for the "ack" to return before issuing new commands. This interface is intended to be controlled solely by software. If |
edn.SW_CMD_STS @ 0x24
EDN command status register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x0 | CMD_RDY | This bit indicates when the command interface is ready to accept commands. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | 0x0 | CMD_STS | This one bit field is the status code returned with the application command ack. It is updated each time a command ack is asserted on the CSRNG interface. 0b0: Request completed successfully 0b1: Request completed with an error |
edn.RESEED_CMD @ 0x28
EDN csrng reseed command register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | RESEED_CMD | Writing this register will fill a FIFO with up to 13 command words (32b words).
This FIFO will be used to automatically send out a reseed command to the CSRNG
application interface when in If more than 13 entires are written to the FIFO, the design will automatically generate a fatal alert. Note that CSRNG command format details can be found in the CSRNG documentation. |
edn.GENERATE_CMD @ 0x2c
EDN csrng generate command register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | x | GENERATE_CMD | Writing this register will fill a FIFO with up to 13 command words (32b words).
This FIFO will be used to automatically send out a generate command to the CSRNG
appl interface when in If more than 13 entires are written to the FIFO, the design will automatically generate a fatal alert. Note that CSRNG command format details can be found in the CSRNG documentation. |
edn.MAX_NUM_REQS_BETWEEN_RESEEDS @ 0x30
EDN maximum number of requests between reseeds register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | rw | 0x0 | MAX_NUM_REQS_BETWEEN_RESEEDS | Setting this field will set the number of generate requests that can be made
to CSRNG before a reseed request is made. This value only has meaning when in
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edn.RECOV_ALERT_STS @ 0x34
Recoverable alert status register Reset default = 0x0, mask 0x100f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x0 | EDN_ENABLE_FIELD_ALERT | This bit is set when the EDN_ENABLE field is set to an illegal value, something other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw0c | 0x0 | BOOT_REQ_MODE_FIELD_ALERT | This bit is set when the BOOT_REQ_MODE field is set to an illegal value, something other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw0c | 0x0 | AUTO_REQ_MODE_FIELD_ALERT | This bit is set when the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw0c | 0x0 | CMD_FIFO_RST_FIELD_ALERT | This bit is set when the CMD_FIFO_RST field is set to an illegal value, something other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:4 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | rw0c | 0x0 | EDN_BUS_CMP_ALERT | This bit is set when the interal entropy bus value is equal to the prior valid value on the bus, indicating a possible attack. Writing a zero resets this status bit. |
edn.ERR_CODE @ 0x38
Hardware detection of fatal error conditions status register Reset default = 0x0, mask 0x70700007
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x0 | SFIFO_RESCMD_ERR | This bit will be set to one when an error has been detected for the reseed command FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). When this bit is set, a fatal error condition will result. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | 0x0 | SFIFO_GENCMD_ERR | This bit will be set to one when an error has been detected for the generate command FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). When this bit is set, a fatal error condition will result. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | ro | 0x0 | SFIFO_OUTPUT_ERR | This bit will be set to one when an error has been detected for the output FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). When this bit is set, a fatal error condition will result. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19:3 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
20 | ro | 0x0 | EDN_ACK_SM_ERR | This bit will be set to one when an illegal state has been detected for the EDN ack stage state machine. This error will signal a fatal alert. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
21 | ro | 0x0 | EDN_MAIN_SM_ERR | This bit will be set to one when an illegal state has been detected for the EDN main stage state machine. This error will signal a fatal alert. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
22 | ro | 0x0 | EDN_CNTR_ERR | This bit will be set to one when a hardened counter has detected an error condition. This error will signal a fatal alert. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27:23 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28 | ro | 0x0 | FIFO_WRITE_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any full FIFO that has been recieved a write pulse. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29 | ro | 0x0 | FIFO_READ_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any empty FIFO that has recieved a read pulse. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | ro | 0x0 | FIFO_STATE_ERR | This bit will be set to one when any of the source bits (bits 0 through 1 of this this register) are asserted as a result of an error pulse generated from any FIFO where both the empty and full status bits are set. This bit will stay set until the next reset. |
edn.ERR_CODE_TEST @ 0x3c
Test error conditions register Reset default = 0x0, mask 0x1f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | ERR_CODE_TEST | Setting this field will set the bit number for which an error
will be forced in the hardware. This bit number is that same one
found in the |
edn.MAIN_SM_STATE @ 0x40
Main state machine state debug register Reset default = 0x185, mask 0x1ff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8:0 | ro | 0x185 | MAIN_SM_STATE | This is the state of the EDN main state machine.
See the RTL file |