Hardware Interfaces and Registers
Interfaces
Referring to the Comportable guideline for peripheral device functionality, the module csrng
has the following hardware interfaces defined.
Primary Clock: clk_i
Other Clocks: none
Bus Device Interfaces (TL-UL): tl
Bus Host Interfaces (TL-UL): none
Peripheral Pins for Chip IO: none
Inter-Module Signals: Reference
Port Name | Package::Struct | Type | Act | Width | Description |
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csrng_cmd | csrng_pkg::csrng | req_rsp | rsp | 2 | |
entropy_src_hw_if | entropy_src_pkg::entropy_src_hw_if | req_rsp | req | 1 | |
cs_aes_halt | entropy_src_pkg::cs_aes_halt | req_rsp | rsp | 1 | |
otp_en_csrng_sw_app_read | prim_mubi_pkg::mubi8 | uni | rcv | 1 | |
lc_hw_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
tl | tlul_pkg::tl | req_rsp | rsp | 1 |
Interrupts:
Interrupt Name | Type | Description |
---|---|---|
cs_cmd_req_done | Event | Asserted when a command request is completed. |
cs_entropy_req | Event | Asserted when a request for entropy has been made. |
cs_hw_inst_exc | Event | Asserted when a hardware-attached CSRNG instance encounters a command exception |
cs_fatal_err | Event | Asserted when a FIFO error or a fatal alert occurs. Check the |
Security Alerts:
Alert Name | Description |
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recov_alert | This alert is triggered when a recoverable alert occurs. Check the |
fatal_alert | This alert triggers (i) if an illegal state machine state is reached, or (ii) if an AES fatal alert condition occurs, or (iii) if a fatal integrity failure is detected on the TL-UL bus. |
Security Countermeasures:
Countermeasure ID | Description |
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CSRNG.CONFIG.REGWEN | Registers are protected from writes. |
CSRNG.CONFIG.MUBI | Registers have multi-bit encoded fields. |
CSRNG.INTERSIG.MUBI | OTP signal used to enable software access to registers. |
CSRNG.MAIN_SM.FSM.SPARSE | The CSRNG main state machine uses a sparse state encoding. |
CSRNG.UPDATE.FSM.SPARSE | The CSRNG update state machine uses a sparse state encoding. |
CSRNG.BLK_ENC.FSM.SPARSE | The CSRNG block encrypt state machine uses a sparse state encoding. |
CSRNG.OUTBLK.FSM.SPARSE | The CSRNG block output state machine uses a sparse state encoding. |
CSRNG.GEN_CMD.CTR.REDUN | The generate command uses a counter that is protected by a second counter that counts in the opposite direction. |
CSRNG.DRBG_UPD.CTR.REDUN | The ctr_drbg update algorthm uses a counter that is protected by a second counter that counts in the opposite direction. |
CSRNG.DRBG_GEN.CTR.REDUN | The ctr_drbg generate algorthm uses a counter that is protected by a second counter that counts in the opposite direction. |
CSRNG.CTRL.MUBI | Multi-bit field used for selection control. |
CSRNG.MAIN_SM.CTR.LOCAL_ESC | A mismatch detected inside any CSRNG counter moves the main state machine into a terminal error state. |
CSRNG.CONSTANTS.LC_GATED | Seed diversification based on the lifecycle state. |
CSRNG.SW_GENBITS.BUS.CONSISTENCY | Comparison on successive bus values for genbits returned on the software channel. |
CSRNG.TILE_LINK.BUS.INTEGRITY | Tilelink end-to-end bus integrity scheme. |
CSRNG.AES_CIPHER.FSM.SPARSE | The AES cipher core FSM uses a sparse state encoding. See the AES module documentation for AES-specific countermeasures. |
CSRNG.AES_CIPHER.FSM.REDUN | The AES cipher core FSM uses multiple, independent logic rails. See the AES module documentation for AES-specific countermeasures. |
CSRNG.AES_CIPHER.CTRL.SPARSE | Critical control signals for the AES cipher core such as handshake and MUX control signals use sparse encodings. See the AES module documentation for AES-specific countermeasures. |
CSRNG.AES_CIPHER.FSM.LOCAL_ESC | The AES cipher core FSM moves to a terminal error state upon local escalation. Can be triggered by AES_CIPHER.FSM.SPARSE, AES_CIPHER.FSM.REDUN, AES_CIPHER.CTR.REDUN and AES_CIPHER.CTRL.SPARSE. See the AES module documentation for AES-specific countermeasures. |
CSRNG.AES_CIPHER.CTR.REDUN | The AES round counter inside the AES cipher core FSM is protected with multiple, independent logic rails. See the AES module documentation for AES-specific countermeasures. |
CSRNG.AES_CIPHER.DATA_REG.LOCAL_ESC | Upon local escalation, the AES cipher core doesn't output intermediate state. See the AES module documentation for AES-specific countermeasures. |
Registers
Summary | |||
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Name | Offset | Length | Description |
csrng.INTR_STATE | 0x0 | 4 | Interrupt State Register |
csrng.INTR_ENABLE | 0x4 | 4 | Interrupt Enable Register |
csrng.INTR_TEST | 0x8 | 4 | Interrupt Test Register |
csrng.ALERT_TEST | 0xc | 4 | Alert Test Register |
csrng.REGWEN | 0x10 | 4 | Register write enable for all control registers |
csrng.CTRL | 0x14 | 4 | Control register |
csrng.CMD_REQ | 0x18 | 4 | Command request register |
csrng.SW_CMD_STS | 0x1c | 4 | Application interface command status register |
csrng.GENBITS_VLD | 0x20 | 4 | Generate bits returned valid register |
csrng.GENBITS | 0x24 | 4 | Generate bits returned register |
csrng.INT_STATE_NUM | 0x28 | 4 | Internal state number register |
csrng.INT_STATE_VAL | 0x2c | 4 | Internal state read access register |
csrng.HW_EXC_STS | 0x30 | 4 | Hardware instance exception status register |
csrng.RECOV_ALERT_STS | 0x34 | 4 | Recoverable alert status register |
csrng.ERR_CODE | 0x38 | 4 | Hardware detection of error conditions status register |
csrng.ERR_CODE_TEST | 0x3c | 4 | Test error conditions register |
csrng.MAIN_SM_STATE | 0x40 | 4 | Main state machine state debug register |
csrng.INTR_STATE @ 0x0
Interrupt State Register Reset default = 0x0, mask 0xf
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw1c | 0x0 | cs_cmd_req_done | Asserted when a command request is completed. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw1c | 0x0 | cs_entropy_req | Asserted when a request for entropy has been made. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw1c | 0x0 | cs_hw_inst_exc | Asserted when a hardware-attached CSRNG instance encounters a command exception | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw1c | 0x0 | cs_fatal_err | Asserted when a FIFO error or a fatal alert occurs. Check the |
csrng.INTR_ENABLE @ 0x4
Interrupt Enable Register Reset default = 0x0, mask 0xf
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw | 0x0 | cs_cmd_req_done | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw | 0x0 | cs_entropy_req | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw | 0x0 | cs_hw_inst_exc | Enable interrupt when | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw | 0x0 | cs_fatal_err | Enable interrupt when |
csrng.INTR_TEST @ 0x8
Interrupt Test Register Reset default = 0x0, mask 0xf
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | cs_cmd_req_done | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | cs_entropy_req | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | wo | 0x0 | cs_hw_inst_exc | Write 1 to force | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | wo | 0x0 | cs_fatal_err | Write 1 to force |
csrng.ALERT_TEST @ 0xc
Alert Test Register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | wo | 0x0 | recov_alert | Write 1 to trigger one alert event of this kind. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | wo | 0x0 | fatal_alert | Write 1 to trigger one alert event of this kind. |
csrng.REGWEN @ 0x10
Register write enable for all control registers Reset default = 0x1, mask 0x1
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x1 | REGWEN | When true, all writeable registers can be modified. When false, they become read-only. |
csrng.CTRL @ 0x14
Control register Reset default = 0x999, mask 0xfff
Register enable = REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x9 | ENABLE | Setting this field to kMultiBitBool4True will enable the CSRNG module. The modules of the entropy complex may only be enabled and disabled in a specific order, see Programmers Guide for details. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:4 | rw | 0x9 | SW_APP_ENABLE | Setting this field to kMultiBitBool4True will enable reading from the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:8 | rw | 0x9 | READ_INT_STATE | Setting this field to kMultiBitBool4True will enable reading from the |
csrng.CMD_REQ @ 0x18
Command request register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | wo | 0x0 | CMD_REQ | Writing this request with defined CSRNG commands will initiate all possible CSRNG actions. The application interface must wait for the "ack" to return before issuing new commands. |
csrng.SW_CMD_STS @ 0x1c
Application interface command status register Reset default = 0x1, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x1 | CMD_RDY | This bit indicates when the command interface is ready to accept commands. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | 0x0 | CMD_STS | This one bit field is the status code returned with the application command ack. It is updated each time a command ack is asserted on the internal application interface for software use. 0b0: Request completed successfully 0b1: Request completed with an error |
csrng.GENBITS_VLD @ 0x20
Generate bits returned valid register Reset default = 0x0, mask 0x3
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | x | GENBITS_VLD | This bit is set when genbits are available on this application interface. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | x | GENBITS_FIPS | This bit is set when genbits are FIPS/CC compliant. |
csrng.GENBITS @ 0x24
Generate bits returned register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | GENBITS | Reading this register will get the generated bits that were requested with
the generate request. This register must be four times for each request
number made. For example, a application command generate request with
a |
csrng.INT_STATE_NUM @ 0x28
Internal state number register Reset default = 0x0, mask 0xf
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3:0 | rw | 0x0 | INT_STATE_NUM | Setting this field will set the number for which internal state can be
selected for a read access. Up to 16 internal state values can be chosen
from this register. The actual number of valid internal state fields
is set by parameter NHwApps plus 1 software app. For those selections that point
to reserved locations (greater than NHwApps plus 1), the returned value
will be zero. Writing this register will also reset the internal read
pointer for the |
csrng.INT_STATE_VAL @ 0x2c
Internal state read access register Reset default = 0x0, mask 0xffffffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
31:0 | ro | x | INT_STATE_VAL | Reading this register will dump out the contents of the selected internal state field.
Since the internal state field is 448 bits wide, it will require 14 reads from this
register to gather the entire field. Once 14 reads have been done, the internal read
pointer (selects 32 bits of the 448 bit field) will reset to zero. The |
csrng.HW_EXC_STS @ 0x30
Hardware instance exception status register Reset default = 0x0, mask 0xffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15:0 | rw0c | 0x0 | HW_EXC_STS | Reading this register indicates whether one of the CSRNG HW instances has
encountered an exception. Each bit corresponds to a particular hardware
instance, with bit 0 corresponding to instance HW0, bit 1 corresponding
to instance HW1, and so forth. (To monitor the status of requests made
to the SW instance, check the |
csrng.RECOV_ALERT_STS @ 0x34
Recoverable alert status register Reset default = 0x0, mask 0x300f
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | rw0c | 0x0 | ENABLE_FIELD_ALERT | This bit is set when the ENABLE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | rw0c | 0x0 | SW_APP_ENABLE_FIELD_ALERT | This bit is set when the SW_APP_ENABLE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | rw0c | 0x0 | READ_INT_STATE_FIELD_ALERT | This bit is set when the READ_INT_STATE field in the | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | rw0c | 0x0 | ACMD_FLAG0_FIELD_ALERT | This bit is set when the FLAG0 field in the Application Command is set to a value other than kMultiBitBool4True or kMultiBitBool4False. Writing a zero resets this status bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11:4 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | rw0c | 0x0 | CS_BUS_CMP_ALERT | This bit is set when the software application port genbits bus value is equal to the prior valid value on the bus, indicating a possible attack. Writing a zero resets this status bit. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 | rw0c | 0x0 | CS_MAIN_SM_ALERT | This bit is set when an unsupported/illegal CSRNG command is being processed. The main FSM will hang unless the module enable field is set to the disabled state. |
csrng.ERR_CODE @ 0x38
Hardware detection of error conditions status register Reset default = 0x0, mask 0x77f0ffff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
0 | ro | 0x0 | SFIFO_CMD_ERR | This bit will be set to one when an error has been detected for the command stage command FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
1 | ro | 0x0 | SFIFO_GENBITS_ERR | This bit will be set to one when an error has been detected for the command stage genbits FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
2 | ro | 0x0 | SFIFO_CMDREQ_ERR | This bit will be set to one when an error has been detected for the cmdreq FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
3 | ro | 0x0 | SFIFO_RCSTAGE_ERR | This bit will be set to one when an error has been detected for the rcstage FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4 | ro | 0x0 | SFIFO_KEYVRC_ERR | This bit will be set to one when an error has been detected for the keyvrc FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
5 | ro | 0x0 | SFIFO_UPDREQ_ERR | This bit will be set to one when an error has been detected for the updreq FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
6 | ro | 0x0 | SFIFO_BENCREQ_ERR | This bit will be set to one when an error has been detected for the bencreq FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7 | ro | 0x0 | SFIFO_BENCACK_ERR | This bit will be set to one when an error has been detected for the bencack FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
8 | ro | 0x0 | SFIFO_PDATA_ERR | This bit will be set to one when an error has been detected for the pdata FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9 | ro | 0x0 | SFIFO_FINAL_ERR | This bit will be set to one when an error has been detected for the final FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
10 | ro | 0x0 | SFIFO_GBENCACK_ERR | This bit will be set to one when an error has been detected for the gbencack FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
11 | ro | 0x0 | SFIFO_GRCSTAGE_ERR | This bit will be set to one when an error has been detected for the grcstage FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
12 | ro | 0x0 | SFIFO_GGENREQ_ERR | This bit will be set to one when an error has been detected for the ggenreq FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
13 | ro | 0x0 | SFIFO_GADSTAGE_ERR | This bit will be set to one when an error has been detected for the gadstage FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
14 | ro | 0x0 | SFIFO_GGENBITS_ERR | This bit will be set to one when an error has been detected for the ggenbits FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
15 | ro | 0x0 | SFIFO_BLKENC_ERR | This bit will be set to one when an error has been detected for the blkenc FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
19:16 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
20 | ro | 0x0 | CMD_STAGE_SM_ERR | This bit will be set to one when an illegal state has been detected for the command stage state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
21 | ro | 0x0 | MAIN_SM_ERR | This bit will be set to one when an illegal state has been detected for the main state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
22 | ro | 0x0 | DRBG_GEN_SM_ERR | This bit will be set to one when an illegal state has been detected for the ctr_drbg gen state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
23 | ro | 0x0 | DRBG_UPDBE_SM_ERR | This bit will be set to one when an illegal state has been detected for the ctr_drbg update block encode state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
24 | ro | 0x0 | DRBG_UPDOB_SM_ERR | This bit will be set to one when an illegal state has been detected for the ctr_drbg update out block state machine. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
25 | ro | 0x0 | AES_CIPHER_SM_ERR | This bit will be set to one when an AES fatal error has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
26 | ro | 0x0 | CMD_GEN_CNT_ERR | This bit will be set to one when a mismatch in any of the hardened counters has been detected. This error will signal a fatal alert, and also an interrupt if enabled. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
27 | Reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
28 | ro | 0x0 | FIFO_WRITE_ERR | This bit will be set to one when any of the source bits (bits 0 through 15 of this this register) are asserted as a result of an error pulse generated from any full FIFO that has been recieved a write pulse. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
29 | ro | 0x0 | FIFO_READ_ERR | This bit will be set to one when any of the source bits (bits 0 through 15 of this this register) are asserted as a result of an error pulse generated from any empty FIFO that has recieved a read pulse. This bit will stay set until the next reset. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
30 | ro | 0x0 | FIFO_STATE_ERR | This bit will be set to one when any of the source bits (bits 0 through 15 of this this register) are asserted as a result of an error pulse generated from any FIFO where both the empty and full status bits are set. This bit will stay set until the next reset. |
csrng.ERR_CODE_TEST @ 0x3c
Test error conditions register Reset default = 0x0, mask 0x1f
Register enable = REGWEN |
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
4:0 | rw | 0x0 | ERR_CODE_TEST | Setting this field will set the bit number for which an error
will be forced in the hardware. This bit number is that same one
found in the |
csrng.MAIN_SM_STATE @ 0x40
Main state machine state debug register Reset default = 0x4e, mask 0xff
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Bits | Type | Reset | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
7:0 | ro | 0x4e | MAIN_SM_STATE | This is the state of the CSRNG main state machine.
See the RTL file |