Hardware Interfaces and Registers

Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module aon_timer has the following hardware interfaces defined.

Primary Clock: clk_i

Other Clocks: clk_aon_i

Bus Device Interfaces (TL-UL): tl

Bus Host Interfaces (TL-UL): none

Peripheral Pins for Chip IO: none

Inter-Module Signals: Reference

Inter-Module Signals
Port Name Package::Struct Type Act Width Description
nmi_wdog_timer_bark logic uni req 1
wkup_req logic uni req 1
aon_timer_rst_req logic uni req 1
lc_escalate_en lc_ctrl_pkg::lc_tx uni rcv 1
sleep_mode logic uni rcv 1
tl tlul_pkg::tl req_rsp rsp 1

Interrupts:

Interrupt NameTypeDescription
wkup_timer_expiredEvent

Raised if the wakeup timer has hit the specified threshold

wdog_timer_barkEvent

Raised if the watchdog timer has hit the bark threshold

Security Alerts:

Alert NameDescription
fatal_fault

This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures:

Countermeasure IDDescription
AON_TIMER.BUS.INTEGRITY

End-to-end bus integrity scheme.

Registers

Summary
Name Offset Length Description
aon_timer.ALERT_TEST 0x0 4

Alert Test Register

aon_timer.WKUP_CTRL 0x4 4

Wakeup Timer Control register

aon_timer.WKUP_THOLD 0x8 4

Wakeup Timer Threshold Register

aon_timer.WKUP_COUNT 0xc 4

Wakeup Timer Count Register

aon_timer.WDOG_REGWEN 0x10 4

Watchdog Timer Write Enable Register

aon_timer.WDOG_CTRL 0x14 4

Watchdog Timer Control register

aon_timer.WDOG_BARK_THOLD 0x18 4

Watchdog Timer Bark Threshold Register

aon_timer.WDOG_BITE_THOLD 0x1c 4

Watchdog Timer Bite Threshold Register

aon_timer.WDOG_COUNT 0x20 4

Watchdog Timer Count Register

aon_timer.INTR_STATE 0x24 4

Interrupt State Register

aon_timer.INTR_TEST 0x28 4

Interrupt Test Register

aon_timer.WKUP_CAUSE 0x2c 4

Wakeup request status

aon_timer.ALERT_TEST @ 0x0

Alert Test Register

Reset default = 0x0, mask 0x1
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  fatal_fault
BitsTypeResetNameDescription
0wo0x0fatal_fault

Write 1 to trigger one alert event of this kind.


aon_timer.WKUP_CTRL @ 0x4

Wakeup Timer Control register

Reset default = 0x0, mask 0x1fff
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  prescaler enable
BitsTypeResetNameDescription
0rw0x0enable

When set to 1, the wakeup timer will count

12:1rw0x0prescaler

Pre-scaler value for wakeup timer count


aon_timer.WKUP_THOLD @ 0x8

Wakeup Timer Threshold Register

Reset default = 0x0, mask 0xffffffff
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threshold...
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...threshold
BitsTypeResetNameDescription
31:0rw0x0threshold

The count at which a wakeup interrupt should be generated


aon_timer.WKUP_COUNT @ 0xc

Wakeup Timer Count Register

Reset default = 0x0, mask 0xffffffff
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count...
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...count
BitsTypeResetNameDescription
31:0rw0x0count

The current wakeup counter value


aon_timer.WDOG_REGWEN @ 0x10

Watchdog Timer Write Enable Register

Reset default = 0x1, mask 0x1
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  regwen
BitsTypeResetNameDescription
0rw0c0x1regwen

Once cleared, the watchdog configuration will be locked until the next reset


aon_timer.WDOG_CTRL @ 0x14

Watchdog Timer Control register

Reset default = 0x0, mask 0x3
Register enable = WDOG_REGWEN
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  pause_in_sleep enable
BitsTypeResetNameDescription
0rw0x0enable

When set to 1, the watchdog timer will count

1rw0x0pause_in_sleep

When set to 1, the watchdog timer will not count during sleep


aon_timer.WDOG_BARK_THOLD @ 0x18

Watchdog Timer Bark Threshold Register

Reset default = 0x0, mask 0xffffffff
Register enable = WDOG_REGWEN
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threshold...
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...threshold
BitsTypeResetNameDescription
31:0rw0x0threshold

The count at which a watchdog bark interrupt should be generated


aon_timer.WDOG_BITE_THOLD @ 0x1c

Watchdog Timer Bite Threshold Register

Reset default = 0x0, mask 0xffffffff
Register enable = WDOG_REGWEN
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threshold...
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...threshold
BitsTypeResetNameDescription
31:0rw0x0threshold

The count at which a watchdog bite reset should be generated


aon_timer.WDOG_COUNT @ 0x20

Watchdog Timer Count Register

Reset default = 0x0, mask 0xffffffff
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count...
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...count
BitsTypeResetNameDescription
31:0rw0x0count

The current watchdog counter value


aon_timer.INTR_STATE @ 0x24

Interrupt State Register

Reset default = 0x0, mask 0x3
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  wdog_timer_bark wkup_timer_expired
BitsTypeResetNameDescription
0rw1c0x0wkup_timer_expired

Raised if the wakeup timer has hit the specified threshold

1rw1c0x0wdog_timer_bark

Raised if the watchdog timer has hit the bark threshold


aon_timer.INTR_TEST @ 0x28

Interrupt Test Register

Reset default = 0x0, mask 0x3
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  wdog_timer_bark wkup_timer_expired
BitsTypeResetNameDescription
0woxwkup_timer_expired

Write 1 to force wkup_timer_expired interrupt

1woxwdog_timer_bark

Write 1 to force wdog_timer_bark interrupt


aon_timer.WKUP_CAUSE @ 0x2c

Wakeup request status

Reset default = 0x0, mask 0x1
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  cause
BitsTypeResetNameDescription
0rw0c0x0cause

AON timer requested wakeup, write 0 to clear