Referring to the Comportable guideline for peripheral device functionality, the module aon_timer has the following hardware interfaces defined
- Primary Clock:
clk_i
- Other Clocks:
clk_aon_i
- Bus Device Interfaces (TL-UL):
tl
- Bus Host Interfaces (TL-UL): none
- Peripheral Pins for Chip IO: none
| Port Name | Package::Struct | Type | Act | Width | Description |
|---|
| nmi_wdog_timer_bark | logic | uni | req | 1 | |
| wkup_req | logic | uni | req | 1 | |
| aon_timer_rst_req | logic | uni | req | 1 | |
| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | |
| sleep_mode | logic | uni | rcv | 1 | |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Interrupt Name | Type | Description |
|---|
| wkup_timer_expired | Event | Raised if the wakeup timer has hit the specified threshold |
| wdog_timer_bark | Event | Raised if the watchdog timer has hit the bark threshold |
| Alert Name | Description |
|---|
| fatal_fault | This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected. |
| Countermeasure ID | Description |
|---|
| AON_TIMER.BUS.INTEGRITY | End-to-end bus integrity scheme. |
Comportable IP ID.
- Offset:
0x0
- Reset default:
0x3
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | ro | 0x3 | CIP_ID | This value is a unique comportable IP identifier. |
Comportable IP semantic version.
- Offset:
0x4
- Reset default:
0x2000000
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:24 | ro | 0x2 | MAJOR | Major version number. |
| 23:16 | ro | 0x0 | MINOR | Minor version number. |
| 15:8 | ro | 0x0 | SUBMINOR | Subminor (patch) version number. |
| 7:0 | ro | 0x0 | RESERVED | Reserved version number. |
Parameter block type.
- Offset:
0x8
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | ro | 0x0 | BLOCK_TYPE | Parameter block type. |
Parameter block length.
- Offset:
0xc
- Reset default:
0xc
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | ro | 0xc | BLOCK_LENGTH | Parameter block length in bytes. |
Next parameter block offset.
- Offset:
0x10
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | ro | 0x0 | BLOCK_OFFSET | This offset value is zero if there is no other parameter block. |
Alert Test Register
- Offset:
0x40
- Reset default:
0x0
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | wo | 0x0 | fatal_fault | Write 1 to trigger one alert event of this kind. |
Wakeup Timer Control register
- Offset:
0x44
- Reset default:
0x0
- Reset mask:
0x1fff
| Bits | Type | Reset | Name | Description |
|---|
| 31:13 | | | | Reserved |
| 12:1 | rw | 0x0 | prescaler | Pre-scaler value for wakeup timer count |
| 0 | rw | 0x0 | enable | When set to 1, the wakeup timer will count |
Wakeup Timer Threshold Register
- Offset:
0x48
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0x0 | threshold | The count at which a wakeup interrupt should be generated |
Wakeup Timer Count Register
- Offset:
0x4c
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0x0 | count | The current wakeup counter value |
Watchdog Timer Write Enable Register
- Offset:
0x50
- Reset default:
0x1
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw0c | 0x1 | regwen | Once cleared, the watchdog configuration will be locked until the next reset |
Watchdog Timer Control register
- Offset:
0x54
- Reset default:
0x0
- Reset mask:
0x3
- Register enable:
WDOG_REGWEN
| Bits | Type | Reset | Name | Description |
|---|
| 31:2 | | | | Reserved |
| 1 | rw | 0x0 | pause_in_sleep | When set to 1, the watchdog timer will not count during sleep |
| 0 | rw | 0x0 | enable | When set to 1, the watchdog timer will count |
Watchdog Timer Bark Threshold Register
- Offset:
0x58
- Reset default:
0x0
- Reset mask:
0xffffffff
- Register enable:
WDOG_REGWEN
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0x0 | threshold | The count at which a watchdog bark interrupt should be generated |
Watchdog Timer Bite Threshold Register
- Offset:
0x5c
- Reset default:
0x0
- Reset mask:
0xffffffff
- Register enable:
WDOG_REGWEN
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0x0 | threshold | The count at which a watchdog bite reset should be generated |
Watchdog Timer Count Register
- Offset:
0x60
- Reset default:
0x0
- Reset mask:
0xffffffff
| Bits | Type | Reset | Name | Description |
|---|
| 31:0 | rw | 0x0 | count | The current watchdog counter value |
Interrupt State Register
- Offset:
0x64
- Reset default:
0x0
- Reset mask:
0x3
| Bits | Type | Reset | Name | Description |
|---|
| 31:2 | | | | Reserved |
| 1 | rw1c | 0x0 | wdog_timer_bark | Raised if the watchdog timer has hit the bark threshold |
| 0 | rw1c | 0x0 | wkup_timer_expired | Raised if the wakeup timer has hit the specified threshold |
Interrupt Test Register
- Offset:
0x68
- Reset default:
0x0
- Reset mask:
0x3
| Bits | Type | Reset | Name | Description |
|---|
| 31:2 | | | | Reserved |
| 1 | wo | x | wdog_timer_bark | Write 1 to force wdog_timer_bark interrupt |
| 0 | wo | x | wkup_timer_expired | Write 1 to force wkup_timer_expired interrupt |
Wakeup request status
- Offset:
0x6c
- Reset default:
0x0
- Reset mask:
0x1
| Bits | Type | Reset | Name | Description |
|---|
| 31:1 | | | | Reserved |
| 0 | rw0c | 0x0 | cause | AON timer requested wakeup, write 0 to clear |