Hardware Interfaces

Referring to the Comportable guideline for peripheral device functionality, the module aon_timer has the following hardware interfaces defined

  • Primary Clock: clk_i
  • Other Clocks: clk_aon_i
  • Bus Device Interfaces (TL-UL): tl
  • Bus Host Interfaces (TL-UL): none
  • Peripheral Pins for Chip IO: none

Inter-Module Signals

Port NamePackage::StructTypeActWidthDescription
nmi_wdog_timer_barklogicunireq1
wkup_reqlogicunireq1
aon_timer_rst_reqlogicunireq1
lc_escalate_enlc_ctrl_pkg::lc_txunircv1
sleep_modelogicunircv1
tltlul_pkg::tlreq_rsprsp1

Interrupts

Interrupt NameTypeDescription
wkup_timer_expiredEventRaised if the wakeup timer has hit the specified threshold
wdog_timer_barkEventRaised if the watchdog timer has hit the bark threshold

Security Alerts

Alert NameDescription
fatal_faultThis fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.

Security Countermeasures

Countermeasure IDDescription
AON_TIMER.BUS.INTEGRITYEnd-to-end bus integrity scheme.

Registers

Summary

NameOffsetLengthDescription
aon_timer.CIP_ID0x04Comportable IP ID.
aon_timer.REVISION0x44Comportable IP semantic version.
aon_timer.PARAMETER_BLOCK_TYPE0x84Parameter block type.
aon_timer.PARAMETER_BLOCK_LENGTH0xc4Parameter block length.
aon_timer.NEXT_PARAMETER_BLOCK0x104Next parameter block offset.
aon_timer.ALERT_TEST0x404Alert Test Register
aon_timer.WKUP_CTRL0x444Wakeup Timer Control register
aon_timer.WKUP_THOLD0x484Wakeup Timer Threshold Register
aon_timer.WKUP_COUNT0x4c4Wakeup Timer Count Register
aon_timer.WDOG_REGWEN0x504Watchdog Timer Write Enable Register
aon_timer.WDOG_CTRL0x544Watchdog Timer Control register
aon_timer.WDOG_BARK_THOLD0x584Watchdog Timer Bark Threshold Register
aon_timer.WDOG_BITE_THOLD0x5c4Watchdog Timer Bite Threshold Register
aon_timer.WDOG_COUNT0x604Watchdog Timer Count Register
aon_timer.INTR_STATE0x644Interrupt State Register
aon_timer.INTR_TEST0x684Interrupt Test Register
aon_timer.WKUP_CAUSE0x6c4Wakeup request status

CIP_ID

Comportable IP ID.

  • Offset: 0x0
  • Reset default: 0x3
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x3CIP_IDThis value is a unique comportable IP identifier.

REVISION

Comportable IP semantic version.

  • Offset: 0x4
  • Reset default: 0x2000000
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:24ro0x2MAJORMajor version number.
23:16ro0x0MINORMinor version number.
15:8ro0x0SUBMINORSubminor (patch) version number.
7:0ro0x0RESERVEDReserved version number.

PARAMETER_BLOCK_TYPE

Parameter block type.

  • Offset: 0x8
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x0BLOCK_TYPEParameter block type.

PARAMETER_BLOCK_LENGTH

Parameter block length.

  • Offset: 0xc
  • Reset default: 0xc
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0xcBLOCK_LENGTHParameter block length in bytes.

NEXT_PARAMETER_BLOCK

Next parameter block offset.

  • Offset: 0x10
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0ro0x0BLOCK_OFFSETThis offset value is zero if there is no other parameter block.

ALERT_TEST

Alert Test Register

  • Offset: 0x40
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0wo0x0fatal_faultWrite 1 to trigger one alert event of this kind.

WKUP_CTRL

Wakeup Timer Control register

  • Offset: 0x44
  • Reset default: 0x0
  • Reset mask: 0x1fff

Fields

BitsTypeResetNameDescription
31:13Reserved
12:1rw0x0prescalerPre-scaler value for wakeup timer count
0rw0x0enableWhen set to 1, the wakeup timer will count

WKUP_THOLD

Wakeup Timer Threshold Register

  • Offset: 0x48
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0thresholdThe count at which a wakeup interrupt should be generated

WKUP_COUNT

Wakeup Timer Count Register

  • Offset: 0x4c
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0countThe current wakeup counter value

WDOG_REGWEN

Watchdog Timer Write Enable Register

  • Offset: 0x50
  • Reset default: 0x1
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x1regwenOnce cleared, the watchdog configuration will be locked until the next reset

WDOG_CTRL

Watchdog Timer Control register

  • Offset: 0x54
  • Reset default: 0x0
  • Reset mask: 0x3
  • Register enable: WDOG_REGWEN

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw0x0pause_in_sleepWhen set to 1, the watchdog timer will not count during sleep
0rw0x0enableWhen set to 1, the watchdog timer will count

WDOG_BARK_THOLD

Watchdog Timer Bark Threshold Register

  • Offset: 0x58
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: WDOG_REGWEN

Fields

BitsTypeResetNameDescription
31:0rw0x0thresholdThe count at which a watchdog bark interrupt should be generated

WDOG_BITE_THOLD

Watchdog Timer Bite Threshold Register

  • Offset: 0x5c
  • Reset default: 0x0
  • Reset mask: 0xffffffff
  • Register enable: WDOG_REGWEN

Fields

BitsTypeResetNameDescription
31:0rw0x0thresholdThe count at which a watchdog bite reset should be generated

WDOG_COUNT

Watchdog Timer Count Register

  • Offset: 0x60
  • Reset default: 0x0
  • Reset mask: 0xffffffff

Fields

BitsTypeResetNameDescription
31:0rw0x0countThe current watchdog counter value

INTR_STATE

Interrupt State Register

  • Offset: 0x64
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1rw1c0x0wdog_timer_barkRaised if the watchdog timer has hit the bark threshold
0rw1c0x0wkup_timer_expiredRaised if the wakeup timer has hit the specified threshold

INTR_TEST

Interrupt Test Register

  • Offset: 0x68
  • Reset default: 0x0
  • Reset mask: 0x3

Fields

BitsTypeResetNameDescription
31:2Reserved
1woxwdog_timer_barkWrite 1 to force wdog_timer_bark interrupt
0woxwkup_timer_expiredWrite 1 to force wkup_timer_expired interrupt

WKUP_CAUSE

Wakeup request status

  • Offset: 0x6c
  • Reset default: 0x0
  • Reset mask: 0x1

Fields

BitsTypeResetNameDescription
31:1Reserved
0rw0c0x0causeAON timer requested wakeup, write 0 to clear