OpenTitan Top Levels
OpenTitan features pre-assembled top level designs that our partners have decided to put together as part of the project.
These top levels address system-level security issues, and provide transparency for our partners’ secure chips or subsystems.
OpenTitan top levels are the best starting point to integrate OpenTitan IP in an SoC, since they have been verified as a system and, in some cases, proven in silicon.
Top Level: Earl Grey 2
01 / PQC + CHERIBuilding on the success of the production-ready Earl Grey, OpenTitan Earl Grey 2 is addressing the new security challenges introduced by Artificial Intelligence and future quantum computers.
✪ Hardware memory safety through the addition of Capability Hardware Enhanced RISC Instructions (CHERI)
✪ Security-hardened and optimized Post-Quantum Cryptography (PQC) compatible with CNSA 2.0, through extensions to its crypto accelerators
✪ Advanced control plane I/O with the addition of an I3C controller and target to address peripheral bottlenecks
✪ Greater efficiency, reducing area and power consumption through process node updates, compressed instructions, IP block optimizations and power domain splitting
Top Level: Earl Grey
02 / StandaloneThe OpenTitan Earl Grey chip is a low-power secure microcontroller which is in production.
It has been hardened against physical attacks (SCA/FI) and can be used for many applications where security is important (e.g. as a Root-of-Trust)
v.1.0.0: Earl Grey release 1.0.0, first OpenTitan production silicon
Top Level: Darjeeling
03 / IntegratedOpenTitan Darjeeling is an SoC Secure Execution Environment.
It has been used in production devices by Rivos, but it requires further design verification.
