OpenTitan IP

OpenTitan Top Levels

OpenTitan features pre-assembled top level designs that our partners have decided to put together as part of the project.

These top levels address system-level security issues, and provide transparency for our partners’ secure chips or subsystems.

OpenTitan top levels are the best starting point to integrate OpenTitan IP in an SoC, since they have been verified as a system and, in some cases, proven in silicon.

OpenTitan chip in production silicon
OpenTitan silicon · shipping in Chromebooks

Top Level: Earl Grey

01 / Standalone

The OpenTitan Earl Grey chip is a low-power secure microcontroller which is in production.

It has been hardened against physical attacks (SCA/FI) and can be used for many applications where security is important (e.g. as a Root-of-Trust)

Datasheet →

OpenTitan Earl Grey block diagram
Earl Grey · standalone secure microcontroller

Top Level: Darjeeling

02 / Integrated

OpenTitan Darjeeling is an SoC Secure Execution Environment.

It has been used in production devices by Rivos, but it requires further design verification.

Datasheet →

OpenTitan Darjeeling block diagram
Darjeeling · integrated secure execution environment